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drm/msm/a6xx: Store correct gmu_cgc_mode in struct a6xx_info

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Store the correct values that we happen to have for some A7xx SKUs in
the GPU info struct and fill out the missing information for A6xx GPUs
based on downstream kernel information.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611094/
[add missing entry to a615 catalog to resolve conflict]
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Konrad Dybcio 2024-08-28 17:06:56 +02:00 committed by Rob Clark
parent 2bbb5fe390
commit d50a8363c2
2 changed files with 20 additions and 0 deletions
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19
drivers/gpu/drm/msm/adreno/a6xx_catalog.c
View File

@ -636,6 +636,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a612_hwcg,
.protect = &a630_protect,
.gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00080000,
},
/*
@ -667,6 +668,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
.gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x0018000,
},
.speedbins = ADRENO_SPEEDBINS(
@ -696,6 +698,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
.gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00180000,
},
.speedbins = ADRENO_SPEEDBINS(
@ -719,6 +722,7 @@ static const struct adreno_info a6xx_gpus[] = {
.init = a6xx_gpu_init,
.a6xx = &(const struct a6xx_info) {
.protect = &a630_protect,
.gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00180000,
},
.speedbins = ADRENO_SPEEDBINS(
@ -742,6 +746,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
.gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00018000,
},
.speedbins = ADRENO_SPEEDBINS(
@ -765,6 +770,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
.gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00018000,
},
.speedbins = ADRENO_SPEEDBINS(
@ -788,6 +794,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
.gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00018000,
},
.speedbins = ADRENO_SPEEDBINS(
@ -816,6 +823,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a630_hwcg,
.protect = &a630_protect,
.gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00180000,
},
}, {
@ -834,6 +842,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a640_hwcg,
.protect = &a630_protect,
.gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00180000,
},
.speedbins = ADRENO_SPEEDBINS(
@ -857,6 +866,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a650_hwcg,
.protect = &a650_protect,
.gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00300200,
},
.address_space_size = SZ_16G,
@ -883,6 +893,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a660_hwcg,
.protect = &a660_protect,
.gmu_cgc_mode = 0x00020000,
.prim_fifo_threshold = 0x00300200,
},
.address_space_size = SZ_16G,
@ -902,6 +913,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a660_hwcg,
.protect = &a660_protect,
.gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00200200,
},
.address_space_size = SZ_16G,
@ -928,6 +940,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a640_hwcg,
.protect = &a630_protect,
.gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00200200,
},
}, {
@ -946,6 +959,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a690_hwcg,
.protect = &a690_protect,
.gmu_cgc_mode = 0x00020200,
.prim_fifo_threshold = 0x00800200,
},
.address_space_size = SZ_16G,
@ -1207,6 +1221,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a702_hwcg,
.protect = &a650_protect,
.gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x0000c000,
},
.speedbins = ADRENO_SPEEDBINS(
@ -1231,6 +1246,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a730_hwcg,
.protect = &a730_protect,
.gmu_cgc_mode = 0x00020000,
},
.address_space_size = SZ_16G,
}, {
@ -1250,6 +1266,7 @@ static const struct adreno_info a7xx_gpus[] = {
.hwcg = a740_hwcg,
.protect = &a730_protect,
.gmu_chipid = 0x7020100,
.gmu_cgc_mode = 0x00020202,
},
.address_space_size = SZ_16G,
}, {
@ -1268,6 +1285,7 @@ static const struct adreno_info a7xx_gpus[] = {
.hwcg = a740_hwcg,
.protect = &a730_protect,
.gmu_chipid = 0x7050001,
.gmu_cgc_mode = 0x00020202,
},
.address_space_size = SZ_256G,
}, {
@ -1286,6 +1304,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.protect = &a730_protect,
.gmu_chipid = 0x7090100,
.gmu_cgc_mode = 0x00020202,
},
.address_space_size = SZ_16G,
}

1
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
View File

@ -22,6 +22,7 @@ struct a6xx_info {
const struct adreno_reglist *hwcg;
const struct adreno_protect *protect;
u32 gmu_chipid;
u32 gmu_cgc_mode;
u32 prim_fifo_threshold;
};