mirror of
https://github.com/torvalds/linux.git
synced 2024-11-11 22:51:42 +00:00
Merge branch 'next/late' with mainline
* next/late: (25 commits) arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7 pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e ARM64: dts: meson-gxbb-p200: add ADC laddered keys ARM64: dts: meson: meson-gx: add the SAR ADC ARM64: dts: meson-gxl: add the pwm_ao_b pin ARM64: dts: meson-gx: add the missing pwm_AO_ab node clk: gxbb: fix CLKID_ETH defined twice clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks ARM64: dts: meson-gxl: rename Nexbox A95x for consistency clk: gxbb: add the SAR ADC clocks and expose them dt-bindings: amlogic: Add WeTek boards ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play dt-bindings: vendor-prefix: Add wetek vendor prefix ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes ARM64: dts: meson-gxbb-vega-s95: Add LED ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
d4b80d9aac
@ -40,6 +40,8 @@ Board compatible values:
|
||||
- "hardkernel,odroid-c2" (Meson gxbb)
|
||||
- "amlogic,p200" (Meson gxbb)
|
||||
- "amlogic,p201" (Meson gxbb)
|
||||
- "wetek,hub" (Meson gxbb)
|
||||
- "wetek,play2" (Meson gxbb)
|
||||
- "amlogic,p212" (Meson gxl s905x)
|
||||
- "amlogic,p230" (Meson gxl s905d)
|
||||
- "amlogic,p231" (Meson gxl s905d)
|
||||
|
||||
@ -329,6 +329,7 @@ virtio Virtual I/O Device Specification, developed by the OASIS consortium
|
||||
vivante Vivante Corporation
|
||||
voipac Voipac Technologies s.r.o.
|
||||
wd Western Digital Corp.
|
||||
wetek WeTek Electronics, limited.
|
||||
wexler Wexler
|
||||
winbond Winbond Electronics corp.
|
||||
wlf Wolfson Microelectronics
|
||||
|
||||
@ -5,12 +5,14 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-nexbox-a95x.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q200.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q201.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q201.dtb
|
||||
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
|
||||
@ -83,6 +83,7 @@
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
@ -91,6 +92,7 @@
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
@ -99,6 +101,7 @@
|
||||
reg = <0x0 0x2>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
@ -107,6 +110,7 @@
|
||||
reg = <0x0 0x3>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
|
||||
l2: l2-cache0 {
|
||||
@ -171,6 +175,28 @@
|
||||
};
|
||||
};
|
||||
|
||||
scpi {
|
||||
compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
|
||||
mboxes = <&mailbox 1 &mailbox 2>;
|
||||
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
|
||||
|
||||
scpi_clocks: clocks {
|
||||
compatible = "arm,scpi-clocks";
|
||||
|
||||
scpi_dvfs: scpi_clocks@0 {
|
||||
compatible = "arm,scpi-dvfs-clocks";
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <0>;
|
||||
clock-output-names = "vcpu";
|
||||
};
|
||||
};
|
||||
|
||||
scpi_sensors: sensors {
|
||||
compatible = "arm,scpi-sensors";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
@ -229,6 +255,14 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
saradc: adc@8680 {
|
||||
compatible = "amlogic,meson-saradc";
|
||||
reg = <0x0 0x8680 0x0 0x34>;
|
||||
#io-channel-cells = <1>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm_ef: pwm@86c0 {
|
||||
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
|
||||
reg = <0x0 0x086c0 0x0 0x10>;
|
||||
@ -282,6 +316,25 @@
|
||||
#address-cells = <0>;
|
||||
};
|
||||
|
||||
sram: sram@c8000000 {
|
||||
compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
|
||||
reg = <0x0 0xc8000000 0x0 0x14000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0xc8000000 0x14000>;
|
||||
|
||||
cpu_scp_lpri: scp-shmem@0 {
|
||||
compatible = "amlogic,meson-gxbb-scp-shmem";
|
||||
reg = <0x13000 0x400>;
|
||||
};
|
||||
|
||||
cpu_scp_hpri: scp-shmem@200 {
|
||||
compatible = "amlogic,meson-gxbb-scp-shmem";
|
||||
reg = <0x13400 0x400>;
|
||||
};
|
||||
};
|
||||
|
||||
aobus: aobus@c8100000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x0 0xc8100000 0x0 0x100000>;
|
||||
@ -297,6 +350,21 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart_AO_B: serial@4e0 {
|
||||
compatible = "amlogic,meson-uart";
|
||||
reg = <0x0 0x004e0 0x0 0x14>;
|
||||
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
|
||||
clocks = <&xtal>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm_AO_ab: pwm@550 {
|
||||
compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
|
||||
reg = <0x0 0x00550 0x0 0x10>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ir: ir@580 {
|
||||
compatible = "amlogic,meson-gxbb-ir";
|
||||
reg = <0x0 0x00580 0x0 0x40>;
|
||||
|
||||
@ -45,10 +45,55 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "meson-gxbb-p20x.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
compatible = "amlogic,p200", "amlogic,meson-gxbb";
|
||||
model = "Amlogic Meson GXBB P200 Development Board";
|
||||
|
||||
avdd18_usb_adc: regulator-avdd18_usb_adc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "AVDD18_USB_ADC";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
adc_keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 0>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1800000>;
|
||||
|
||||
button-home {
|
||||
label = "Home";
|
||||
linux,code = <KEY_HOME>;
|
||||
press-threshold-microvolt = <900000>; /* 50% */
|
||||
};
|
||||
|
||||
button-esc {
|
||||
label = "Esc";
|
||||
linux,code = <KEY_ESC>;
|
||||
press-threshold-microvolt = <684000>; /* 38% */
|
||||
};
|
||||
|
||||
button-up {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
press-threshold-microvolt = <468000>; /* 26% */
|
||||
};
|
||||
|
||||
button-down {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
press-threshold-microvolt = <252000>; /* 14% */
|
||||
};
|
||||
|
||||
button-menu {
|
||||
label = "Menu";
|
||||
linux,code = <KEY_MENU>;
|
||||
press-threshold-microvolt = <0>; /* 0% */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_B {
|
||||
@ -56,3 +101,8 @@
|
||||
pinctrl-0 = <&i2c_b_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
vref-supply = <&avdd18_usb_adc>;
|
||||
};
|
||||
|
||||
@ -53,6 +53,17 @@
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
blue {
|
||||
label = "vega-s95:blue:on";
|
||||
gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
panic-indicator;
|
||||
};
|
||||
};
|
||||
|
||||
usb_vbus: regulator-usb0-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
|
||||
66
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
Normal file
66
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
Normal file
@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright (c) 2016 BayLibre, Inc.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "meson-gxbb-p20x.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "wetek,hub", "amlogic,meson-gxbb";
|
||||
model = "WeTek Hub";
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
system {
|
||||
label = "wetek-play:system-status";
|
||||
gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
panic-indicator;
|
||||
};
|
||||
};
|
||||
|
||||
cvbs-connector {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
94
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
Normal file
94
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
Normal file
@ -0,0 +1,94 @@
|
||||
/*
|
||||
* Copyright (c) 2016 BayLibre, Inc.
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "meson-gxbb-p20x.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
compatible = "wetek,play2", "amlogic,meson-gxbb";
|
||||
model = "WeTek Play 2";
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
system {
|
||||
label = "wetek-play:system-status";
|
||||
gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
panic-indicator;
|
||||
};
|
||||
|
||||
wifi {
|
||||
label = "wetek-play:wifi-status";
|
||||
gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
ethernet {
|
||||
label = "wetek-play:ethernet-status";
|
||||
gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys-polled {
|
||||
compatible = "gpio-keys-polled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
poll-interval = <100>;
|
||||
|
||||
button@0 {
|
||||
label = "reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c_A {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&i2c_a_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
@ -50,28 +50,6 @@
|
||||
/ {
|
||||
compatible = "amlogic,meson-gxbb";
|
||||
|
||||
scpi {
|
||||
compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
|
||||
mboxes = <&mailbox 1 &mailbox 2>;
|
||||
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
|
||||
|
||||
scpi_clocks: clocks {
|
||||
compatible = "arm,scpi-clocks";
|
||||
|
||||
scpi_dvfs: scpi_clocks@0 {
|
||||
compatible = "arm,scpi-dvfs-clocks";
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <0>;
|
||||
clock-output-names = "vcpu";
|
||||
};
|
||||
};
|
||||
|
||||
scpi_sensors: sensors {
|
||||
compatible = "arm,scpi-sensors";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
usb0_phy: phy@c0000000 {
|
||||
compatible = "amlogic,meson-gxbb-usb2-phy";
|
||||
@ -93,25 +71,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sram: sram@c8000000 {
|
||||
compatible = "amlogic,meson-gxbb-sram", "mmio-sram";
|
||||
reg = <0x0 0xc8000000 0x0 0x14000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0xc8000000 0x14000>;
|
||||
|
||||
cpu_scp_lpri: scp-shmem@0 {
|
||||
compatible = "amlogic,meson-gxbb-scp-shmem";
|
||||
reg = <0x13000 0x400>;
|
||||
};
|
||||
|
||||
cpu_scp_hpri: scp-shmem@200 {
|
||||
compatible = "amlogic,meson-gxbb-scp-shmem";
|
||||
reg = <0x13400 0x400>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: usb@c9000000 {
|
||||
compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
|
||||
reg = <0x0 0xc9000000 0x0 0x40000>;
|
||||
@ -138,22 +97,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
clocks = <&scpi_dvfs 0>;
|
||||
};
|
||||
|
||||
&cbus {
|
||||
spifc: spi@8c80 {
|
||||
compatible = "amlogic,meson-gxbb-spifc";
|
||||
@ -195,6 +138,29 @@
|
||||
};
|
||||
};
|
||||
|
||||
uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
|
||||
mux {
|
||||
groups = "uart_cts_ao_a",
|
||||
"uart_rts_ao_a";
|
||||
function = "uart_ao";
|
||||
};
|
||||
};
|
||||
|
||||
uart_ao_b_pins: uart_ao_b {
|
||||
mux {
|
||||
groups = "uart_tx_ao_b", "uart_rx_ao_b";
|
||||
function = "uart_ao_b";
|
||||
};
|
||||
};
|
||||
|
||||
uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
|
||||
mux {
|
||||
groups = "uart_cts_ao_b",
|
||||
"uart_rts_ao_b";
|
||||
function = "uart_ao_b";
|
||||
};
|
||||
};
|
||||
|
||||
remote_input_ao_pins: remote_input_ao {
|
||||
mux {
|
||||
groups = "remote_input_ao";
|
||||
@ -340,6 +306,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
uart_a_cts_rts_pins: uart_a_cts_rts {
|
||||
mux {
|
||||
groups = "uart_cts_a",
|
||||
"uart_rts_a";
|
||||
function = "uart_a";
|
||||
};
|
||||
};
|
||||
|
||||
uart_b_pins: uart_b {
|
||||
mux {
|
||||
groups = "uart_tx_b",
|
||||
@ -348,6 +322,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
uart_b_cts_rts_pins: uart_b_cts_rts {
|
||||
mux {
|
||||
groups = "uart_cts_b",
|
||||
"uart_rts_b";
|
||||
function = "uart_b";
|
||||
};
|
||||
};
|
||||
|
||||
uart_c_pins: uart_c {
|
||||
mux {
|
||||
groups = "uart_tx_c",
|
||||
@ -356,6 +338,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
uart_c_cts_rts_pins: uart_c_cts_rts {
|
||||
mux {
|
||||
groups = "uart_cts_c",
|
||||
"uart_rts_c";
|
||||
function = "uart_c";
|
||||
};
|
||||
};
|
||||
|
||||
i2c_a_pins: i2c_a {
|
||||
mux {
|
||||
groups = "i2c_sck_a",
|
||||
@ -463,6 +453,20 @@
|
||||
function = "pwm_f_y";
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_hpd_pins: hdmi_hpd {
|
||||
mux {
|
||||
groups = "hdmi_hpd";
|
||||
function = "hdmi_hpd";
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_i2c_pins: hdmi_i2c {
|
||||
mux {
|
||||
groups = "hdmi_sda", "hdmi_scl";
|
||||
function = "hdmi_i2c";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -486,6 +490,16 @@
|
||||
clocks = <&clkc CLKID_I2C>;
|
||||
};
|
||||
|
||||
&saradc {
|
||||
compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
|
||||
clocks = <&xtal>,
|
||||
<&clkc CLKID_SAR_ADC>,
|
||||
<&clkc CLKID_SANA>,
|
||||
<&clkc CLKID_SAR_ADC_CLK>,
|
||||
<&clkc CLKID_SAR_ADC_SEL>;
|
||||
clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
|
||||
};
|
||||
|
||||
&sd_emmc_a {
|
||||
clocks = <&clkc CLKID_SD_EMMC_A>,
|
||||
<&xtal>,
|
||||
|
||||
@ -88,12 +88,42 @@
|
||||
};
|
||||
};
|
||||
|
||||
uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
|
||||
mux {
|
||||
groups = "uart_cts_ao_a",
|
||||
"uart_rts_ao_a";
|
||||
function = "uart_ao";
|
||||
};
|
||||
};
|
||||
|
||||
uart_ao_b_pins: uart_ao_b {
|
||||
mux {
|
||||
groups = "uart_tx_ao_b", "uart_rx_ao_b";
|
||||
function = "uart_ao_b";
|
||||
};
|
||||
};
|
||||
|
||||
uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
|
||||
mux {
|
||||
groups = "uart_cts_ao_b",
|
||||
"uart_rts_ao_b";
|
||||
function = "uart_ao_b";
|
||||
};
|
||||
};
|
||||
|
||||
remote_input_ao_pins: remote_input_ao {
|
||||
mux {
|
||||
groups = "remote_input_ao";
|
||||
function = "remote_input_ao";
|
||||
};
|
||||
};
|
||||
|
||||
pwm_ao_b_pins: pwm_ao_b {
|
||||
mux {
|
||||
groups = "pwm_ao_b";
|
||||
function = "pwm_ao_b";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -163,6 +193,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
uart_a_cts_rts_pins: uart_a_cts_rts {
|
||||
mux {
|
||||
groups = "uart_cts_a",
|
||||
"uart_rts_a";
|
||||
function = "uart_a";
|
||||
};
|
||||
};
|
||||
|
||||
uart_b_pins: uart_b {
|
||||
mux {
|
||||
groups = "uart_tx_b",
|
||||
@ -171,6 +209,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
uart_b_cts_rts_pins: uart_b_cts_rts {
|
||||
mux {
|
||||
groups = "uart_cts_b",
|
||||
"uart_rts_b";
|
||||
function = "uart_b";
|
||||
};
|
||||
};
|
||||
|
||||
uart_c_pins: uart_c {
|
||||
mux {
|
||||
groups = "uart_tx_c",
|
||||
@ -179,6 +225,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
uart_c_cts_rts_pins: uart_c_cts_rts {
|
||||
mux {
|
||||
groups = "uart_cts_c",
|
||||
"uart_rts_c";
|
||||
function = "uart_c";
|
||||
};
|
||||
};
|
||||
|
||||
i2c_a_pins: i2c_a {
|
||||
mux {
|
||||
groups = "i2c_sck_a",
|
||||
@ -229,6 +283,20 @@
|
||||
function = "pwm_e";
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_hpd_pins: hdmi_hpd {
|
||||
mux {
|
||||
groups = "hdmi_hpd";
|
||||
function = "hdmi_hpd";
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_i2c_pins: hdmi_i2c {
|
||||
mux {
|
||||
groups = "hdmi_sda", "hdmi_scl";
|
||||
function = "hdmi_i2c";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eth-phy-mux {
|
||||
@ -279,6 +347,16 @@
|
||||
clocks = <&clkc CLKID_I2C>;
|
||||
};
|
||||
|
||||
&saradc {
|
||||
compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
|
||||
clocks = <&xtal>,
|
||||
<&clkc CLKID_SAR_ADC>,
|
||||
<&clkc CLKID_SANA>,
|
||||
<&clkc CLKID_SAR_ADC_CLK>,
|
||||
<&clkc CLKID_SAR_ADC_SEL>;
|
||||
clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
|
||||
};
|
||||
|
||||
&sd_emmc_a {
|
||||
clocks = <&clkc CLKID_SD_EMMC_A>,
|
||||
<&xtal>,
|
||||
|
||||
@ -85,6 +85,7 @@
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
};
|
||||
|
||||
cpu5: cpu@101 {
|
||||
@ -93,6 +94,7 @@
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
};
|
||||
|
||||
cpu6: cpu@102 {
|
||||
@ -101,6 +103,7 @@
|
||||
reg = <0x0 0x102>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
};
|
||||
|
||||
cpu7: cpu@103 {
|
||||
@ -109,10 +112,21 @@
|
||||
reg = <0x0 0x103>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&l2>;
|
||||
clocks = <&scpi_dvfs 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&saradc {
|
||||
compatible = "amlogic,meson-gxm-saradc", "amlogic,meson-saradc";
|
||||
};
|
||||
|
||||
&scpi_dvfs {
|
||||
clock-indices = <0 1>;
|
||||
clock-output-names = "vbig", "vlittle";
|
||||
};
|
||||
|
||||
&vpu {
|
||||
compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu";
|
||||
};
|
||||
|
||||
|
||||
@ -217,18 +217,6 @@
|
||||
assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
|
||||
};
|
||||
|
||||
&cmu_disp {
|
||||
assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
|
||||
<&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
|
||||
assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
|
||||
<0>,
|
||||
<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
|
||||
assigned-clock-rates = <0>, <400000000>;
|
||||
};
|
||||
|
||||
&cmu_fsys {
|
||||
assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
|
||||
<&cmu_top CLK_MOUT_SCLK_USBHOST30>,
|
||||
|
||||
@ -18,6 +18,40 @@
|
||||
compatible = "samsung,tm2", "samsung,exynos5433";
|
||||
};
|
||||
|
||||
&cmu_disp {
|
||||
/*
|
||||
* TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
|
||||
* clocks properties for DISP CMU for each board to keep them together
|
||||
* for easier review and maintenance.
|
||||
*/
|
||||
assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
|
||||
<&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
|
||||
<&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DSIM0>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
|
||||
<&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
|
||||
<&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
|
||||
<&cmu_disp CLK_MOUT_DISP_PLL>,
|
||||
<&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
|
||||
assigned-clock-parents = <0>, <0>,
|
||||
<&cmu_mif CLK_ACLK_DISP_333>,
|
||||
<&cmu_mif CLK_SCLK_DSIM0_DISP>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
|
||||
<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
|
||||
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
|
||||
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
|
||||
<&cmu_disp CLK_FOUT_DISP_PLL>,
|
||||
<&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
|
||||
<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
|
||||
assigned-clock-rates = <250000000>, <400000000>;
|
||||
};
|
||||
|
||||
&hsi2c_9 {
|
||||
status = "okay";
|
||||
|
||||
|
||||
@ -18,6 +18,40 @@
|
||||
compatible = "samsung,tm2e", "samsung,exynos5433";
|
||||
};
|
||||
|
||||
&cmu_disp {
|
||||
/*
|
||||
* TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
|
||||
* clocks properties for DISP CMU for each board to keep them together
|
||||
* for easier review and maintenance.
|
||||
*/
|
||||
assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
|
||||
<&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
|
||||
<&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DSIM0>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
|
||||
<&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
|
||||
<&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
|
||||
<&cmu_disp CLK_MOUT_DISP_PLL>,
|
||||
<&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
|
||||
assigned-clock-parents = <0>, <0>,
|
||||
<&cmu_mif CLK_ACLK_DISP_333>,
|
||||
<&cmu_mif CLK_SCLK_DSIM0_DISP>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
|
||||
<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
|
||||
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
|
||||
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
|
||||
<&cmu_disp CLK_FOUT_DISP_PLL>,
|
||||
<&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
|
||||
<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
|
||||
<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
|
||||
assigned-clock-rates = <278000000>, <400000000>;
|
||||
};
|
||||
|
||||
&ldo31_reg {
|
||||
regulator-name = "TSP_VDD_1.8V_AP";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
#include "exynos7.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/samsung,s2mps11.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Samsung Exynos7 Espresso board based on EXYNOS7";
|
||||
@ -32,6 +33,29 @@
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0x0 0xC0000000>;
|
||||
};
|
||||
|
||||
usb30_vbus_reg: regulator-usb30 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VBUS_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gph1 1 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb30_vbus_en>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
usb3drd_boost_5v: regulator-usb3drd-boost {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VUSB_VBUS_5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpf4 1 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb3drd_boost_en>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&fin_pll {
|
||||
@ -328,8 +352,8 @@
|
||||
&pinctrl_alive {
|
||||
pmic_irq: pmic-irq {
|
||||
samsung,pins = "gpa0-2";
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -365,3 +389,24 @@
|
||||
vqmmc-supply = <&ldo2_reg>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&pinctrl_bus1 {
|
||||
usb30_vbus_en: usb30-vbus-en {
|
||||
samsung,pins = "gph1-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
usb3drd_boost_en: usb3drd-boost-en {
|
||||
samsung,pins = "gpf4-1";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbdrd_phy {
|
||||
vbus-supply = <&usb30_vbus_reg>;
|
||||
vbus-boost-supply = <&usb3drd_boost_5v>;
|
||||
};
|
||||
|
||||
@ -12,6 +12,8 @@
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/samsung.h>
|
||||
|
||||
&pinctrl_alive {
|
||||
gpa0: gpa0 {
|
||||
gpio-controller;
|
||||
@ -187,163 +189,163 @@
|
||||
|
||||
hs_i2c10_bus: hs-i2c10-bus {
|
||||
samsung,pins = "gpb0-1", "gpb0-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c11_bus: hs-i2c11-bus {
|
||||
samsung,pins = "gpb0-3", "gpb0-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c2_bus: hs-i2c2-bus {
|
||||
samsung,pins = "gpd0-3", "gpd0-2";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart0_data: uart0-data {
|
||||
samsung,pins = "gpd0-0", "gpd0-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart0_fctl: uart0-fctl {
|
||||
samsung,pins = "gpd0-2", "gpd0-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart2_data: uart2-data {
|
||||
samsung,pins = "gpd1-4", "gpd1-5";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c3_bus: hs-i2c3-bus {
|
||||
samsung,pins = "gpd1-3", "gpd1-2";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart1_data: uart1-data {
|
||||
samsung,pins = "gpd1-0", "gpd1-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart1_fctl: uart1-fctl {
|
||||
samsung,pins = "gpd1-2", "gpd1-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c0_bus: hs-i2c0-bus {
|
||||
samsung,pins = "gpd2-1", "gpd2-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c1_bus: hs-i2c1-bus {
|
||||
samsung,pins = "gpd2-3", "gpd2-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c9_bus: hs-i2c9-bus {
|
||||
samsung,pins = "gpd2-7", "gpd2-6";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
pwm0_out: pwm0-out {
|
||||
samsung,pins = "gpd2-4";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
pwm1_out: pwm1-out {
|
||||
samsung,pins = "gpd2-5";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
pwm2_out: pwm2-out {
|
||||
samsung,pins = "gpd2-6";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
pwm3_out: pwm3-out {
|
||||
samsung,pins = "gpd2-7";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c8_bus: hs-i2c8-bus {
|
||||
samsung,pins = "gpd5-3", "gpd5-2";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
uart3_data: uart3-data {
|
||||
samsung,pins = "gpd5-0", "gpd5-1";
|
||||
samsung,pin-function = <3>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
spi2_bus: spi2-bus {
|
||||
samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
spi1_bus: spi1-bus {
|
||||
samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
spi0_bus: spi0-bus {
|
||||
samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c4_bus: hs-i2c4-bus {
|
||||
samsung,pins = "gpg3-1", "gpg3-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
hs_i2c5_bus: hs-i2c5-bus {
|
||||
samsung,pins = "gpg3-3", "gpg3-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -358,9 +360,9 @@
|
||||
|
||||
hs_i2c6_bus: hs-i2c6-bus {
|
||||
samsung,pins = "gpj0-1", "gpj0-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -375,9 +377,9 @@
|
||||
|
||||
hs_i2c7_bus: hs-i2c7-bus {
|
||||
samsung,pins = "gpj1-1", "gpj1-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -392,9 +394,9 @@
|
||||
|
||||
spi3_bus: spi3-bus {
|
||||
samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -409,9 +411,9 @@
|
||||
|
||||
spi4_bus: spi4-bus {
|
||||
samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -426,37 +428,37 @@
|
||||
|
||||
sd2_clk: sd2-clk {
|
||||
samsung,pins = "gpr4-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <3>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
|
||||
};
|
||||
|
||||
sd2_cmd: sd2-cmd {
|
||||
samsung,pins = "gpr4-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <3>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
|
||||
};
|
||||
|
||||
sd2_cd: sd2-cd {
|
||||
samsung,pins = "gpr4-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
|
||||
};
|
||||
|
||||
sd2_bus1: sd2-bus-width1 {
|
||||
samsung,pins = "gpr4-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
|
||||
};
|
||||
|
||||
sd2_bus4: sd2-bus-width4 {
|
||||
samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <3>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -495,107 +497,107 @@
|
||||
|
||||
sd0_clk: sd0-clk {
|
||||
samsung,pins = "gpr0-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <4>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
sd0_cmd: sd0-cmd {
|
||||
samsung,pins = "gpr0-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <4>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
sd0_ds: sd0-ds {
|
||||
samsung,pins = "gpr0-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <1>;
|
||||
samsung,pin-drv = <4>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
sd0_qrdy: sd0-qrdy {
|
||||
samsung,pins = "gpr0-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <1>;
|
||||
samsung,pin-drv = <4>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
sd0_bus1: sd0-bus-width1 {
|
||||
samsung,pins = "gpr1-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <4>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
sd0_bus4: sd0-bus-width4 {
|
||||
samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <4>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
sd0_bus8: sd0-bus-width8 {
|
||||
samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <4>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
sd1_clk: sd1-clk {
|
||||
samsung,pins = "gpr2-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <2>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
|
||||
};
|
||||
|
||||
sd1_cmd: sd1-cmd {
|
||||
samsung,pins = "gpr2-1";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <2>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
|
||||
};
|
||||
|
||||
sd1_ds: sd1-ds {
|
||||
samsung,pins = "gpr2-2";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <1>;
|
||||
samsung,pin-drv = <6>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV4>;
|
||||
};
|
||||
|
||||
sd1_qrdy: sd1-qrdy {
|
||||
samsung,pins = "gpr2-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <1>;
|
||||
samsung,pin-drv = <6>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV4>;
|
||||
};
|
||||
|
||||
sd1_int: sd1-int {
|
||||
samsung,pins = "gpr2-4";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <1>;
|
||||
samsung,pin-drv = <6>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV4>;
|
||||
};
|
||||
|
||||
sd1_bus1: sd1-bus-width1 {
|
||||
samsung,pins = "gpr3-0";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <2>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
|
||||
};
|
||||
|
||||
sd1_bus4: sd1-bus-width4 {
|
||||
samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <2>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
|
||||
};
|
||||
|
||||
sd1_bus8: sd1-bus-width8 {
|
||||
samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <2>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -682,22 +684,22 @@
|
||||
|
||||
spi5_bus: spi5-bus {
|
||||
samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
ufs_refclk_out: ufs-refclk-out {
|
||||
samsung,pins = "gpg2-4";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <0>;
|
||||
samsung,pin-drv = <2>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
|
||||
};
|
||||
|
||||
ufs_rst_n: ufs-rst-n {
|
||||
samsung,pins = "gph1-5";
|
||||
samsung,pin-function = <2>;
|
||||
samsung,pin-pud = <3>;
|
||||
samsung,pin-drv = <0>;
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
|
||||
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -603,6 +603,40 @@
|
||||
#include "exynos7-trip-points.dtsi"
|
||||
};
|
||||
};
|
||||
|
||||
usbdrd_phy: phy@15500000 {
|
||||
compatible = "samsung,exynos7-usbdrd-phy";
|
||||
reg = <0x15500000 0x100>;
|
||||
clocks = <&clock_fsys0 ACLK_USBDRD300>,
|
||||
<&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
|
||||
<&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
|
||||
<&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
|
||||
<&clock_fsys0 SCLK_USBDRD300_REFCLK>;
|
||||
clock-names = "phy", "ref", "phy_pipe",
|
||||
"phy_utmi", "itp";
|
||||
samsung,pmu-syscon = <&pmu_system_controller>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
usbdrd3 {
|
||||
compatible = "samsung,exynos7-dwusb3";
|
||||
clocks = <&clock_fsys0 ACLK_USBDRD300>,
|
||||
<&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
|
||||
<&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
|
||||
clock-names = "usbdrd30", "usbdrd30_susp_clk",
|
||||
"usbdrd30_axius_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
dwc3@15400000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x15400000 0x10000>;
|
||||
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -564,6 +564,46 @@ static struct clk_gate gxbb_clk81 = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_mux gxbb_sar_adc_clk_sel = {
|
||||
.reg = (void *)HHI_SAR_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 9,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sar_adc_clk_sel",
|
||||
.ops = &clk_mux_ops,
|
||||
/* NOTE: The datasheet doesn't list the parents for bit 10 */
|
||||
.parent_names = (const char *[]){ "xtal", "clk81", },
|
||||
.num_parents = 2,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_divider gxbb_sar_adc_clk_div = {
|
||||
.reg = (void *)HHI_SAR_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 8,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sar_adc_clk_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.parent_names = (const char *[]){ "sar_adc_clk_sel" },
|
||||
.num_parents = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate gxbb_sar_adc_clk = {
|
||||
.reg = (void *)HHI_SAR_CLK_CNTL,
|
||||
.bit_idx = 8,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "sar_adc_clk",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "sar_adc_clk_div" },
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
/* Everything Else (EE) domain gates */
|
||||
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
|
||||
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
|
||||
@ -754,6 +794,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
|
||||
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
|
||||
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
|
||||
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
|
||||
[CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
|
||||
[CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
|
||||
[CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
};
|
||||
@ -856,6 +899,7 @@ static struct clk_gate *gxbb_clk_gates[] = {
|
||||
&gxbb_emmc_a,
|
||||
&gxbb_emmc_b,
|
||||
&gxbb_emmc_c,
|
||||
&gxbb_sar_adc_clk,
|
||||
};
|
||||
|
||||
static int gxbb_clkc_probe(struct platform_device *pdev)
|
||||
@ -888,6 +932,10 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
|
||||
gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
|
||||
gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
|
||||
|
||||
/* Populate the base address for the SAR ADC clks */
|
||||
gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg;
|
||||
gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg;
|
||||
|
||||
/* Populate base address for gates */
|
||||
for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
|
||||
gxbb_clk_gates[i]->reg = clk_base +
|
||||
|
||||
@ -191,7 +191,7 @@
|
||||
#define CLKID_PERIPHS 20
|
||||
#define CLKID_SPICC 21
|
||||
/* CLKID_I2C */
|
||||
#define CLKID_SAR_ADC 23
|
||||
/* #define CLKID_SAR_ADC */
|
||||
#define CLKID_SMART_CARD 24
|
||||
#define CLKID_RNG0 25
|
||||
#define CLKID_UART0 26
|
||||
@ -204,7 +204,7 @@
|
||||
#define CLKID_ASSIST_MISC 33
|
||||
/* CLKID_SPI */
|
||||
#define CLKID_I2S_SPDIF 35
|
||||
#define CLKID_ETH 36
|
||||
/* CLKID_ETH */
|
||||
#define CLKID_DEMUX 37
|
||||
#define CLKID_AIU_GLUE 38
|
||||
#define CLKID_IEC958 39
|
||||
@ -231,13 +231,13 @@
|
||||
#define CLKID_AHB_DATA_BUS 60
|
||||
#define CLKID_AHB_CTRL_BUS 61
|
||||
#define CLKID_HDMI_INTR_SYNC 62
|
||||
#define CLKID_HDMI_PCLK 63
|
||||
/* CLKID_HDMI_PCLK */
|
||||
/* CLKID_USB1_DDR_BRIDGE */
|
||||
/* CLKID_USB0_DDR_BRIDGE */
|
||||
#define CLKID_MMC_PCLK 66
|
||||
#define CLKID_DVIN 67
|
||||
#define CLKID_UART2 68
|
||||
#define CLKID_SANA 69
|
||||
/* #define CLKID_SANA */
|
||||
#define CLKID_VPU_INTR 70
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
|
||||
#define CLKID_CLK81_A53 72
|
||||
@ -245,7 +245,7 @@
|
||||
#define CLKID_VCLK2_VENCI1 74
|
||||
#define CLKID_VCLK2_VENCP0 75
|
||||
#define CLKID_VCLK2_VENCP1 76
|
||||
#define CLKID_GCLK_VENCI_INT0 77
|
||||
/* CLKID_GCLK_VENCI_INT0 */
|
||||
#define CLKID_GCLK_VENCI_INT 78
|
||||
#define CLKID_DAC_CLK 79
|
||||
#define CLKID_AOCLK_GATE 80
|
||||
@ -265,8 +265,11 @@
|
||||
/* CLKID_SD_EMMC_A */
|
||||
/* CLKID_SD_EMMC_B */
|
||||
/* CLKID_SD_EMMC_C */
|
||||
/* CLKID_SAR_ADC_CLK */
|
||||
/* CLKID_SAR_ADC_SEL */
|
||||
#define CLKID_SAR_ADC_DIV 99
|
||||
|
||||
#define NR_CLKS 97
|
||||
#define NR_CLKS 100
|
||||
|
||||
/* include the CLKIDs that have been made part of the stable DT binding */
|
||||
#include <dt-bindings/clock/gxbb-clkc.h>
|
||||
|
||||
@ -739,7 +739,9 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst =
|
||||
PLL_35XX_RATE(350000000U, 350, 6, 2),
|
||||
PLL_35XX_RATE(333000000U, 222, 4, 2),
|
||||
PLL_35XX_RATE(300000000U, 500, 5, 3),
|
||||
PLL_35XX_RATE(278000000U, 556, 6, 3),
|
||||
PLL_35XX_RATE(266000000U, 532, 6, 3),
|
||||
PLL_35XX_RATE(250000000U, 500, 6, 3),
|
||||
PLL_35XX_RATE(200000000U, 400, 6, 3),
|
||||
PLL_35XX_RATE(166000000U, 332, 6, 3),
|
||||
PLL_35XX_RATE(160000000U, 320, 6, 3),
|
||||
@ -2559,8 +2561,10 @@ static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
|
||||
FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
|
||||
FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
|
||||
/* PHY clocks from MIPI_DPHY0 */
|
||||
FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000),
|
||||
FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000),
|
||||
FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
|
||||
NULL, 0, 188000000),
|
||||
FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
|
||||
NULL, 0, 100000000),
|
||||
/* PHY clocks from HDMI_PHY */
|
||||
FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
|
||||
NULL, 0, 300000000),
|
||||
|
||||
@ -771,7 +771,10 @@
|
||||
|
||||
#define CLK_PCLK_DECON 113
|
||||
|
||||
#define DISP_NR_CLK 114
|
||||
#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114
|
||||
#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115
|
||||
|
||||
#define DISP_NR_CLK 116
|
||||
|
||||
/* CMU_AUD */
|
||||
#define CLK_MOUT_AUD_PLL_USER 1
|
||||
|
||||
@ -14,15 +14,21 @@
|
||||
#define CLKID_MPLL2 15
|
||||
#define CLKID_SPI 34
|
||||
#define CLKID_I2C 22
|
||||
#define CLKID_SAR_ADC 23
|
||||
#define CLKID_ETH 36
|
||||
#define CLKID_USB0 50
|
||||
#define CLKID_USB1 51
|
||||
#define CLKID_USB 55
|
||||
#define CLKID_HDMI_PCLK 63
|
||||
#define CLKID_USB1_DDR_BRIDGE 64
|
||||
#define CLKID_USB0_DDR_BRIDGE 65
|
||||
#define CLKID_SANA 69
|
||||
#define CLKID_GCLK_VENCI_INT0 77
|
||||
#define CLKID_AO_I2C 93
|
||||
#define CLKID_SD_EMMC_A 94
|
||||
#define CLKID_SD_EMMC_B 95
|
||||
#define CLKID_SD_EMMC_C 96
|
||||
#define CLKID_SAR_ADC_CLK 97
|
||||
#define CLKID_SAR_ADC_SEL 98
|
||||
|
||||
#endif /* __GXBB_CLKC_H */
|
||||
|
||||
@ -68,4 +68,12 @@
|
||||
#define EXYNOS_PIN_FUNC_6 6
|
||||
#define EXYNOS_PIN_FUNC_F 0xf
|
||||
|
||||
/* Drive strengths for Exynos7 FSYS1 block */
|
||||
#define EXYNOS7_FSYS1_PIN_DRV_LV1 0
|
||||
#define EXYNOS7_FSYS1_PIN_DRV_LV2 4
|
||||
#define EXYNOS7_FSYS1_PIN_DRV_LV3 2
|
||||
#define EXYNOS7_FSYS1_PIN_DRV_LV4 6
|
||||
#define EXYNOS7_FSYS1_PIN_DRV_LV5 1
|
||||
#define EXYNOS7_FSYS1_PIN_DRV_LV6 5
|
||||
|
||||
#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user