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[PATCH] AT91RM9200 Ethernet driver
This patch adds support for the Ethernet controller integrated in the Atmel AT91RM9200 SoC processor. Changes since the previous submission (01/02/2006) are: - Make use of the clk.h clock infrastructure. - The multicast hash function is not crc32. [Patch by Pedro Perez] Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Andrew Victor
Jeff Garzik
parent
e93252faca
commit
d4b7780ea1
@ -31,3 +31,11 @@ config ARM_ETHERH
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help
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If you have an Acorn system with one of these network cards, you
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should say Y to this option if you wish to use it with Linux.
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config ARM_AT91_ETHER
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tristate "AT91RM9200 Ethernet support"
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depends on NET_ETHERNET && ARM && ARCH_AT91RM9200
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select MII
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help
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If you wish to compile a kernel for the AT91RM9200 and enable
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ethernet support, then you should always answer Y to this.
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@ -7,3 +7,4 @@ obj-$(CONFIG_ARM_AM79C961A) += am79c961a.o
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obj-$(CONFIG_ARM_ETHERH) += etherh.o
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obj-$(CONFIG_ARM_ETHER3) += ether3.o
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obj-$(CONFIG_ARM_ETHER1) += ether1.o
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obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o
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1110
drivers/net/arm/at91_ether.c
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1110
drivers/net/arm/at91_ether.c
Normal file
File diff suppressed because it is too large
Load Diff
101
drivers/net/arm/at91_ether.h
Normal file
101
drivers/net/arm/at91_ether.h
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@ -0,0 +1,101 @@
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/*
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* Ethernet driver for the Atmel AT91RM9200 (Thunder)
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*
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* Copyright (C) SAN People (Pty) Ltd
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*
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* Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
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* Initial version by Rick Bronson.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef AT91_ETHERNET
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#define AT91_ETHERNET
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/* Davicom 9161 PHY */
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#define MII_DM9161_ID 0x0181b880
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#define MII_DM9161A_ID 0x0181b8a0
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/* Davicom specific registers */
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#define MII_DSCR_REG 16
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#define MII_DSCSR_REG 17
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#define MII_DSINTR_REG 21
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/* Intel LXT971A PHY */
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#define MII_LXT971A_ID 0x001378E0
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/* Intel specific registers */
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#define MII_ISINTE_REG 18
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#define MII_ISINTS_REG 19
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#define MII_LEDCTRL_REG 20
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/* Realtek RTL8201 PHY */
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#define MII_RTL8201_ID 0x00008200
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/* Broadcom BCM5221 PHY */
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#define MII_BCM5221_ID 0x004061e0
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/* Broadcom specific registers */
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#define MII_BCMINTR_REG 26
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/* National Semiconductor DP83847 */
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#define MII_DP83847_ID 0x20005c30
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/* Altima AC101L PHY */
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#define MII_AC101L_ID 0x00225520
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/* Micrel KS8721 PHY */
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#define MII_KS8721_ID 0x00221610
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/* ........................................................................ */
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#define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */
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#define MAX_RX_DESCR 9 /* max number of receive buffers */
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#define EMAC_DESC_DONE 0x00000001 /* bit for if DMA is done */
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#define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */
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#define EMAC_BROADCAST 0x80000000 /* broadcast address */
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#define EMAC_MULTICAST 0x40000000 /* multicast address */
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#define EMAC_UNICAST 0x20000000 /* unicast address */
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struct rbf_t
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{
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unsigned int addr;
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unsigned long size;
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};
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struct recv_desc_bufs
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{
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struct rbf_t descriptors[MAX_RX_DESCR]; /* must be on sizeof (rbf_t) boundary */
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char recv_buf[MAX_RX_DESCR][MAX_RBUFF_SZ]; /* must be on long boundary */
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};
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struct at91_private
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{
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struct net_device_stats stats;
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struct mii_if_info mii; /* ethtool support */
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struct at91_eth_data board_data; /* board-specific configuration */
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/* PHY */
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unsigned long phy_type; /* type of PHY (PHY_ID) */
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spinlock_t lock; /* lock for MDI interface */
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short phy_media; /* media interface type */
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unsigned short phy_address; /* 5-bit MDI address of PHY (0..31) */
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/* Transmit */
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struct sk_buff *skb; /* holds skb until xmit interrupt completes */
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dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
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int skb_length; /* saved skb length for pci_unmap_single */
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/* Receive */
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int rxBuffIndex; /* index into receive descriptor list */
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struct recv_desc_bufs *dlist; /* descriptor list address */
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struct recv_desc_bufs *dlist_phys; /* descriptor list physical address */
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};
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#endif
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138
include/asm-arm/arch-at91rm9200/at91rm9200_emac.h
Normal file
138
include/asm-arm/arch-at91rm9200/at91rm9200_emac.h
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@ -0,0 +1,138 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91rm9200_emac.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Ethernet MAC registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91RM9200_EMAC_H
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#define AT91RM9200_EMAC_H
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#define AT91_EMAC_CTL 0x00 /* Control Register */
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#define AT91_EMAC_LB (1 << 0) /* Loopback */
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#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */
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#define AT91_EMAC_RE (1 << 2) /* Receive Enable */
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#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */
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#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */
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#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */
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#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */
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#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */
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#define AT91_EMAC_BP (1 << 8) /* Back Pressure */
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#define AT91_EMAC_CFG 0x04 /* Configuration Register */
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#define AT91_EMAC_SPD (1 << 0) /* Speed */
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#define AT91_EMAC_FD (1 << 1) /* Full Duplex */
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#define AT91_EMAC_BR (1 << 2) /* Bit Rate */
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#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */
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#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */
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#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */
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#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */
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#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */
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#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */
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#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */
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#define AT91_EMAC_CLK_DIV8 (0 << 10)
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#define AT91_EMAC_CLK_DIV16 (1 << 10)
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#define AT91_EMAC_CLK_DIV32 (2 << 10)
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#define AT91_EMAC_CLK_DIV64 (3 << 10)
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#define AT91_EMAC_RTY (1 << 12) /* Retry Test */
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#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */
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#define AT91_EMAC_SR 0x08 /* Status Register */
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#define AT91_EMAC_SR_LINK (1 << 0) /* Link */
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#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */
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#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */
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#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */
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#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */
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#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */
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#define AT91_EMAC_NCRC (1 << 15) /* No CRC */
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#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */
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#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */
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#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */
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#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */
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#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */
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#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */
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#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */
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#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */
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#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */
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#define AT91_EMAC_RSR 0x20 /* Receive Status Register */
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#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */
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#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */
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#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */
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#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */
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#define AT91_EMAC_DONE (1 << 0) /* Management Done */
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#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */
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#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */
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#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */
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#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */
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#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */
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#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */
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#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */
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#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */
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#define AT91_EMAC_LINK (1 << 9) /* Link */
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#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */
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#define AT91_EMAC_ABT (1 << 11) /* Abort */
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#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */
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#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */
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#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */
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#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */
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#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */
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#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */
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#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */
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#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */
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#define AT91_EMAC_RW_W (1 << 28)
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#define AT91_EMAC_RW_R (2 << 28)
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#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */
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/*
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* Statistics Registers.
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*/
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#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */
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#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */
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#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */
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#define AT91_EMAC_OK 0x4c /* Frames Received OK */
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#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */
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#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */
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#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */
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#define AT91_EMAC_LCOL 0x5c /* Late Collision */
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#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */
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#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */
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#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */
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#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */
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#define AT91_EMAC_ROV 0x70 /* Receive Overrun */
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#define AT91_EMAC_CDE 0x74 /* Code Error */
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#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */
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#define AT91_EMAC_RJB 0x7c /* Receive Jabber */
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#define AT91_EMAC_USF 0x80 /* Undersize Frame */
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#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */
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/*
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* Address Registers.
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*/
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#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */
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#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */
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#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */
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#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */
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#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */
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#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */
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#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */
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#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */
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#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */
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#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */
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#endif
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