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mtd: rawnand: mxc: implement exec_op
This converts the driver to the more modern exec_op which gets us rid of a bunch of legacy code. Tested on i.MX27 and i.MX25. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20240522-mtd-nand-mxc-nand-exec-op-v4-2-75b611e0ac44@pengutronix.de
This commit is contained in:
Sascha Hauer
Miquel Raynal
parent
94beaa25c7
commit
d3dfbae6d4
@ -126,8 +126,7 @@ struct mxc_nand_host;
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struct mxc_nand_devtype_data {
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void (*preset)(struct mtd_info *);
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int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc,
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int page);
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int (*read_page)(struct nand_chip *chip);
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void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
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void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
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void (*send_page)(struct mtd_info *, unsigned int);
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@ -182,8 +181,7 @@ struct mxc_nand_host {
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struct completion op_completion;
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uint8_t *data_buf;
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unsigned int buf_start;
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void *data_buf;
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const struct mxc_nand_devtype_data *devtype_data;
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};
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@ -285,63 +283,6 @@ static void copy_spare(struct mtd_info *mtd, bool bfrom, void *buf)
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}
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}
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/*
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* MXC NANDFC can only perform full page+spare or spare-only read/write. When
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* the upper layers perform a read/write buf operation, the saved column address
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* is used to index into the full page. So usually this function is called with
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* column == 0 (unless no column cycle is needed indicated by column == -1)
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*/
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static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
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{
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struct nand_chip *nand_chip = mtd_to_nand(mtd);
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struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
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/* Write out column address, if necessary */
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if (column != -1) {
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host->devtype_data->send_addr(host, column & 0xff,
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page_addr == -1);
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if (mtd->writesize > 512)
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/* another col addr cycle for 2k page */
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host->devtype_data->send_addr(host,
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(column >> 8) & 0xff,
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false);
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}
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/* Write out page address, if necessary */
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if (page_addr != -1) {
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/* paddr_0 - p_addr_7 */
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host->devtype_data->send_addr(host, (page_addr & 0xff), false);
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if (mtd->writesize > 512) {
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if (mtd->size >= 0x10000000) {
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/* paddr_8 - paddr_15 */
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host->devtype_data->send_addr(host,
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(page_addr >> 8) & 0xff,
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false);
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host->devtype_data->send_addr(host,
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(page_addr >> 16) & 0xff,
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true);
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} else
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/* paddr_8 - paddr_15 */
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host->devtype_data->send_addr(host,
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(page_addr >> 8) & 0xff, true);
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} else {
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if (nand_chip->options & NAND_ROW_ADDR_3) {
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/* paddr_8 - paddr_15 */
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host->devtype_data->send_addr(host,
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(page_addr >> 8) & 0xff,
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false);
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host->devtype_data->send_addr(host,
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(page_addr >> 16) & 0xff,
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true);
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} else
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/* paddr_8 - paddr_15 */
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host->devtype_data->send_addr(host,
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(page_addr >> 8) & 0xff, true);
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}
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}
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}
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static int check_int_v3(struct mxc_nand_host *host)
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{
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uint32_t tmp;
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@ -763,18 +704,7 @@ static void mxc_nand_enable_hwecc_v3(struct nand_chip *chip, bool enable)
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writel(config2, NFC_V3_CONFIG2);
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}
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/* This functions is used by upper layer to checks if device is ready */
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static int mxc_nand_dev_ready(struct nand_chip *chip)
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{
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/*
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* NFC handles R/B internally. Therefore, this function
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* always returns status as ready.
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*/
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return 1;
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}
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static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *oob,
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bool ecc, int page)
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static int mxc_nand_read_page_v1(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct mxc_nand_host *host = nand_get_controller_data(chip);
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@ -782,15 +712,11 @@ static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *oob,
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int i;
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unsigned int ecc_stats = 0;
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host->devtype_data->enable_hwecc(chip, ecc);
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host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
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mxc_do_addr_cycle(mtd, 0, page);
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if (mtd->writesize > 512)
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host->devtype_data->send_cmd(host, NAND_CMD_READSTART, true);
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if (mtd->writesize)
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no_subpages = mtd->writesize >> 9;
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else
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/* READ PARAMETER PAGE is called when mtd->writesize is not yet set */
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no_subpages = 1;
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for (i = 0; i < no_subpages; i++) {
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/* NANDFC buffer 0 is used for page read/write */
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@ -807,97 +733,68 @@ static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *oob,
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host->ecc_stats_v1 = ecc_stats;
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if (buf)
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memcpy32_fromio(buf, host->main_area0, mtd->writesize);
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if (oob)
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copy_spare(mtd, true, oob);
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return 0;
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}
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static int mxc_nand_read_page_v2_v3(struct nand_chip *chip, void *buf,
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void *oob, bool ecc, int page)
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static int mxc_nand_read_page_v2_v3(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct mxc_nand_host *host = nand_get_controller_data(chip);
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host->devtype_data->enable_hwecc(chip, ecc);
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host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
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mxc_do_addr_cycle(mtd, 0, page);
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if (mtd->writesize > 512)
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host->devtype_data->send_cmd(host,
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NAND_CMD_READSTART, true);
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host->devtype_data->send_page(mtd, NFC_OUTPUT);
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if (buf)
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memcpy32_fromio(buf, host->main_area0, mtd->writesize);
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if (oob)
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copy_spare(mtd, true, oob);
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return 0;
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}
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static int mxc_nand_read_page(struct nand_chip *chip, uint8_t *buf,
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int oob_required, int page)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct mxc_nand_host *host = nand_get_controller_data(chip);
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void *oob_buf;
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int ret;
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if (oob_required)
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oob_buf = chip->oob_poi;
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else
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oob_buf = NULL;
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host->devtype_data->enable_hwecc(chip, true);
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ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize);
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host->devtype_data->enable_hwecc(chip, false);
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ret = host->devtype_data->read_page(chip, buf, oob_buf, 1, page);
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if (ret)
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return ret;
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if (oob_required)
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copy_spare(mtd, true, chip->oob_poi);
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return host->devtype_data->get_ecc_status(chip);
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}
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static int mxc_nand_read_page_raw(struct nand_chip *chip, uint8_t *buf,
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int oob_required, int page)
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{
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struct mxc_nand_host *host = nand_get_controller_data(chip);
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void *oob_buf;
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struct mtd_info *mtd = nand_to_mtd(chip);
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int ret;
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ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize);
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if (ret)
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return ret;
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if (oob_required)
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oob_buf = chip->oob_poi;
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else
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oob_buf = NULL;
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copy_spare(mtd, true, chip->oob_poi);
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return host->devtype_data->read_page(chip, buf, oob_buf, 0, page);
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return 0;
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}
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static int mxc_nand_read_oob(struct nand_chip *chip, int page)
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{
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struct mxc_nand_host *host = nand_get_controller_data(chip);
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return host->devtype_data->read_page(chip, NULL, chip->oob_poi, 0,
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page);
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}
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static int mxc_nand_write_page(struct nand_chip *chip, const uint8_t *buf,
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bool ecc, int page)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct mxc_nand_host *host = nand_get_controller_data(chip);
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int ret;
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host->devtype_data->enable_hwecc(chip, ecc);
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ret = nand_read_page_op(chip, page, 0, host->data_buf, mtd->writesize);
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if (ret)
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return ret;
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host->devtype_data->send_cmd(host, NAND_CMD_SEQIN, false);
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mxc_do_addr_cycle(mtd, 0, page);
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memcpy32_toio(host->main_area0, buf, mtd->writesize);
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copy_spare(mtd, false, chip->oob_poi);
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host->devtype_data->send_page(mtd, NFC_INPUT);
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host->devtype_data->send_cmd(host, NAND_CMD_PAGEPROG, true);
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mxc_do_addr_cycle(mtd, 0, page);
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copy_spare(mtd, true, chip->oob_poi);
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return 0;
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}
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@ -905,13 +802,29 @@ static int mxc_nand_write_page(struct nand_chip *chip, const uint8_t *buf,
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static int mxc_nand_write_page_ecc(struct nand_chip *chip, const uint8_t *buf,
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int oob_required, int page)
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{
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return mxc_nand_write_page(chip, buf, true, page);
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct mxc_nand_host *host = nand_get_controller_data(chip);
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int ret;
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copy_spare(mtd, false, chip->oob_poi);
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host->devtype_data->enable_hwecc(chip, true);
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ret = nand_prog_page_op(chip, page, 0, buf, mtd->writesize);
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host->devtype_data->enable_hwecc(chip, false);
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return ret;
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}
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static int mxc_nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
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int oob_required, int page)
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{
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return mxc_nand_write_page(chip, buf, false, page);
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struct mtd_info *mtd = nand_to_mtd(chip);
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copy_spare(mtd, false, chip->oob_poi);
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return nand_prog_page_op(chip, page, 0, buf, mtd->writesize);
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}
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static int mxc_nand_write_oob(struct nand_chip *chip, int page)
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@ -920,68 +833,9 @@ static int mxc_nand_write_oob(struct nand_chip *chip, int page)
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struct mxc_nand_host *host = nand_get_controller_data(chip);
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memset(host->data_buf, 0xff, mtd->writesize);
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copy_spare(mtd, false, chip->oob_poi);
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return mxc_nand_write_page(chip, host->data_buf, false, page);
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}
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static u_char mxc_nand_read_byte(struct nand_chip *nand_chip)
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{
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struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
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uint8_t ret;
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/* Check for status request */
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if (host->status_request)
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return host->devtype_data->get_dev_status(host) & 0xFF;
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if (nand_chip->options & NAND_BUSWIDTH_16) {
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/* only take the lower byte of each word */
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ret = *(uint16_t *)(host->data_buf + host->buf_start);
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host->buf_start += 2;
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} else {
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ret = *(uint8_t *)(host->data_buf + host->buf_start);
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host->buf_start++;
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}
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dev_dbg(host->dev, "%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
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return ret;
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}
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/* Write data of length len to buffer buf. The data to be
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* written on NAND Flash is first copied to RAMbuffer. After the Data Input
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* Operation by the NFC, the data is written to NAND Flash */
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static void mxc_nand_write_buf(struct nand_chip *nand_chip, const u_char *buf,
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int len)
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{
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struct mtd_info *mtd = nand_to_mtd(nand_chip);
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struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
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u16 col = host->buf_start;
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int n = mtd->oobsize + mtd->writesize - col;
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n = min(n, len);
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memcpy(host->data_buf + col, buf, n);
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host->buf_start += n;
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}
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/* Read the data buffer from the NAND Flash. To read the data from NAND
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* Flash first the data output cycle is initiated by the NFC, which copies
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* the data to RAMbuffer. This data of length len is then copied to buffer buf.
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*/
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static void mxc_nand_read_buf(struct nand_chip *nand_chip, u_char *buf,
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int len)
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{
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struct mtd_info *mtd = nand_to_mtd(nand_chip);
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struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
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u16 col = host->buf_start;
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int n = mtd->oobsize + mtd->writesize - col;
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n = min(n, len);
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memcpy(buf, host->data_buf + col, n);
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host->buf_start += n;
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return nand_prog_page_op(chip, page, 0, host->data_buf, mtd->writesize);
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}
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/* This function is used by upper layer for select and
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@ -1360,107 +1214,6 @@ static void preset_v3(struct mtd_info *mtd)
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writel(0, NFC_V3_DELAY_LINE);
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}
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/* Used by the upper layer to write command to NAND Flash for
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* different operations to be carried out on NAND Flash */
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static void mxc_nand_command(struct nand_chip *nand_chip, unsigned command,
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int column, int page_addr)
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{
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struct mtd_info *mtd = nand_to_mtd(nand_chip);
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struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
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dev_dbg(host->dev, "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
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command, column, page_addr);
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/* Reset command state information */
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host->status_request = false;
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/* Command pre-processing step */
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switch (command) {
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case NAND_CMD_RESET:
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host->devtype_data->preset(mtd);
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host->devtype_data->send_cmd(host, command, false);
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break;
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case NAND_CMD_STATUS:
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host->buf_start = 0;
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host->status_request = true;
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host->devtype_data->send_cmd(host, command, true);
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WARN_ONCE(column != -1 || page_addr != -1,
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"Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
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command, column, page_addr);
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mxc_do_addr_cycle(mtd, column, page_addr);
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break;
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case NAND_CMD_READID:
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host->devtype_data->send_cmd(host, command, true);
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mxc_do_addr_cycle(mtd, column, page_addr);
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host->devtype_data->send_read_id(host);
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host->buf_start = 0;
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break;
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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host->devtype_data->send_cmd(host, command, false);
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WARN_ONCE(column != -1,
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"Unexpected column value (cmd=%u, col=%d)\n",
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command, column);
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mxc_do_addr_cycle(mtd, column, page_addr);
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break;
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case NAND_CMD_PARAM:
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host->devtype_data->send_cmd(host, command, false);
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mxc_do_addr_cycle(mtd, column, page_addr);
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host->devtype_data->send_page(mtd, NFC_OUTPUT);
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memcpy32_fromio(host->data_buf, host->main_area0, 512);
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host->buf_start = 0;
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break;
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default:
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WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
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command);
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break;
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}
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}
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static int mxc_nand_set_features(struct nand_chip *chip, int addr,
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u8 *subfeature_param)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct mxc_nand_host *host = nand_get_controller_data(chip);
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int i;
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host->buf_start = 0;
|
||||
|
||||
for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
|
||||
chip->legacy.write_byte(chip, subfeature_param[i]);
|
||||
|
||||
memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
|
||||
host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false);
|
||||
mxc_do_addr_cycle(mtd, addr, -1);
|
||||
host->devtype_data->send_page(mtd, NFC_INPUT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxc_nand_get_features(struct nand_chip *chip, int addr,
|
||||
u8 *subfeature_param)
|
||||
{
|
||||
struct mtd_info *mtd = nand_to_mtd(chip);
|
||||
struct mxc_nand_host *host = nand_get_controller_data(chip);
|
||||
int i;
|
||||
|
||||
host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false);
|
||||
mxc_do_addr_cycle(mtd, addr, -1);
|
||||
host->devtype_data->send_page(mtd, NFC_OUTPUT);
|
||||
memcpy32_fromio(host->data_buf, host->main_area0, 512);
|
||||
host->buf_start = 0;
|
||||
|
||||
for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
|
||||
*subfeature_param++ = chip->legacy.read_byte(chip);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* The generic flash bbt descriptors overlap with our ecc
|
||||
* hardware, so define some i.MX specific ones.
|
||||
@ -1717,9 +1470,127 @@ static int mxcnd_setup_interface(struct nand_chip *chip, int chipnr,
|
||||
return host->devtype_data->setup_interface(chip, chipnr, conf);
|
||||
}
|
||||
|
||||
static int mxcnd_do_exec_op(struct nand_chip *chip,
|
||||
const struct nand_subop *op)
|
||||
{
|
||||
struct mxc_nand_host *host = nand_get_controller_data(chip);
|
||||
struct mtd_info *mtd = nand_to_mtd(chip);
|
||||
int i, j, buf_len;
|
||||
void *buf_read = NULL;
|
||||
const void *buf_write = NULL;
|
||||
const struct nand_op_instr *instr;
|
||||
bool readid = false;
|
||||
bool statusreq = false;
|
||||
|
||||
for (i = 0; i < op->ninstrs; i++) {
|
||||
instr = &op->instrs[i];
|
||||
|
||||
switch (instr->type) {
|
||||
case NAND_OP_WAITRDY_INSTR:
|
||||
/* NFC handles R/B internally, nothing to do here */
|
||||
break;
|
||||
case NAND_OP_CMD_INSTR:
|
||||
host->devtype_data->send_cmd(host, instr->ctx.cmd.opcode, true);
|
||||
|
||||
if (instr->ctx.cmd.opcode == NAND_CMD_READID)
|
||||
readid = true;
|
||||
if (instr->ctx.cmd.opcode == NAND_CMD_STATUS)
|
||||
statusreq = true;
|
||||
|
||||
break;
|
||||
case NAND_OP_ADDR_INSTR:
|
||||
for (j = 0; j < instr->ctx.addr.naddrs; j++) {
|
||||
bool islast = j == instr->ctx.addr.naddrs - 1;
|
||||
host->devtype_data->send_addr(host, instr->ctx.addr.addrs[j], islast);
|
||||
}
|
||||
break;
|
||||
case NAND_OP_DATA_OUT_INSTR:
|
||||
buf_write = instr->ctx.data.buf.out;
|
||||
buf_len = instr->ctx.data.len;
|
||||
|
||||
memcpy32_toio(host->main_area0, buf_write, buf_len);
|
||||
|
||||
host->devtype_data->send_page(mtd, NFC_INPUT);
|
||||
|
||||
break;
|
||||
case NAND_OP_DATA_IN_INSTR:
|
||||
|
||||
buf_read = instr->ctx.data.buf.in;
|
||||
buf_len = instr->ctx.data.len;
|
||||
|
||||
if (readid) {
|
||||
host->devtype_data->send_read_id(host);
|
||||
readid = false;
|
||||
|
||||
memcpy32_fromio(host->data_buf, host->main_area0, buf_len * 2);
|
||||
|
||||
if (chip->options & NAND_BUSWIDTH_16) {
|
||||
u8 *bufr = buf_read;
|
||||
u16 *bufw = host->data_buf;
|
||||
for (j = 0; j < buf_len; j++)
|
||||
bufr[j] = bufw[j];
|
||||
} else {
|
||||
memcpy(buf_read, host->data_buf, buf_len);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (statusreq) {
|
||||
*(u8*)buf_read = host->devtype_data->get_dev_status(host);
|
||||
statusreq = false;
|
||||
break;
|
||||
}
|
||||
|
||||
host->devtype_data->read_page(chip);
|
||||
|
||||
if (IS_ALIGNED(buf_len, 4)) {
|
||||
memcpy32_fromio(buf_read, host->main_area0, buf_len);
|
||||
} else {
|
||||
memcpy32_fromio(host->data_buf, host->main_area0, mtd->writesize);
|
||||
memcpy(buf_read, host->data_buf, buf_len);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define MAX_DATA_SIZE (4096 + 512)
|
||||
|
||||
static const struct nand_op_parser mxcnd_op_parser = NAND_OP_PARSER(
|
||||
NAND_OP_PARSER_PATTERN(mxcnd_do_exec_op,
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_ADDR_ELEM(true, 7),
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(true),
|
||||
NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
|
||||
NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, MAX_DATA_SIZE)),
|
||||
NAND_OP_PARSER_PATTERN(mxcnd_do_exec_op,
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_ADDR_ELEM(false, 7),
|
||||
NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_DATA_SIZE),
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
|
||||
NAND_OP_PARSER_PATTERN(mxcnd_do_exec_op,
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(false),
|
||||
NAND_OP_PARSER_PAT_ADDR_ELEM(false, 7),
|
||||
NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, MAX_DATA_SIZE),
|
||||
NAND_OP_PARSER_PAT_CMD_ELEM(true),
|
||||
NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
|
||||
);
|
||||
|
||||
static int mxcnd_exec_op(struct nand_chip *chip,
|
||||
const struct nand_operation *op, bool check_only)
|
||||
{
|
||||
return nand_op_parser_exec_op(chip, &mxcnd_op_parser,
|
||||
op, check_only);
|
||||
}
|
||||
|
||||
static const struct nand_controller_ops mxcnd_controller_ops = {
|
||||
.attach_chip = mxcnd_attach_chip,
|
||||
.setup_interface = mxcnd_setup_interface,
|
||||
.exec_op = mxcnd_exec_op,
|
||||
};
|
||||
|
||||
static int mxcnd_probe(struct platform_device *pdev)
|
||||
@ -1752,13 +1623,6 @@ static int mxcnd_probe(struct platform_device *pdev)
|
||||
|
||||
nand_set_controller_data(this, host);
|
||||
nand_set_flash_node(this, pdev->dev.of_node);
|
||||
this->legacy.dev_ready = mxc_nand_dev_ready;
|
||||
this->legacy.cmdfunc = mxc_nand_command;
|
||||
this->legacy.read_byte = mxc_nand_read_byte;
|
||||
this->legacy.write_buf = mxc_nand_write_buf;
|
||||
this->legacy.read_buf = mxc_nand_read_buf;
|
||||
this->legacy.set_features = mxc_nand_set_features;
|
||||
this->legacy.get_features = mxc_nand_get_features;
|
||||
|
||||
host->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(host->clk))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user