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perf vendor events arm64: Add ThunderX2 implementation defined pmu core events

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This is not a full event list, but a short list of useful events.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ganapatrao Kulkarni <gklkml16@gmail.com>
Cc: Jayachandran C <jnair@caviumnetworks.com>
Cc: Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Robert Richter <robert.richter@cavium.com>
Cc: Shaokun Zhang <zhangshaokun@hisilicon.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/20171016183222.25750-5-ganapatrao.kulkarni@cavium.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ganapatrao Kulkarni 2017-10-17 00:02:21 +05:30 committed by Arnaldo Carvalho de Melo
parent 14b22ae028
commit d3964221ea
2 changed files with 77 additions and 0 deletions
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62
tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json Normal file
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[
{
"PublicDescription": "Attributable Level 1 data cache access, read",
"EventCode": "0x40",
"EventName": "l1d_cache_rd",
"BriefDescription": "L1D cache read",
},
{
"PublicDescription": "Attributable Level 1 data cache access, write ",
"EventCode": "0x41",
"EventName": "l1d_cache_wr",
"BriefDescription": "L1D cache write",
},
{
"PublicDescription": "Attributable Level 1 data cache refill, read",
"EventCode": "0x42",
"EventName": "l1d_cache_refill_rd",
"BriefDescription": "L1D cache refill read",
},
{
"PublicDescription": "Attributable Level 1 data cache refill, write",
"EventCode": "0x43",
"EventName": "l1d_cache_refill_wr",
"BriefDescription": "L1D refill write",
},
{
"PublicDescription": "Attributable Level 1 data TLB refill, read",
"EventCode": "0x4C",
"EventName": "l1d_tlb_refill_rd",
"BriefDescription": "L1D tlb refill read",
},
{
"PublicDescription": "Attributable Level 1 data TLB refill, write",
"EventCode": "0x4D",
"EventName": "l1d_tlb_refill_wr",
"BriefDescription": "L1D tlb refill write",
},
{
"PublicDescription": "Attributable Level 1 data or unified TLB access, read",
"EventCode": "0x4E",
"EventName": "l1d_tlb_rd",
"BriefDescription": "L1D tlb read",
},
{
"PublicDescription": "Attributable Level 1 data or unified TLB access, write",
"EventCode": "0x4F",
"EventName": "l1d_tlb_wr",
"BriefDescription": "L1D tlb write",
},
{
"PublicDescription": "Bus access read",
"EventCode": "0x60",
"EventName": "bus_access_rd",
"BriefDescription": "Bus access read",
},
{
"PublicDescription": "Bus access write",
"EventCode": "0x61",
"EventName": "bus_access_wr",
"BriefDescription": "Bus access write",
}
]

15
tools/perf/pmu-events/arch/arm64/mapfile.csv Normal file
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# Format:
# MIDR,Version,JSON/file/pathname,Type
#
# where
# MIDR Processor version
# Variant[23:20] and Revision [3:0] should be zero.
# Version could be used to track version of of JSON file
# but currently unused.
# JSON/file/pathname is the path to JSON file, relative
# to tools/perf/pmu-events/arch/arm64/.
# Type is core, uncore etc
#
#
#Family-model,Version,Filename,EventType
0x00000000420f5160,v1,cavium,core
1 # Format:
2 # MIDR,Version,JSON/file/pathname,Type
3 #
4 # where
5 # MIDR Processor version
6 # Variant[23:20] and Revision [3:0] should be zero.
7 # Version could be used to track version of of JSON file
8 # but currently unused.
9 # JSON/file/pathname is the path to JSON file, relative
10 # to tools/perf/pmu-events/arch/arm64/.
11 # Type is core, uncore etc
12 #
13 #
14 #Family-model,Version,Filename,EventType
15 0x00000000420f5160,v1,cavium,core