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xen-pciback: return proper values during BAR sizing

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Reads following writes with all address bits set to 1 should return all
changeable address bits as one, not the BAR size (nor, as was the case
for the upper half of 64-bit BARs, the high half of the region's end
address). Presumably this didn't cause any problems so far because
consumers use the value to calculate the size (usually via val & -val),
and do nothing else with it.

But also consider the exception here: Unimplemented BARs should always
return all zeroes.

And finally, the check for whether to return the sizing address on read
for the ROM BAR should ignore all non-address bits, not just the ROM
Enable one.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Signed-off-by: David Vrabel <david.vrabel@citrix.com>
This commit is contained in:
Jan Beulich 2016-06-24 03:13:34 -06:00 committed by David Vrabel
parent d6b186c1e2
commit d2bd05d88d
1 changed files with 11 additions and 7 deletions
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18
drivers/xen/xen-pciback/conf_space_header.c
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@ -145,7 +145,7 @@ static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data)
/* A write to obtain the length must happen as a 32-bit write. /* A write to obtain the length must happen as a 32-bit write.
* This does not (yet) support writing individual bytes * This does not (yet) support writing individual bytes
*/ */
if (value == ~PCI_ROM_ADDRESS_ENABLE) if ((value | ~PCI_ROM_ADDRESS_MASK) == ~0U)
bar->which = 1; bar->which = 1;
else { else {
u32 tmpval; u32 tmpval;
@ -225,38 +225,42 @@ static inline void read_dev_bar(struct pci_dev *dev,
(PCI_BASE_ADDRESS_SPACE_MEMORY | (PCI_BASE_ADDRESS_SPACE_MEMORY |
PCI_BASE_ADDRESS_MEM_TYPE_64))) { PCI_BASE_ADDRESS_MEM_TYPE_64))) {
bar_info->val = res[pos - 1].start >> 32; bar_info->val = res[pos - 1].start >> 32;
bar_info->len_val = res[pos - 1].end >> 32; bar_info->len_val = -resource_size(&res[pos - 1]) >> 32;
return; return;
} }
} }
if (!res[pos].flags ||
(res[pos].flags & (IORESOURCE_DISABLED | IORESOURCE_UNSET |
IORESOURCE_BUSY)))
return;
bar_info->val = res[pos].start | bar_info->val = res[pos].start |
(res[pos].flags & PCI_REGION_FLAG_MASK); (res[pos].flags & PCI_REGION_FLAG_MASK);
bar_info->len_val = resource_size(&res[pos]); bar_info->len_val = -resource_size(&res[pos]) |
(res[pos].flags & PCI_REGION_FLAG_MASK);
} }
static void *bar_init(struct pci_dev *dev, int offset) static void *bar_init(struct pci_dev *dev, int offset)
{ {
struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL); struct pci_bar_info *bar = kzalloc(sizeof(*bar), GFP_KERNEL);
if (!bar) if (!bar)
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);
read_dev_bar(dev, bar, offset, ~0); read_dev_bar(dev, bar, offset, ~0);
bar->which = 0;
return bar; return bar;
} }
static void *rom_init(struct pci_dev *dev, int offset) static void *rom_init(struct pci_dev *dev, int offset)
{ {
struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL); struct pci_bar_info *bar = kzalloc(sizeof(*bar), GFP_KERNEL);
if (!bar) if (!bar)
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);
read_dev_bar(dev, bar, offset, ~PCI_ROM_ADDRESS_ENABLE); read_dev_bar(dev, bar, offset, ~PCI_ROM_ADDRESS_ENABLE);
bar->which = 0;
return bar; return bar;
} }