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MIPS: Octeon: Add PCIe2 support in arch_setup_msi_irq()

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In arch_setup_msi_irq(), there is no case for PCIe2. So board which have PCIe2 functionality
fails to boot with "Kernel panic - not syncing: arch_setup_msi_irq: Invalid octeon_dma_bar_type"
message. This patch solve this problem.

Signed-off-by: Eunbong Song <eunb.song@samsung.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/6747/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Eunbong Song 2014-04-11 08:32:54 +00:00 committed by Ralf Baechle
parent b8bca000f6
commit d19648d7f3
1 changed files with 6 additions and 0 deletions
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6
arch/mips/pci/msi-octeon.c
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@ -15,6 +15,7 @@
#include <asm/octeon/cvmx-npi-defs.h> #include <asm/octeon/cvmx-npi-defs.h>
#include <asm/octeon/cvmx-pci-defs.h> #include <asm/octeon/cvmx-pci-defs.h>
#include <asm/octeon/cvmx-npei-defs.h> #include <asm/octeon/cvmx-npei-defs.h>
#include <asm/octeon/cvmx-sli-defs.h>
#include <asm/octeon/cvmx-pexp-defs.h> #include <asm/octeon/cvmx-pexp-defs.h>
#include <asm/octeon/pci-octeon.h> #include <asm/octeon/pci-octeon.h>
@ -162,6 +163,11 @@ msi_irq_allocated:
msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff; msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32; msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
break; break;
case OCTEON_DMA_BAR_TYPE_PCIE2:
/* When using PCIe2, Bar 0 is based at 0 */
msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff;
msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32;
break;
default: default:
panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type"); panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
} }