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ARM: tegra: make tegra_resume can work with current and later chips
Because the CPU0 was the first up and the last down core when cluster power up/down or platform suspend. So only CPU0 needs the rest of the functions to reset flow controller and re-enable SCU and L2. We also move the L2 init function for Cortex-A15 to there. The secondery CPU can just call cpu_resume. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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@ -45,17 +45,11 @@
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ENTRY(tegra_resume)
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ENTRY(tegra_resume)
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check_cpu_part_num 0xc09, r8, r9
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check_cpu_part_num 0xc09, r8, r9
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bleq v7_invalidate_l1
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bleq v7_invalidate_l1
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blne tegra_init_l2_for_a15
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cpu_id r0
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cpu_id r0
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tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
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cmp r6, #TEGRA114
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beq no_cpu0_chk
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cmp r0, #0 @ CPU0?
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cmp r0, #0 @ CPU0?
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THUMB( it ne )
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THUMB( it ne )
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bne cpu_resume @ no
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bne cpu_resume @ no
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no_cpu0_chk:
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/* Are we on Tegra20? */
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/* Are we on Tegra20? */
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cmp r6, #TEGRA20
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cmp r6, #TEGRA20
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@ -75,7 +69,7 @@ no_cpu0_chk:
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mov32 r9, 0xc09
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mov32 r9, 0xc09
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cmp r8, r9
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cmp r8, r9
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bne not_ca9
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bne end_ca9_scu_l2_resume
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#ifdef CONFIG_HAVE_ARM_SCU
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#ifdef CONFIG_HAVE_ARM_SCU
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/* enable SCU */
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/* enable SCU */
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mov32 r0, TEGRA_ARM_PERIF_BASE
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mov32 r0, TEGRA_ARM_PERIF_BASE
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@ -86,7 +80,10 @@ no_cpu0_chk:
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/* L2 cache resume & re-enable */
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/* L2 cache resume & re-enable */
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l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
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l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
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not_ca9:
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end_ca9_scu_l2_resume:
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mov32 r9, 0xc0f
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cmp r8, r9
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bleq tegra_init_l2_for_a15
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b cpu_resume
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b cpu_resume
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ENDPROC(tegra_resume)
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ENDPROC(tegra_resume)
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