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drm/amd/powerplay: avoid DPM reenable process on Navi1x ASICs V2
Otherwise, without RLC reinitialization, the DPM reenablement will fail. That affects the custom pptable uploading. V2: setting/clearing uploading_custom_pp_table in smu_sys_set_pp_table() Reported-by: Matt Coffin <mcoffin13@gmail.com> Signed-off-by: Evan Quan <evan.quan@amd.com> Tested-by: Matt Coffin <mcoffin13@gmail.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -591,10 +591,18 @@ int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size)
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smu_table->power_play_table = smu_table->hardcode_pptable;
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smu_table->power_play_table_size = size;
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/*
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* Special hw_fini action(for Navi1x, the DPMs disablement will be
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* skipped) may be needed for custom pptable uploading.
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*/
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smu->uploading_custom_pp_table = true;
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ret = smu_reset(smu);
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if (ret)
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pr_info("smu reset failed, ret = %d\n", ret);
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smu->uploading_custom_pp_table = false;
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failed:
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mutex_unlock(&smu->mutex);
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return ret;
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@ -1295,10 +1303,25 @@ static int smu_hw_fini(void *handle)
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return ret;
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}
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ret = smu_stop_dpms(smu);
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if (ret) {
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pr_warn("Fail to stop Dpms!\n");
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return ret;
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/*
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* For custom pptable uploading, skip the DPM features
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* disable process on Navi1x ASICs.
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* - As the gfx related features are under control of
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* RLC on those ASICs. RLC reinitialization will be
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* needed to reenable them. That will cost much more
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* efforts.
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*
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* - SMU firmware can handle the DPM reenablement
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* properly.
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*/
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if (!smu->uploading_custom_pp_table ||
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!((adev->asic_type >= CHIP_NAVI10) &&
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(adev->asic_type <= CHIP_NAVI12))) {
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ret = smu_stop_dpms(smu);
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if (ret) {
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pr_warn("Fail to stop Dpms!\n");
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return ret;
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}
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}
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kfree(table_context->driver_pptable);
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@ -390,6 +390,7 @@ struct smu_context
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uint32_t smc_if_version;
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bool uploading_custom_pp_table;
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};
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struct i2c_adapter;
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