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[ARM] nommu: Initial uCLinux support for MMU-based CPUs
In noMMU mode, various of functions which are defined in mm/proc-*.S is not valid or needed to be avoided. i.g. switch_mm is not needed, just returns and this makes the I & D caches are valid which shows great improvement of performance including task switching and IPC. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Hyok S. Choi
Russell King
parent
a4f7e76367
commit
d090dddaba
@ -3,6 +3,7 @@
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*
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* Copyright (C) 2000 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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* hacked for non-paged-MM by Hyok S. Choi, 2003.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -101,7 +102,9 @@ ENTRY(cpu_arm1020_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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@ -359,6 +362,7 @@ ENTRY(cpu_arm1020_dcache_clean_area)
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*/
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.align 5
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ENTRY(cpu_arm1020_switch_mm)
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#ifdef CONFIG_MMU
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, r3, c7, c10, 4
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mov r1, #0xF @ 16 segments
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@ -383,6 +387,7 @@ ENTRY(cpu_arm1020_switch_mm)
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
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#endif /* CONFIG_MMU */
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mov pc, lr
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/*
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@ -392,6 +397,7 @@ ENTRY(cpu_arm1020_switch_mm)
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*/
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.align 5
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ENTRY(cpu_arm1020_set_pte)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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@ -421,6 +427,7 @@ ENTRY(cpu_arm1020_set_pte)
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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#endif /* CONFIG_MMU */
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mov pc, lr
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__INIT
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@ -430,7 +437,9 @@ __arm1020_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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#endif
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mrc p15, 0, r0, c1, c0 @ get control register v4
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ldr r5, arm1020_cr1_clear
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bic r0, r0, r5
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2000 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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* hacked for non-paged-MM by Hyok S. Choi, 2003.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -101,7 +102,9 @@ ENTRY(cpu_arm1020e_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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@ -344,6 +347,7 @@ ENTRY(cpu_arm1020e_dcache_clean_area)
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*/
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.align 5
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ENTRY(cpu_arm1020e_switch_mm)
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#ifdef CONFIG_MMU
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, r3, c7, c10, 4
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mov r1, #0xF @ 16 segments
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@ -367,6 +371,7 @@ ENTRY(cpu_arm1020e_switch_mm)
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mov pc, lr
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/*
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@ -376,6 +381,7 @@ ENTRY(cpu_arm1020e_switch_mm)
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*/
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.align 5
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ENTRY(cpu_arm1020e_set_pte)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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@ -403,6 +409,7 @@ ENTRY(cpu_arm1020e_set_pte)
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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#endif
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#endif /* CONFIG_MMU */
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mov pc, lr
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__INIT
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@ -412,7 +419,9 @@ __arm1020e_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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#endif
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mrc p15, 0, r0, c1, c0 @ get control register v4
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ldr r5, arm1020e_cr1_clear
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bic r0, r0, r5
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2000 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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* hacked for non-paged-MM by Hyok S. Choi, 2003.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -90,7 +91,9 @@ ENTRY(cpu_arm1022_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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@ -333,6 +336,7 @@ ENTRY(cpu_arm1022_dcache_clean_area)
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*/
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.align 5
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ENTRY(cpu_arm1022_switch_mm)
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#ifdef CONFIG_MMU
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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@ -349,6 +353,7 @@ ENTRY(cpu_arm1022_switch_mm)
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mov pc, lr
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/*
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@ -358,6 +363,7 @@ ENTRY(cpu_arm1022_switch_mm)
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*/
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.align 5
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ENTRY(cpu_arm1022_set_pte)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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@ -385,6 +391,7 @@ ENTRY(cpu_arm1022_set_pte)
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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#endif
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#endif /* CONFIG_MMU */
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mov pc, lr
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__INIT
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@ -394,7 +401,9 @@ __arm1022_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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#endif
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mrc p15, 0, r0, c1, c0 @ get control register v4
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ldr r5, arm1022_cr1_clear
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bic r0, r0, r5
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2000 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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* hacked for non-paged-MM by Hyok S. Choi, 2003.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -90,7 +91,9 @@ ENTRY(cpu_arm1026_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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@ -327,6 +330,7 @@ ENTRY(cpu_arm1026_dcache_clean_area)
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*/
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.align 5
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ENTRY(cpu_arm1026_switch_mm)
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#ifdef CONFIG_MMU
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mov r1, #0
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
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@ -338,6 +342,7 @@ ENTRY(cpu_arm1026_switch_mm)
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mov pc, lr
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/*
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@ -347,6 +352,7 @@ ENTRY(cpu_arm1026_switch_mm)
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*/
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.align 5
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ENTRY(cpu_arm1026_set_pte)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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@ -374,6 +380,7 @@ ENTRY(cpu_arm1026_set_pte)
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#ifndef CONFIG_CPU_DCACHE_DISABLE
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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#endif
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#endif /* CONFIG_MMU */
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mov pc, lr
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@ -384,8 +391,10 @@ __arm1026_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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mcr p15, 0, r4, c2, c0 @ load page table pointer
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#endif
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mov r0, #4 @ explicitly disable writeback
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mcr p15, 7, r0, c15, c0, 0
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@ -2,6 +2,7 @@
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* linux/arch/arm/mm/proc-arm6,7.S
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*
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* Copyright (C) 1997-2000 Russell King
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* hacked for non-paged-MM by Hyok S. Choi, 2003.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -199,10 +200,12 @@ ENTRY(cpu_arm7_do_idle)
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*/
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ENTRY(cpu_arm6_switch_mm)
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ENTRY(cpu_arm7_switch_mm)
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#ifdef CONFIG_MMU
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mov r1, #0
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mcr p15, 0, r1, c7, c0, 0 @ flush cache
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mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
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mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
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#endif
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mov pc, lr
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/*
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@ -214,6 +217,7 @@ ENTRY(cpu_arm7_switch_mm)
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.align 5
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ENTRY(cpu_arm6_set_pte)
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ENTRY(cpu_arm7_set_pte)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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@ -232,6 +236,7 @@ ENTRY(cpu_arm7_set_pte)
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movne r2, #0
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str r2, [r0] @ hardware version
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#endif /* CONFIG_MMU */
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mov pc, lr
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/*
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@ -243,7 +248,9 @@ ENTRY(cpu_arm6_reset)
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ENTRY(cpu_arm7_reset)
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mov r1, #0
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mcr p15, 0, r1, c7, c0, 0 @ flush cache
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#ifdef CONFIG_MMU
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mcr p15, 0, r1, c5, c0, 0 @ flush TLB
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#endif
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mov r1, #0x30
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mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
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mov pc, r0
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@ -253,19 +260,27 @@ ENTRY(cpu_arm7_reset)
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.type __arm6_setup, #function
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__arm6_setup: mov r0, #0
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mcr p15, 0, r0, c7, c0 @ flush caches on v3
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
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mov r0, #0x3d @ . ..RS BLDP WCAM
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orr r0, r0, #0x100 @ . ..01 0011 1101
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#else
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mov r0, #0x3c @ . ..RS BLDP WCA.
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#endif
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mov pc, lr
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.size __arm6_setup, . - __arm6_setup
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.type __arm7_setup, #function
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__arm7_setup: mov r0, #0
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mcr p15, 0, r0, c7, c0 @ flush caches on v3
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
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mcr p15, 0, r0, c3, c0 @ load domain access register
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mov r0, #0x7d @ . ..RS BLDP WCAM
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orr r0, r0, #0x100 @ . ..01 0111 1101
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#else
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mov r0, #0x7c @ . ..RS BLDP WCA.
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#endif
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mov pc, lr
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.size __arm7_setup, . - __arm7_setup
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@ -4,6 +4,7 @@
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* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
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* Rob Scott (rscott@mtrob.fdns.net)
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* Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
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* hacked for non-paged-MM by Hyok S. Choi, 2004.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -29,6 +30,7 @@
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* out of 'proc-arm6,7.S' per RMK discussion
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* 07-25-2000 SJH Added idle function.
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* 08-25-2000 DBS Updated for integration of ARM Ltd version.
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* 04-20-2004 HSC modified for non-paged memory management mode.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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@ -75,10 +77,12 @@ ENTRY(cpu_arm720_do_idle)
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* the new.
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*/
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ENTRY(cpu_arm720_switch_mm)
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#ifdef CONFIG_MMU
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mov r1, #0
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mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
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mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
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mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
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#endif
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mov pc, lr
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/*
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@ -89,6 +93,7 @@ ENTRY(cpu_arm720_switch_mm)
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*/
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.align 5
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ENTRY(cpu_arm720_set_pte)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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@ -107,6 +112,7 @@ ENTRY(cpu_arm720_set_pte)
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movne r2, #0
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str r2, [r0] @ hardware version
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#endif
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mov pc, lr
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/*
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@ -117,7 +123,9 @@ ENTRY(cpu_arm720_set_pte)
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ENTRY(cpu_arm720_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x2100 @ ..v....s........
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@ -130,7 +138,9 @@ ENTRY(cpu_arm720_reset)
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__arm710_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
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#endif
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mrc p15, 0, r0, c1, c0 @ get control register
|
||||
ldr r5, arm710_cr1_clear
|
||||
bic r0, r0, r5
|
||||
@ -156,7 +166,9 @@ arm710_cr1_set:
|
||||
__arm720_setup:
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
|
||||
#endif
|
||||
mrc p15, 0, r0, c1, c0 @ get control register
|
||||
ldr r5, arm720_cr1_clear
|
||||
bic r0, r0, r5
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
*
|
||||
* Copyright (C) 1999,2000 ARM Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd.
|
||||
* hacked for non-paged-MM by Hyok S. Choi, 2003.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@ -97,7 +98,9 @@ ENTRY(cpu_arm920_reset)
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
#endif
|
||||
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
|
||||
bic ip, ip, #0x000f @ ............wcam
|
||||
bic ip, ip, #0x1100 @ ...i...s........
|
||||
@ -317,6 +320,7 @@ ENTRY(cpu_arm920_dcache_clean_area)
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_arm920_switch_mm)
|
||||
#ifdef CONFIG_MMU
|
||||
mov ip, #0
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
|
||||
@ -337,6 +341,7 @@ ENTRY(cpu_arm920_switch_mm)
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
@ -346,6 +351,7 @@ ENTRY(cpu_arm920_switch_mm)
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_arm920_set_pte)
|
||||
#ifdef CONFIG_MMU
|
||||
str r1, [r0], #-2048 @ linux version
|
||||
|
||||
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
|
||||
@ -372,6 +378,7 @@ ENTRY(cpu_arm920_set_pte)
|
||||
mov r0, r0
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||||
#endif /* CONFIG_MMU */
|
||||
mov pc, lr
|
||||
|
||||
__INIT
|
||||
@ -381,7 +388,9 @@ __arm920_setup:
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
|
||||
#endif
|
||||
mrc p15, 0, r0, c1, c0 @ get control register v4
|
||||
ldr r5, arm920_cr1_clear
|
||||
bic r0, r0, r5
|
||||
|
||||
@ -4,6 +4,7 @@
|
||||
* Copyright (C) 1999,2000 ARM Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd.
|
||||
* Copyright (C) 2001 Altera Corporation
|
||||
* hacked for non-paged-MM by Hyok S. Choi, 2003.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@ -99,7 +100,9 @@ ENTRY(cpu_arm922_reset)
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
#endif
|
||||
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
|
||||
bic ip, ip, #0x000f @ ............wcam
|
||||
bic ip, ip, #0x1100 @ ...i...s........
|
||||
@ -321,6 +324,7 @@ ENTRY(cpu_arm922_dcache_clean_area)
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_arm922_switch_mm)
|
||||
#ifdef CONFIG_MMU
|
||||
mov ip, #0
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
|
||||
@ -341,6 +345,7 @@ ENTRY(cpu_arm922_switch_mm)
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
@ -350,6 +355,7 @@ ENTRY(cpu_arm922_switch_mm)
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_arm922_set_pte)
|
||||
#ifdef CONFIG_MMU
|
||||
str r1, [r0], #-2048 @ linux version
|
||||
|
||||
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
|
||||
@ -376,6 +382,7 @@ ENTRY(cpu_arm922_set_pte)
|
||||
mov r0, r0
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||||
#endif /* CONFIG_MMU */
|
||||
mov pc, lr
|
||||
|
||||
__INIT
|
||||
@ -385,7 +392,9 @@ __arm922_setup:
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
|
||||
#endif
|
||||
mrc p15, 0, r0, c1, c0 @ get control register v4
|
||||
ldr r5, arm922_cr1_clear
|
||||
bic r0, r0, r5
|
||||
|
||||
@ -9,6 +9,8 @@
|
||||
* Update for Linux-2.6 and cache flush improvements
|
||||
* Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
|
||||
*
|
||||
* hacked for non-paged-MM by Hyok S. Choi, 2004.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
@ -122,7 +124,9 @@ ENTRY(cpu_arm925_reset)
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
#endif
|
||||
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
|
||||
bic ip, ip, #0x000f @ ............wcam
|
||||
bic ip, ip, #0x1100 @ ...i...s........
|
||||
@ -369,6 +373,7 @@ ENTRY(cpu_arm925_dcache_clean_area)
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_arm925_switch_mm)
|
||||
#ifdef CONFIG_MMU
|
||||
mov ip, #0
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
|
||||
@ -383,6 +388,7 @@ ENTRY(cpu_arm925_switch_mm)
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
@ -392,6 +398,7 @@ ENTRY(cpu_arm925_switch_mm)
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_arm925_set_pte)
|
||||
#ifdef CONFIG_MMU
|
||||
str r1, [r0], #-2048 @ linux version
|
||||
|
||||
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
|
||||
@ -420,6 +427,7 @@ ENTRY(cpu_arm925_set_pte)
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||||
#endif
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||||
#endif /* CONFIG_MMU */
|
||||
mov pc, lr
|
||||
|
||||
__INIT
|
||||
@ -438,7 +446,9 @@ __arm925_setup:
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
mov r0, #4 @ disable write-back on caches explicitly
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
*
|
||||
* Copyright (C) 1999-2001 ARM Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd.
|
||||
* hacked for non-paged-MM by Hyok S. Choi, 2003.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
@ -85,7 +86,9 @@ ENTRY(cpu_arm926_reset)
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
#endif
|
||||
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
|
||||
bic ip, ip, #0x000f @ ............wcam
|
||||
bic ip, ip, #0x1100 @ ...i...s........
|
||||
@ -329,6 +332,7 @@ ENTRY(cpu_arm926_dcache_clean_area)
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_arm926_switch_mm)
|
||||
#ifdef CONFIG_MMU
|
||||
mov ip, #0
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
|
||||
@ -341,6 +345,7 @@ ENTRY(cpu_arm926_switch_mm)
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
@ -350,6 +355,7 @@ ENTRY(cpu_arm926_switch_mm)
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_arm926_set_pte)
|
||||
#ifdef CONFIG_MMU
|
||||
str r1, [r0], #-2048 @ linux version
|
||||
|
||||
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
|
||||
@ -378,6 +384,7 @@ ENTRY(cpu_arm926_set_pte)
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||||
#endif
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
__INIT
|
||||
@ -387,7 +394,9 @@ __arm926_setup:
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
* linux/arch/arm/mm/proc-sa110.S
|
||||
*
|
||||
* Copyright (C) 1997-2002 Russell King
|
||||
* hacked for non-paged-MM by Hyok S. Choi, 2003.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
@ -67,7 +68,9 @@ ENTRY(cpu_sa110_reset)
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
#endif
|
||||
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
|
||||
bic ip, ip, #0x000f @ ............wcam
|
||||
bic ip, ip, #0x1100 @ ...i...s........
|
||||
@ -130,11 +133,15 @@ ENTRY(cpu_sa110_dcache_clean_area)
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_sa110_switch_mm)
|
||||
#ifdef CONFIG_MMU
|
||||
str lr, [sp, #-4]!
|
||||
bl v4wb_flush_kern_cache_all @ clears IP
|
||||
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
ldr pc, [sp], #4
|
||||
#else
|
||||
mov pc, lr
|
||||
#endif
|
||||
|
||||
/*
|
||||
* cpu_sa110_set_pte(ptep, pte)
|
||||
@ -143,6 +150,7 @@ ENTRY(cpu_sa110_switch_mm)
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_sa110_set_pte)
|
||||
#ifdef CONFIG_MMU
|
||||
str r1, [r0], #-2048 @ linux version
|
||||
|
||||
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
|
||||
@ -164,6 +172,7 @@ ENTRY(cpu_sa110_set_pte)
|
||||
mov r0, r0
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
__INIT
|
||||
@ -173,7 +182,9 @@ __sa110_setup:
|
||||
mov r10, #0
|
||||
mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
|
||||
mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
|
||||
#endif
|
||||
mrc p15, 0, r0, c1, c0 @ get control register v4
|
||||
ldr r5, sa110_cr1_clear
|
||||
bic r0, r0, r5
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
* linux/arch/arm/mm/proc-sa1100.S
|
||||
*
|
||||
* Copyright (C) 1997-2002 Russell King
|
||||
* hacked for non-paged-MM by Hyok S. Choi, 2003.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
@ -77,7 +78,9 @@ ENTRY(cpu_sa1100_reset)
|
||||
mov ip, #0
|
||||
mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
|
||||
mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
#endif
|
||||
mrc p15, 0, ip, c1, c0, 0 @ ctrl register
|
||||
bic ip, ip, #0x000f @ ............wcam
|
||||
bic ip, ip, #0x1100 @ ...i...s........
|
||||
@ -142,12 +145,16 @@ ENTRY(cpu_sa1100_dcache_clean_area)
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_sa1100_switch_mm)
|
||||
#ifdef CONFIG_MMU
|
||||
str lr, [sp, #-4]!
|
||||
bl v4wb_flush_kern_cache_all @ clears IP
|
||||
mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
|
||||
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
ldr pc, [sp], #4
|
||||
#else
|
||||
mov pc, lr
|
||||
#endif
|
||||
|
||||
/*
|
||||
* cpu_sa1100_set_pte(ptep, pte)
|
||||
@ -156,6 +163,7 @@ ENTRY(cpu_sa1100_switch_mm)
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(cpu_sa1100_set_pte)
|
||||
#ifdef CONFIG_MMU
|
||||
str r1, [r0], #-2048 @ linux version
|
||||
|
||||
eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
|
||||
@ -177,6 +185,7 @@ ENTRY(cpu_sa1100_set_pte)
|
||||
mov r0, r0
|
||||
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
__INIT
|
||||
@ -186,7 +195,9 @@ __sa1100_setup:
|
||||
mov r0, #0
|
||||
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
|
||||
#endif
|
||||
mrc p15, 0, r0, c1, c0 @ get control register v4
|
||||
ldr r5, sa1100_cr1_clear
|
||||
bic r0, r0, r5
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
* linux/arch/arm/mm/proc-v6.S
|
||||
*
|
||||
* Copyright (C) 2001 Deep Blue Solutions Ltd.
|
||||
* Modified by Catalin Marinas for noMMU support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
@ -88,6 +89,7 @@ ENTRY(cpu_v6_dcache_clean_area)
|
||||
* - we are not using split page tables
|
||||
*/
|
||||
ENTRY(cpu_v6_switch_mm)
|
||||
#ifdef CONFIG_MMU
|
||||
mov r2, #0
|
||||
ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
|
||||
#ifdef CONFIG_SMP
|
||||
@ -97,6 +99,7 @@ ENTRY(cpu_v6_switch_mm)
|
||||
mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
|
||||
mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
|
||||
mcr p15, 0, r1, c13, c0, 1 @ set context ID
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
@ -119,6 +122,7 @@ ENTRY(cpu_v6_switch_mm)
|
||||
* 1111 0 1 1 r/w r/w
|
||||
*/
|
||||
ENTRY(cpu_v6_set_pte)
|
||||
#ifdef CONFIG_MMU
|
||||
str r1, [r0], #-2048 @ linux version
|
||||
|
||||
bic r2, r1, #0x000003f0
|
||||
@ -145,6 +149,7 @@ ENTRY(cpu_v6_set_pte)
|
||||
|
||||
str r2, [r0]
|
||||
mcr p15, 0, r0, c7, c10, 1 @ flush_pte
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
|
||||
@ -194,12 +199,14 @@ __v6_setup:
|
||||
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
|
||||
mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
|
||||
mcr p15, 0, r0, c2, c0, 2 @ TTB control register
|
||||
#ifdef CONFIG_SMP
|
||||
orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
|
||||
#endif
|
||||
mcr p15, 0, r4, c2, c0, 1 @ load TTB1
|
||||
#endif /* CONFIG_MMU */
|
||||
#ifdef CONFIG_VFP
|
||||
mrc p15, 0, r0, c1, c0, 2
|
||||
orr r0, r0, #(0xf << 20)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user