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clk/samsung updates for v4.11:
- addition of the CPU clock configuration data for Exynos4412
Prime SoC variant,
- removal of driver for deprecated Exynos4415 SoC,
- switching from the syscore to regular system sleep PM ops
in the audio subsystem clocks controller driver,
- updates of the definitions of some "Network On Chip" related
clocks.
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Merge tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull Samsung clk updates from Sylwester Nawrocki:
- addition of the CPU clock configuration data for Exynos4412
Prime SoC variant,
- removal of driver for deprecated Exynos4415 SoC,
- switching from the syscore to regular system sleep PM ops
in the audio subsystem clocks controller driver,
- updates of the definitions of some "Network On Chip" related
clocks.
* tag 'clk-v4.11-samsung' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: Remove Exynos4415 driver (SoC not supported anymore)
clk: samsung: exynos-audss: Replace syscore PM with platform device PM
clk: samsung: exynos5433: Set NoC (Network On Chip) clocks as critical
clk: samsung: Add CPU clk configuration data for Exynos4412 Prime
This commit is contained in:
Stephen Boyd
commit
d07ed23f4c
@ -1,38 +0,0 @@
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* Samsung Exynos4415 Clock Controller
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The Exynos4415 clock controller generates and supplies clock to various
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consumer devices within the Exynos4415 SoC.
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Required properties:
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- compatible: should be one of the following:
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- "samsung,exynos4415-cmu" - for the main system clocks controller
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(CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
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- "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
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Controller (DMC) domain clock controller.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos4415.h header and can be used in device
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tree sources.
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Example 1: An example of a clock controller node is listed below.
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cmu: clock-controller@10030000 {
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compatible = "samsung,exynos4415-cmu";
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reg = <0x10030000 0x18000>;
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#clock-cells = <1>;
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};
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cmu-dmc: clock-controller@105C0000 {
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compatible = "samsung,exynos4415-cmu-dmc";
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reg = <0x105C0000 0x3000>;
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#clock-cells = <1>;
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};
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@ -5,7 +5,6 @@
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obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
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obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
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obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
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obj-$(CONFIG_SOC_EXYNOS4415) += clk-exynos4415.o
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obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
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obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
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obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
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@ -44,7 +44,7 @@ static unsigned long reg_save[][2] = {
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{ ASS_CLK_GATE, 0 },
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};
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static int exynos_audss_clk_suspend(void)
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static int exynos_audss_clk_suspend(struct device *dev)
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{
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int i;
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@ -54,18 +54,15 @@ static int exynos_audss_clk_suspend(void)
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return 0;
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}
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static void exynos_audss_clk_resume(void)
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static int exynos_audss_clk_resume(struct device *dev)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(reg_save); i++)
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writel(reg_save[i][1], reg_base + reg_save[i][0]);
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}
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static struct syscore_ops exynos_audss_clk_syscore_ops = {
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.suspend = exynos_audss_clk_suspend,
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.resume = exynos_audss_clk_resume,
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};
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return 0;
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}
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#endif /* CONFIG_PM_SLEEP */
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struct exynos_audss_clk_drvdata {
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@ -251,9 +248,6 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
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goto unregister;
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}
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#ifdef CONFIG_PM_SLEEP
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register_syscore_ops(&exynos_audss_clk_syscore_ops);
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#endif
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return 0;
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unregister:
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@ -267,10 +261,6 @@ unregister:
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static int exynos_audss_clk_remove(struct platform_device *pdev)
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{
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#ifdef CONFIG_PM_SLEEP
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unregister_syscore_ops(&exynos_audss_clk_syscore_ops);
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#endif
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of_clk_del_provider(pdev->dev.of_node);
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exynos_audss_clk_teardown();
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@ -281,10 +271,16 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
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SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_audss_clk_suspend,
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exynos_audss_clk_resume)
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};
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static struct platform_driver exynos_audss_clk_driver = {
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.driver = {
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.name = "exynos-audss-clk",
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.of_match_table = exynos_audss_clk_of_match,
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.pm = &exynos_audss_clk_pm_ops,
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},
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.probe = exynos_audss_clk_probe,
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.remove = exynos_audss_clk_remove,
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@ -1298,6 +1298,8 @@ static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst =
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};
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static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {
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PLL_35XX_RATE(1704000000, 213, 3, 0),
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PLL_35XX_RATE(1600000000, 200, 3, 0),
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PLL_35XX_RATE(1500000000, 250, 4, 0),
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PLL_35XX_RATE(1400000000, 175, 3, 0),
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PLL_35XX_RATE(1300000000, 325, 6, 0),
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@ -1421,6 +1423,8 @@ static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
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(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
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static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
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{ 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), },
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{ 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
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{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
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{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
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{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
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File diff suppressed because it is too large
Load Diff
@ -549,10 +549,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
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29, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
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ENABLE_ACLK_TOP, 26,
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CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
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CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
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ENABLE_ACLK_TOP, 25,
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CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
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CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
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ENABLE_ACLK_TOP, 24,
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CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
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@ -616,7 +616,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
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/* ENABLE_SCLK_TOP_MSCL */
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GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
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ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
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ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0),
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/* ENABLE_SCLK_TOP_CAM1 */
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GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
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@ -1382,7 +1382,7 @@ static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
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/* ENABLE_ACLK_MIF3 */
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GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
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ENABLE_ACLK_MIF3, 4,
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CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
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CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
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GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
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ENABLE_ACLK_MIF3, 1,
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CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
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@ -1,360 +0,0 @@
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/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Author: Chanwoo Choi <cw00.choi@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Device Tree binding constants for Samsung Exynos4415 clock controllers.
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*/
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#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
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#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
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/*
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* Let each exported clock get a unique index, which is used on DT-enabled
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* platforms to lookup the clock from a clock specifier. These indices are
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* therefore considered an ABI and so must not be changed. This implies
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* that new clocks should be added either in free spaces between clock groups
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* or at the end.
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*/
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/*
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* Main CMU
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*/
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#define CLK_OSCSEL 1
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#define CLK_FIN_PLL 2
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#define CLK_FOUT_APLL 3
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#define CLK_FOUT_MPLL 4
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#define CLK_FOUT_EPLL 5
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#define CLK_FOUT_G3D_PLL 6
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#define CLK_FOUT_ISP_PLL 7
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#define CLK_FOUT_DISP_PLL 8
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/* Muxes */
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#define CLK_MOUT_MPLL_USER_L 16
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#define CLK_MOUT_GDL 17
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#define CLK_MOUT_MPLL_USER_R 18
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#define CLK_MOUT_GDR 19
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#define CLK_MOUT_EBI 20
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#define CLK_MOUT_ACLK_200 21
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#define CLK_MOUT_ACLK_160 22
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#define CLK_MOUT_ACLK_100 23
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#define CLK_MOUT_ACLK_266 24
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#define CLK_MOUT_G3D_PLL 25
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#define CLK_MOUT_EPLL 26
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#define CLK_MOUT_EBI_1 27
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#define CLK_MOUT_ISP_PLL 28
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#define CLK_MOUT_DISP_PLL 29
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#define CLK_MOUT_MPLL_USER_T 30
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#define CLK_MOUT_ACLK_400_MCUISP 31
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#define CLK_MOUT_G3D_PLLSRC 32
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#define CLK_MOUT_CSIS1 33
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#define CLK_MOUT_CSIS0 34
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#define CLK_MOUT_CAM1 35
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#define CLK_MOUT_FIMC3_LCLK 36
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#define CLK_MOUT_FIMC2_LCLK 37
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#define CLK_MOUT_FIMC1_LCLK 38
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#define CLK_MOUT_FIMC0_LCLK 39
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#define CLK_MOUT_MFC 40
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#define CLK_MOUT_MFC_1 41
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#define CLK_MOUT_MFC_0 42
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#define CLK_MOUT_G3D 43
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#define CLK_MOUT_G3D_1 44
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#define CLK_MOUT_G3D_0 45
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#define CLK_MOUT_MIPI0 46
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#define CLK_MOUT_FIMD0 47
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#define CLK_MOUT_TSADC_ISP 48
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#define CLK_MOUT_UART_ISP 49
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#define CLK_MOUT_SPI1_ISP 50
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#define CLK_MOUT_SPI0_ISP 51
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#define CLK_MOUT_PWM_ISP 52
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#define CLK_MOUT_AUDIO0 53
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#define CLK_MOUT_TSADC 54
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#define CLK_MOUT_MMC2 55
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#define CLK_MOUT_MMC1 56
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#define CLK_MOUT_MMC0 57
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#define CLK_MOUT_UART3 58
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#define CLK_MOUT_UART2 59
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#define CLK_MOUT_UART1 60
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#define CLK_MOUT_UART0 61
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#define CLK_MOUT_SPI2 62
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#define CLK_MOUT_SPI1 63
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#define CLK_MOUT_SPI0 64
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#define CLK_MOUT_SPDIF 65
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#define CLK_MOUT_AUDIO2 66
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#define CLK_MOUT_AUDIO1 67
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#define CLK_MOUT_MPLL_USER_C 68
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#define CLK_MOUT_HPM 69
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#define CLK_MOUT_CORE 70
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#define CLK_MOUT_APLL 71
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#define CLK_MOUT_PXLASYNC_CSIS1_FIMC 72
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#define CLK_MOUT_PXLASYNC_CSIS0_FIMC 73
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#define CLK_MOUT_JPEG 74
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#define CLK_MOUT_JPEG1 75
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#define CLK_MOUT_JPEG0 76
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#define CLK_MOUT_ACLK_ISP0_300 77
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#define CLK_MOUT_ACLK_ISP0_400 78
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#define CLK_MOUT_ACLK_ISP0_300_USER 79
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#define CLK_MOUT_ACLK_ISP1_300 80
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#define CLK_MOUT_ACLK_ISP1_300_USER 81
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#define CLK_MOUT_HDMI 82
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/* Dividers */
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#define CLK_DIV_GPL 90
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#define CLK_DIV_GDL 91
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#define CLK_DIV_GPR 92
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#define CLK_DIV_GDR 93
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#define CLK_DIV_ACLK_400_MCUISP 94
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#define CLK_DIV_EBI 95
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#define CLK_DIV_ACLK_200 96
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#define CLK_DIV_ACLK_160 97
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#define CLK_DIV_ACLK_100 98
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#define CLK_DIV_ACLK_266 99
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#define CLK_DIV_CSIS1 100
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#define CLK_DIV_CSIS0 101
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#define CLK_DIV_CAM1 102
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#define CLK_DIV_FIMC3_LCLK 103
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#define CLK_DIV_FIMC2_LCLK 104
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#define CLK_DIV_FIMC1_LCLK 105
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#define CLK_DIV_FIMC0_LCLK 106
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#define CLK_DIV_TV_BLK 107
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#define CLK_DIV_MFC 108
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#define CLK_DIV_G3D 109
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#define CLK_DIV_MIPI0_PRE 110
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#define CLK_DIV_MIPI0 111
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#define CLK_DIV_FIMD0 112
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#define CLK_DIV_UART_ISP 113
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#define CLK_DIV_SPI1_ISP_PRE 114
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#define CLK_DIV_SPI1_ISP 115
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#define CLK_DIV_SPI0_ISP_PRE 116
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#define CLK_DIV_SPI0_ISP 117
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#define CLK_DIV_PWM_ISP 118
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#define CLK_DIV_PCM0 119
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#define CLK_DIV_AUDIO0 120
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#define CLK_DIV_TSADC_PRE 121
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#define CLK_DIV_TSADC 122
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#define CLK_DIV_MMC1_PRE 123
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#define CLK_DIV_MMC1 124
|
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#define CLK_DIV_MMC0_PRE 125
|
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#define CLK_DIV_MMC0 126
|
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#define CLK_DIV_MMC2_PRE 127
|
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#define CLK_DIV_MMC2 128
|
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#define CLK_DIV_UART3 129
|
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#define CLK_DIV_UART2 130
|
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#define CLK_DIV_UART1 131
|
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#define CLK_DIV_UART0 132
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#define CLK_DIV_SPI1_PRE 133
|
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#define CLK_DIV_SPI1 134
|
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#define CLK_DIV_SPI0_PRE 135
|
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#define CLK_DIV_SPI0 136
|
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#define CLK_DIV_SPI2_PRE 137
|
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#define CLK_DIV_SPI2 138
|
||||
#define CLK_DIV_PCM2 139
|
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#define CLK_DIV_AUDIO2 140
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#define CLK_DIV_PCM1 141
|
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#define CLK_DIV_AUDIO1 142
|
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#define CLK_DIV_I2S1 143
|
||||
#define CLK_DIV_PXLASYNC_CSIS1_FIMC 144
|
||||
#define CLK_DIV_PXLASYNC_CSIS0_FIMC 145
|
||||
#define CLK_DIV_JPEG 146
|
||||
#define CLK_DIV_CORE2 147
|
||||
#define CLK_DIV_APLL 148
|
||||
#define CLK_DIV_PCLK_DBG 149
|
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#define CLK_DIV_ATB 150
|
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#define CLK_DIV_PERIPH 151
|
||||
#define CLK_DIV_COREM1 152
|
||||
#define CLK_DIV_COREM0 153
|
||||
#define CLK_DIV_CORE 154
|
||||
#define CLK_DIV_HPM 155
|
||||
#define CLK_DIV_COPY 156
|
||||
|
||||
/* Gates */
|
||||
#define CLK_ASYNC_G3D 180
|
||||
#define CLK_ASYNC_MFCL 181
|
||||
#define CLK_ASYNC_TVX 182
|
||||
#define CLK_PPMULEFT 183
|
||||
#define CLK_GPIO_LEFT 184
|
||||
#define CLK_PPMUIMAGE 185
|
||||
#define CLK_QEMDMA2 186
|
||||
#define CLK_QEROTATOR 187
|
||||
#define CLK_SMMUMDMA2 188
|
||||
#define CLK_SMMUROTATOR 189
|
||||
#define CLK_MDMA2 190
|
||||
#define CLK_ROTATOR 191
|
||||
#define CLK_ASYNC_ISPMX 192
|
||||
#define CLK_ASYNC_MAUDIOX 193
|
||||
#define CLK_ASYNC_MFCR 194
|
||||
#define CLK_ASYNC_FSYSD 195
|
||||
#define CLK_ASYNC_LCD0X 196
|
||||
#define CLK_ASYNC_CAMX 197
|
||||
#define CLK_PPMURIGHT 198
|
||||
#define CLK_GPIO_RIGHT 199
|
||||
#define CLK_ANTIRBK_APBIF 200
|
||||
#define CLK_EFUSE_WRITER_APBIF 201
|
||||
#define CLK_MONOCNT 202
|
||||
#define CLK_TZPC6 203
|
||||
#define CLK_PROVISIONKEY1 204
|
||||
#define CLK_PROVISIONKEY0 205
|
||||
#define CLK_CMU_ISPPART 206
|
||||
#define CLK_TMU_APBIF 207
|
||||
#define CLK_KEYIF 208
|
||||
#define CLK_RTC 209
|
||||
#define CLK_WDT 210
|
||||
#define CLK_MCT 211
|
||||
#define CLK_SECKEY 212
|
||||
#define CLK_HDMI_CEC 213
|
||||
#define CLK_TZPC5 214
|
||||
#define CLK_TZPC4 215
|
||||
#define CLK_TZPC3 216
|
||||
#define CLK_TZPC2 217
|
||||
#define CLK_TZPC1 218
|
||||
#define CLK_TZPC0 219
|
||||
#define CLK_CMU_COREPART 220
|
||||
#define CLK_CMU_TOPPART 221
|
||||
#define CLK_PMU_APBIF 222
|
||||
#define CLK_SYSREG 223
|
||||
#define CLK_CHIP_ID 224
|
||||
#define CLK_SMMUFIMC_LITE2 225
|
||||
#define CLK_FIMC_LITE2 226
|
||||
#define CLK_PIXELASYNCM1 227
|
||||
#define CLK_PIXELASYNCM0 228
|
||||
#define CLK_PPMUCAMIF 229
|
||||
#define CLK_SMMUJPEG 230
|
||||
#define CLK_SMMUFIMC3 231
|
||||
#define CLK_SMMUFIMC2 232
|
||||
#define CLK_SMMUFIMC1 233
|
||||
#define CLK_SMMUFIMC0 234
|
||||
#define CLK_JPEG 235
|
||||
#define CLK_CSIS1 236
|
||||
#define CLK_CSIS0 237
|
||||
#define CLK_FIMC3 238
|
||||
#define CLK_FIMC2 239
|
||||
#define CLK_FIMC1 240
|
||||
#define CLK_FIMC0 241
|
||||
#define CLK_PPMUTV 242
|
||||
#define CLK_SMMUTV 243
|
||||
#define CLK_HDMI 244
|
||||
#define CLK_MIXER 245
|
||||
#define CLK_VP 246
|
||||
#define CLK_PPMUMFC_R 247
|
||||
#define CLK_PPMUMFC_L 248
|
||||
#define CLK_SMMUMFC_R 249
|
||||
#define CLK_SMMUMFC_L 250
|
||||
#define CLK_MFC 251
|
||||
#define CLK_PPMUG3D 252
|
||||
#define CLK_G3D 253
|
||||
#define CLK_PPMULCD0 254
|
||||
#define CLK_SMMUFIMD0 255
|
||||
#define CLK_DSIM0 256
|
||||
#define CLK_SMIES 257
|
||||
#define CLK_MIE0 258
|
||||
#define CLK_FIMD0 259
|
||||
#define CLK_TSADC 260
|
||||
#define CLK_PPMUFILE 261
|
||||
#define CLK_NFCON 262
|
||||
#define CLK_USBDEVICE 263
|
||||
#define CLK_USBHOST 264
|
||||
#define CLK_SROMC 265
|
||||
#define CLK_SDMMC2 266
|
||||
#define CLK_SDMMC1 267
|
||||
#define CLK_SDMMC0 268
|
||||
#define CLK_PDMA1 269
|
||||
#define CLK_PDMA0 270
|
||||
#define CLK_SPDIF 271
|
||||
#define CLK_PWM 272
|
||||
#define CLK_PCM2 273
|
||||
#define CLK_PCM1 274
|
||||
#define CLK_I2S1 275
|
||||
#define CLK_SPI2 276
|
||||
#define CLK_SPI1 277
|
||||
#define CLK_SPI0 278
|
||||
#define CLK_I2CHDMI 279
|
||||
#define CLK_I2C7 280
|
||||
#define CLK_I2C6 281
|
||||
#define CLK_I2C5 282
|
||||
#define CLK_I2C4 283
|
||||
#define CLK_I2C3 284
|
||||
#define CLK_I2C2 285
|
||||
#define CLK_I2C1 286
|
||||
#define CLK_I2C0 287
|
||||
#define CLK_UART3 288
|
||||
#define CLK_UART2 289
|
||||
#define CLK_UART1 290
|
||||
#define CLK_UART0 291
|
||||
|
||||
/* Special clocks */
|
||||
#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC 330
|
||||
#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC 331
|
||||
#define CLK_SCLK_JPEG 332
|
||||
#define CLK_SCLK_CSIS1 333
|
||||
#define CLK_SCLK_CSIS0 334
|
||||
#define CLK_SCLK_CAM1 335
|
||||
#define CLK_SCLK_FIMC3_LCLK 336
|
||||
#define CLK_SCLK_FIMC2_LCLK 337
|
||||
#define CLK_SCLK_FIMC1_LCLK 338
|
||||
#define CLK_SCLK_FIMC0_LCLK 339
|
||||
#define CLK_SCLK_PIXEL 340
|
||||
#define CLK_SCLK_HDMI 341
|
||||
#define CLK_SCLK_MIXER 342
|
||||
#define CLK_SCLK_MFC 343
|
||||
#define CLK_SCLK_G3D 344
|
||||
#define CLK_SCLK_MIPIDPHY4L 345
|
||||
#define CLK_SCLK_MIPI0 346
|
||||
#define CLK_SCLK_MDNIE0 347
|
||||
#define CLK_SCLK_FIMD0 348
|
||||
#define CLK_SCLK_PCM0 349
|
||||
#define CLK_SCLK_AUDIO0 350
|
||||
#define CLK_SCLK_TSADC 351
|
||||
#define CLK_SCLK_EBI 352
|
||||
#define CLK_SCLK_MMC2 353
|
||||
#define CLK_SCLK_MMC1 354
|
||||
#define CLK_SCLK_MMC0 355
|
||||
#define CLK_SCLK_I2S 356
|
||||
#define CLK_SCLK_PCM2 357
|
||||
#define CLK_SCLK_PCM1 358
|
||||
#define CLK_SCLK_AUDIO2 359
|
||||
#define CLK_SCLK_AUDIO1 360
|
||||
#define CLK_SCLK_SPDIF 361
|
||||
#define CLK_SCLK_SPI2 362
|
||||
#define CLK_SCLK_SPI1 363
|
||||
#define CLK_SCLK_SPI0 364
|
||||
#define CLK_SCLK_UART3 365
|
||||
#define CLK_SCLK_UART2 366
|
||||
#define CLK_SCLK_UART1 367
|
||||
#define CLK_SCLK_UART0 368
|
||||
#define CLK_SCLK_HDMIPHY 369
|
||||
|
||||
/*
|
||||
* Total number of clocks of main CMU.
|
||||
* NOTE: Must be equal to last clock ID increased by one.
|
||||
*/
|
||||
#define CLK_NR_CLKS 370
|
||||
|
||||
/*
|
||||
* CMU DMC
|
||||
*/
|
||||
#define CLK_DMC_FOUT_MPLL 1
|
||||
#define CLK_DMC_FOUT_BPLL 2
|
||||
|
||||
#define CLK_DMC_MOUT_MPLL 3
|
||||
#define CLK_DMC_MOUT_BPLL 4
|
||||
#define CLK_DMC_MOUT_DPHY 5
|
||||
#define CLK_DMC_MOUT_DMC_BUS 6
|
||||
|
||||
#define CLK_DMC_DIV_DMC 7
|
||||
#define CLK_DMC_DIV_DPHY 8
|
||||
#define CLK_DMC_DIV_DMC_PRE 9
|
||||
#define CLK_DMC_DIV_DMCP 10
|
||||
#define CLK_DMC_DIV_DMCD 11
|
||||
#define CLK_DMC_DIV_MPLL_PRE 12
|
||||
|
||||
/*
|
||||
* Total number of clocks of CMU_DMC.
|
||||
* NOTE: Must be equal to highest clock ID increased by one.
|
||||
*/
|
||||
#define NR_CLKS_DMC 13
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */
|
||||
Loading…
Reference in New Issue
Block a user