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drm/amd/display: DML2.1 Reintegration for Various Fixes
[Why and How] DML2.1 reintegration for several fixes and updates to the DML code. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Roman Li <roman.li@amd Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Austin Zheng
Alex Deucher
parent
20b5a8f9f4
commit
d07722e1fc
@ -79,7 +79,6 @@ CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_optimization := $(dml2_
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CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag)
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CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_shared.o := $(dml2_ccflags) $(frame_warn_flag)
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CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags)
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@ -101,7 +100,6 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_optimization.o :
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_shared.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags)
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@ -122,7 +120,6 @@ DML21 += src/inc/dml2_debug.o
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DML21 += src/dml2_core/dml2_core_dcn4.o
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DML21 += src/dml2_core/dml2_core_factory.o
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DML21 += src/dml2_core/dml2_core_dcn4_calcs.o
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DML21 += src/dml2_core/dml2_core_shared.o
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DML21 += src/dml2_dpmm/dml2_dpmm_dcn4.o
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DML21 += src/dml2_dpmm/dml2_dpmm_factory.o
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DML21 += src/dml2_mcg/dml2_mcg_dcn4.o
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@ -355,7 +355,7 @@ static const struct dml2_ip_capabilities dml2_dcn401_max_ip_caps = {
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.fams2 = {
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.max_allow_delay_us = 100 * 1000,
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.scheduling_delay_us = 125,
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.vertical_interrupt_ack_delay_us = 18,
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.vertical_interrupt_ack_delay_us = 40,
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.allow_programming_delay_us = 18,
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.min_allow_width_us = 20,
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.subvp_df_throttle_delay_us = 100,
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@ -151,6 +151,7 @@ struct dml2_soc_bb {
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double phy_downspread_percent;
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double dcn_downspread_percent;
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double dispclk_dppclk_vco_speed_mhz;
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bool no_dfs;
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bool do_urgent_latency_adjustment;
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unsigned int mem_word_bytes;
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unsigned int num_dcc_mcaches;
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@ -273,7 +273,6 @@ static void pack_mode_programming_params_with_implicit_subvp(struct dml2_core_in
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programming->fams2_required = display_cfg->stage3.fams2_required;
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dml2_core_calcs_get_global_fams2_programming(&core->clean_me_up.mode_lib, display_cfg, &programming->fams2_global_config);
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programming->fams2_global_config.features.bits.enable = display_cfg->stage3.fams2_required;
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}
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// Only loop over all the main streams (the implicit svp streams will be packed as part of the main stream)
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File diff suppressed because it is too large
Load Diff
@ -10,7 +10,7 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance
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{
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bool result = false;
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if (!out)
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if (out == 0)
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return false;
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memset(out, 0, sizeof(struct dml2_core_instance));
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@ -1,37 +0,0 @@
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// SPDX-License-Identifier: MIT
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//
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// Copyright 2024 Advanced Micro Devices, Inc.
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#ifndef __DML2_CORE_SHARED_H__
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#define __DML2_CORE_SHARED_H__
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#define __DML_VBA_DEBUG__
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#define __DML2_CALCS_MAX_VRATIO_PRE_OTO__ 4.0 //<brief Prefetch schedule max vratio for one to one scheduling calculation for prefetch
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#define __DML2_CALCS_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ 6.0 //<brief Prefetch schedule max vratio when enhance prefetch schedule acceleration is enabled and vstartup is earliest possible already
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#define __DML2_CALCS_DPP_INVALID__ 0
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#define __DML2_CALCS_DCFCLK_FACTOR__ 1.15 //<brief fudge factor for min dcfclk calclation
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#define __DML2_CALCS_PIPE_NO_PLANE__ 99
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#include "dml2_core_shared_types.h"
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#include "dml2_internal_shared_types.h"
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double dml2_core_shared_div_rem(double dividend, unsigned int divisor, unsigned int *remainder);
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const char *dml2_core_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type);
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const char *dml2_core_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type);
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bool dml2_core_shared_is_420(enum dml2_source_format_class source_format);
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bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_out_params);
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bool dml2_core_shared_mode_programming(struct dml2_core_calcs_mode_programming_ex *in_out_params);
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void dml2_core_shared_get_watermarks(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_dchub_watermark_regs *out);
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void dml2_core_shared_get_arb_params(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_display_arb_regs *out);
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void dml2_core_shared_get_pipe_regs(const struct dml2_display_cfg *display_cfg, struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_dchub_per_pipe_register_set *out, int pipe_index);
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void dml2_core_shared_get_stream_programming(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_per_stream_programming *out, int pipe_index);
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void dml2_core_shared_get_mcache_allocation(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_mcache_surface_allocation *out, int plane_idx);
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void dml2_core_shared_get_mall_allocation(struct dml2_core_internal_display_mode_lib *mode_lib, unsigned int *out, int pipe_index);
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void dml2_core_shared_get_plane_support_info(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct core_plane_support_info *out, int plane_idx);
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void dml2_core_shared_get_stream_support_info(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct core_stream_support_info *out, int plane_index);
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void dml2_core_shared_get_informative(const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_display_cfg_programming *out);
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void dml2_core_shared_cursor_dlg_reg(struct dml2_cursor_dlg_regs *cursor_dlg_regs, const struct dml2_get_cursor_dlg_reg *p);
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#endif
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@ -9,6 +9,15 @@
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#include "dml_top_display_cfg_types.h"
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#include "dml_top_types.h"
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#define __DML_VBA_DEBUG__
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#define __DML2_CALCS_MAX_VRATIO_PRE_OTO__ 4.0 //<brief max vratio for one-to-one prefetch bw scheduling
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#define __DML2_CALCS_MAX_VRATIO_PRE_EQU__ 6.0 //<brief max vratio for equalized prefetch bw scheduling
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#define __DML2_CALCS_MAX_VRATIO_PRE__ 8.0 //<brief max prefetch vratio register limit
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#define __DML2_CALCS_DPP_INVALID__ 0
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#define __DML2_CALCS_DCFCLK_FACTOR__ 1.15 //<brief fudge factor for min dcfclk calclation
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#define __DML2_CALCS_PIPE_NO_PLANE__ 99
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struct dml2_core_ip_params {
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unsigned int vblank_nom_default_us;
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unsigned int remote_iommu_outstanding_translations;
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@ -853,6 +862,9 @@ struct dml2_core_internal_SOCParametersList {
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double USRRetrainingLatency;
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double SMNLatency;
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double g6_temp_read_blackout_us;
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double max_urgent_latency_us;
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double df_response_time_us;
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enum dml2_qos_param_type qos_type;
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};
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struct dml2_core_calcs_mode_support_locals {
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@ -914,9 +926,7 @@ struct dml2_core_calcs_mode_support_locals {
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double HostVMInefficiencyFactor;
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double HostVMInefficiencyFactorPrefetch;
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unsigned int NextMaxVStartup;
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unsigned int MaxVStartup;
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bool AnyLinesForVMOrRowTooLarge;
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double PixelClockBackEndFactor;
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unsigned int NumDSCUnitRequired;
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@ -1197,11 +1207,14 @@ struct dml2_core_calcs_CalculatePrefetchSchedule_locals {
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double Tdmec;
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double Tdmsks;
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double prefetch_sw_bytes;
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double total_row_bytes;
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double prefetch_bw_pr;
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double bytes_pp;
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double dep_bytes;
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double min_Lsw_oto;
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double min_Lsw_equ;
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double Tsw_est1;
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double Tsw_est2;
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double Tsw_est3;
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double prefetch_bw1;
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double prefetch_bw2;
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@ -1333,6 +1346,10 @@ struct dml2_core_shared_get_urgent_bandwidth_required_locals {
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double tmp_nom_adj_factor_p1;
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double tmp_pref_adj_factor_p0;
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double tmp_pref_adj_factor_p1;
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double vm_row_bw;
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double flip_and_active_bw;
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double flip_and_prefetch_bw;
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double active_and_excess_bw;
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};
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struct dml2_core_shared_calculate_peak_bandwidth_required_locals {
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@ -1689,7 +1706,6 @@ struct dml2_core_calcs_CalculatePrefetchSchedule_params {
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enum dml2_output_format_class OutputFormat;
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unsigned int MaxInterDCNTileRepeaters;
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unsigned int VStartup;
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unsigned int MaxVStartup;
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unsigned int HostVMMinPageSize;
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bool DynamicMetadataEnable;
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bool DynamicMetadataVMEnabled;
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@ -0,0 +1,631 @@
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// SPDX-License-Identifier: MIT
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//
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// Copyright 2024 Advanced Micro Devices, Inc.
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#include "dml2_core_utils.h"
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double dml2_core_utils_div_rem(double dividend, unsigned int divisor, unsigned int *remainder)
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{
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*remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0);
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return dividend / divisor;
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}
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const char *dml2_core_utils_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type)
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{
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switch (bw_type) {
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case (dml2_core_internal_bw_sdp):
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return("dml2_core_internal_bw_sdp");
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case (dml2_core_internal_bw_dram):
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return("dml2_core_internal_bw_dram");
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case (dml2_core_internal_bw_max):
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return("dml2_core_internal_bw_max");
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default:
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return("dml2_core_internal_bw_unknown");
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}
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}
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bool dml2_core_utils_is_420(enum dml2_source_format_class source_format)
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{
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bool val = false;
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switch (source_format) {
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case dml2_444_8:
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val = 0;
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break;
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case dml2_444_16:
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val = 0;
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break;
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case dml2_444_32:
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val = 0;
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break;
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case dml2_444_64:
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val = 0;
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break;
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case dml2_420_8:
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val = 1;
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break;
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case dml2_420_10:
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val = 1;
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break;
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case dml2_420_12:
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val = 1;
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break;
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case dml2_rgbe_alpha:
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val = 0;
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break;
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case dml2_rgbe:
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val = 0;
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break;
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case dml2_mono_8:
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val = 0;
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break;
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case dml2_mono_16:
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val = 0;
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break;
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default:
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DML2_ASSERT(0);
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break;
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}
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return val;
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}
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void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only)
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{
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dml2_printf("DML: ===================================== \n");
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dml2_printf("DML: DML_MODE_SUPPORT_INFO_ST\n");
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if (!fail_only || support->ScaleRatioAndTapsSupport == 0)
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dml2_printf("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport);
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if (!fail_only || support->SourceFormatPixelAndScanSupport == 0)
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dml2_printf("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixelAndScanSupport);
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if (!fail_only || support->ViewportSizeSupport == 0)
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dml2_printf("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport);
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if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1)
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dml2_printf("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support->LinkRateDoesNotMatchDPVersion);
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if (!fail_only || support->LinkRateForMultistreamNotIndicated == 1)
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dml2_printf("DML: support: LinkRateForMultistreamNotIndicated = %d\n", support->LinkRateForMultistreamNotIndicated);
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if (!fail_only || support->BPPForMultistreamNotIndicated == 1)
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dml2_printf("DML: support: BPPForMultistreamNotIndicated = %d\n", support->BPPForMultistreamNotIndicated);
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if (!fail_only || support->MultistreamWithHDMIOreDP == 1)
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dml2_printf("DML: support: MultistreamWithHDMIOreDP = %d\n", support->MultistreamWithHDMIOreDP);
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if (!fail_only || support->ExceededMultistreamSlots == 1)
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dml2_printf("DML: support: ExceededMultistreamSlots = %d\n", support->ExceededMultistreamSlots);
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if (!fail_only || support->MSOOrODMSplitWithNonDPLink == 1)
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dml2_printf("DML: support: MSOOrODMSplitWithNonDPLink = %d\n", support->MSOOrODMSplitWithNonDPLink);
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if (!fail_only || support->NotEnoughLanesForMSO == 1)
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dml2_printf("DML: support: NotEnoughLanesForMSO = %d\n", support->NotEnoughLanesForMSO);
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if (!fail_only || support->P2IWith420 == 1)
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dml2_printf("DML: support: P2IWith420 = %d\n", support->P2IWith420);
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if (!fail_only || support->DSC422NativeNotSupported == 1)
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dml2_printf("DML: support: DSC422NativeNotSupported = %d\n", support->DSC422NativeNotSupported);
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if (!fail_only || support->DSCSlicesODMModeSupported == 0)
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dml2_printf("DML: support: DSCSlicesODMModeSupported = %d\n", support->DSCSlicesODMModeSupported);
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if (!fail_only || support->NotEnoughDSCUnits == 1)
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dml2_printf("DML: support: NotEnoughDSCUnits = %d\n", support->NotEnoughDSCUnits);
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if (!fail_only || support->NotEnoughDSCSlices == 1)
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dml2_printf("DML: support: NotEnoughDSCSlices = %d\n", support->NotEnoughDSCSlices);
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if (!fail_only || support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1)
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dml2_printf("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = %d\n", support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe);
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if (!fail_only || support->InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1)
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dml2_printf("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = %d\n", support->InvalidCombinationOfMALLUseForPStateAndStaticScreen);
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if (!fail_only || support->DSCCLKRequiredMoreThanSupported == 1)
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dml2_printf("DML: support: DSCCLKRequiredMoreThanSupported = %d\n", support->DSCCLKRequiredMoreThanSupported);
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if (!fail_only || support->PixelsPerLinePerDSCUnitSupport == 0)
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dml2_printf("DML: support: PixelsPerLinePerDSCUnitSupport = %d\n", support->PixelsPerLinePerDSCUnitSupport);
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if (!fail_only || support->DTBCLKRequiredMoreThanSupported == 1)
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dml2_printf("DML: support: DTBCLKRequiredMoreThanSupported = %d\n", support->DTBCLKRequiredMoreThanSupported);
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if (!fail_only || support->InvalidCombinationOfMALLUseForPState == 1)
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dml2_printf("DML: support: InvalidCombinationOfMALLUseForPState = %d\n", support->InvalidCombinationOfMALLUseForPState);
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if (!fail_only || support->ROBSupport == 0)
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dml2_printf("DML: support: ROBSupport = %d\n", support->ROBSupport);
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if (!fail_only || support->OutstandingRequestsSupport == 0)
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dml2_printf("DML: support: OutstandingRequestsSupport = %d\n", support->OutstandingRequestsSupport);
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if (!fail_only || support->OutstandingRequestsUrgencyAvoidance == 0)
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dml2_printf("DML: support: OutstandingRequestsUrgencyAvoidance = %d\n", support->OutstandingRequestsUrgencyAvoidance);
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if (!fail_only || support->DISPCLK_DPPCLK_Support == 0)
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dml2_printf("DML: support: DISPCLK_DPPCLK_Support = %d\n", support->DISPCLK_DPPCLK_Support);
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if (!fail_only || support->TotalAvailablePipesSupport == 0)
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dml2_printf("DML: support: TotalAvailablePipesSupport = %d\n", support->TotalAvailablePipesSupport);
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if (!fail_only || support->NumberOfOTGSupport == 0)
|
||||
dml2_printf("DML: support: NumberOfOTGSupport = %d\n", support->NumberOfOTGSupport);
|
||||
if (!fail_only || support->NumberOfHDMIFRLSupport == 0)
|
||||
dml2_printf("DML: support: NumberOfHDMIFRLSupport = %d\n", support->NumberOfHDMIFRLSupport);
|
||||
if (!fail_only || support->NumberOfDP2p0Support == 0)
|
||||
dml2_printf("DML: support: NumberOfDP2p0Support = %d\n", support->NumberOfDP2p0Support);
|
||||
if (!fail_only || support->EnoughWritebackUnits == 0)
|
||||
dml2_printf("DML: support: EnoughWritebackUnits = %d\n", support->EnoughWritebackUnits);
|
||||
if (!fail_only || support->WritebackScaleRatioAndTapsSupport == 0)
|
||||
dml2_printf("DML: support: WritebackScaleRatioAndTapsSupport = %d\n", support->WritebackScaleRatioAndTapsSupport);
|
||||
if (!fail_only || support->WritebackLatencySupport == 0)
|
||||
dml2_printf("DML: support: WritebackLatencySupport = %d\n", support->WritebackLatencySupport);
|
||||
if (!fail_only || support->CursorSupport == 0)
|
||||
dml2_printf("DML: support: CursorSupport = %d\n", support->CursorSupport);
|
||||
if (!fail_only || support->PitchSupport == 0)
|
||||
dml2_printf("DML: support: PitchSupport = %d\n", support->PitchSupport);
|
||||
if (!fail_only || support->ViewportExceedsSurface == 1)
|
||||
dml2_printf("DML: support: ViewportExceedsSurface = %d\n", support->ViewportExceedsSurface);
|
||||
if (!fail_only || support->PrefetchSupported == 0)
|
||||
dml2_printf("DML: support: PrefetchSupported = %d\n", support->PrefetchSupported);
|
||||
if (!fail_only || support->EnoughUrgentLatencyHidingSupport == 0)
|
||||
dml2_printf("DML: support: EnoughUrgentLatencyHidingSupport = %d\n", support->EnoughUrgentLatencyHidingSupport);
|
||||
if (!fail_only || support->AvgBandwidthSupport == 0)
|
||||
dml2_printf("DML: support: AvgBandwidthSupport = %d\n", support->AvgBandwidthSupport);
|
||||
if (!fail_only || support->DynamicMetadataSupported == 0)
|
||||
dml2_printf("DML: support: DynamicMetadataSupported = %d\n", support->DynamicMetadataSupported);
|
||||
if (!fail_only || support->VRatioInPrefetchSupported == 0)
|
||||
dml2_printf("DML: support: VRatioInPrefetchSupported = %d\n", support->VRatioInPrefetchSupported);
|
||||
if (!fail_only || support->PTEBufferSizeNotExceeded == 1)
|
||||
dml2_printf("DML: support: PTEBufferSizeNotExceeded = %d\n", support->PTEBufferSizeNotExceeded);
|
||||
if (!fail_only || support->DCCMetaBufferSizeNotExceeded == 1)
|
||||
dml2_printf("DML: support: DCCMetaBufferSizeNotExceeded = %d\n", support->DCCMetaBufferSizeNotExceeded);
|
||||
if (!fail_only || support->ExceededMALLSize == 1)
|
||||
dml2_printf("DML: support: ExceededMALLSize = %d\n", support->ExceededMALLSize);
|
||||
if (!fail_only || support->g6_temp_read_support == 0)
|
||||
dml2_printf("DML: support: g6_temp_read_support = %d\n", support->g6_temp_read_support);
|
||||
if (!fail_only || support->ImmediateFlipSupport == 0)
|
||||
dml2_printf("DML: support: ImmediateFlipSupport = %d\n", support->ImmediateFlipSupport);
|
||||
if (!fail_only || support->LinkCapacitySupport == 0)
|
||||
dml2_printf("DML: support: LinkCapacitySupport = %d\n", support->LinkCapacitySupport);
|
||||
|
||||
if (!fail_only || support->ModeSupport == 0)
|
||||
dml2_printf("DML: support: ModeSupport = %d\n", support->ModeSupport);
|
||||
dml2_printf("DML: ===================================== \n");
|
||||
}
|
||||
|
||||
const char *dml2_core_utils_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type)
|
||||
{
|
||||
switch (dml2_core_internal_soc_state_type) {
|
||||
case (dml2_core_internal_soc_state_sys_idle):
|
||||
return("dml2_core_internal_soc_state_sys_idle");
|
||||
case (dml2_core_internal_soc_state_sys_active):
|
||||
return("dml2_core_internal_soc_state_sys_active");
|
||||
case (dml2_core_internal_soc_state_svp_prefetch):
|
||||
return("dml2_core_internal_soc_state_svp_prefetch");
|
||||
case dml2_core_internal_soc_state_max:
|
||||
default:
|
||||
return("dml2_core_internal_soc_state_unknown");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg)
|
||||
{
|
||||
for (unsigned int k = 0; k < display_cfg->num_planes; k++) {
|
||||
double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc;
|
||||
if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) {
|
||||
switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format) {
|
||||
case dml2_444:
|
||||
out_bpp[k] = bpc * 3;
|
||||
break;
|
||||
case dml2_s422:
|
||||
out_bpp[k] = bpc * 2;
|
||||
break;
|
||||
case dml2_n422:
|
||||
out_bpp[k] = bpc * 2;
|
||||
break;
|
||||
case dml2_420:
|
||||
default:
|
||||
out_bpp[k] = bpc * 1.5;
|
||||
break;
|
||||
}
|
||||
} else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) {
|
||||
out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16;
|
||||
} else {
|
||||
out_bpp[k] = 0;
|
||||
}
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml2_printf("DML::%s: k=%d bpc=%f\n", __func__, k, bpc);
|
||||
dml2_printf("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable);
|
||||
dml2_printf("DML::%s: k=%d out_bpp=%f\n", __func__, k, out_bpp[k]);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int dml2_core_utils_round_to_multiple(unsigned int num, unsigned int multiple, bool up)
|
||||
{
|
||||
unsigned int remainder;
|
||||
|
||||
if (multiple == 0)
|
||||
return num;
|
||||
|
||||
remainder = num % multiple;
|
||||
if (remainder == 0)
|
||||
return num;
|
||||
|
||||
if (up)
|
||||
return (num + multiple - remainder);
|
||||
else
|
||||
return (num - remainder);
|
||||
}
|
||||
|
||||
unsigned int dml2_core_util_get_num_active_pipes(int unsigned num_planes, const struct core_display_cfg_support_info *cfg_support_info)
|
||||
{
|
||||
unsigned int num_active_pipes = 0;
|
||||
|
||||
for (unsigned int k = 0; k < num_planes; k++) {
|
||||
num_active_pipes = num_active_pipes + (unsigned int)cfg_support_info->plane_support_info[k].dpps_used;
|
||||
}
|
||||
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml2_printf("DML::%s: num_active_pipes = %d\n", __func__, num_active_pipes);
|
||||
#endif
|
||||
return num_active_pipes;
|
||||
}
|
||||
|
||||
void dml2_core_utils_pipe_plane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane)
|
||||
{
|
||||
unsigned int pipe_idx = 0;
|
||||
|
||||
for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) {
|
||||
pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__;
|
||||
}
|
||||
|
||||
for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) {
|
||||
for (int i = 0; i < cfg_support_info->plane_support_info[plane_idx].dpps_used; i++) {
|
||||
pipe_plane[pipe_idx] = plane_idx;
|
||||
pipe_idx++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg)
|
||||
{
|
||||
bool is_phantom = false;
|
||||
|
||||
if (plane_cfg->overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe ||
|
||||
plane_cfg->overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe_no_data_return) {
|
||||
is_phantom = true;
|
||||
}
|
||||
|
||||
return is_phantom;
|
||||
}
|
||||
|
||||
unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode)
|
||||
{
|
||||
switch (sw_mode) {
|
||||
case (dml2_sw_linear):
|
||||
return 256; break;
|
||||
case (dml2_sw_256b_2d):
|
||||
return 256; break;
|
||||
case (dml2_sw_4kb_2d):
|
||||
return 4096; break;
|
||||
case (dml2_sw_64kb_2d):
|
||||
return 65536; break;
|
||||
case (dml2_sw_256kb_2d):
|
||||
return 262144; break;
|
||||
case (dml2_gfx11_sw_linear):
|
||||
return 256; break;
|
||||
case (dml2_gfx11_sw_64kb_d):
|
||||
return 65536; break;
|
||||
case (dml2_gfx11_sw_64kb_d_t):
|
||||
return 65536; break;
|
||||
case (dml2_gfx11_sw_64kb_d_x):
|
||||
return 65536; break;
|
||||
case (dml2_gfx11_sw_64kb_r_x):
|
||||
return 65536; break;
|
||||
case (dml2_gfx11_sw_256kb_d_x):
|
||||
return 262144; break;
|
||||
case (dml2_gfx11_sw_256kb_r_x):
|
||||
return 262144; break;
|
||||
default:
|
||||
DML2_ASSERT(0);
|
||||
return 256;
|
||||
};
|
||||
}
|
||||
|
||||
|
||||
bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan)
|
||||
{
|
||||
bool is_vert = false;
|
||||
if (Scan == dml2_rotation_90 || Scan == dml2_rotation_270) {
|
||||
is_vert = true;
|
||||
} else {
|
||||
is_vert = false;
|
||||
}
|
||||
return is_vert;
|
||||
}
|
||||
|
||||
|
||||
int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode)
|
||||
{
|
||||
int unsigned version = 0;
|
||||
|
||||
if (sw_mode == dml2_sw_linear ||
|
||||
sw_mode == dml2_sw_256b_2d ||
|
||||
sw_mode == dml2_sw_4kb_2d ||
|
||||
sw_mode == dml2_sw_64kb_2d ||
|
||||
sw_mode == dml2_sw_256kb_2d) {
|
||||
version = 12;
|
||||
} else if (sw_mode == dml2_gfx11_sw_linear ||
|
||||
sw_mode == dml2_gfx11_sw_64kb_d ||
|
||||
sw_mode == dml2_gfx11_sw_64kb_d_t ||
|
||||
sw_mode == dml2_gfx11_sw_64kb_d_x ||
|
||||
sw_mode == dml2_gfx11_sw_64kb_r_x ||
|
||||
sw_mode == dml2_gfx11_sw_256kb_d_x ||
|
||||
sw_mode == dml2_gfx11_sw_256kb_r_x) {
|
||||
version = 11;
|
||||
} else {
|
||||
dml2_printf("ERROR: Invalid sw_mode setting! val=%u\n", sw_mode);
|
||||
DML2_ASSERT(0);
|
||||
}
|
||||
|
||||
return version;
|
||||
}
|
||||
|
||||
unsigned int dml2_core_utils_get_qos_param_index(unsigned long uclk_freq_khz, const struct dml2_dcn4_uclk_dpm_dependent_qos_params *per_uclk_dpm_params)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int index = 0;
|
||||
|
||||
for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) {
|
||||
dml2_printf("DML::%s: per_uclk_dpm_params[%d].minimum_uclk_khz = %d\n", __func__, i, per_uclk_dpm_params[i].minimum_uclk_khz);
|
||||
|
||||
if (i == 0)
|
||||
index = 0;
|
||||
else
|
||||
index = i - 1;
|
||||
|
||||
if (uclk_freq_khz < per_uclk_dpm_params[i].minimum_uclk_khz ||
|
||||
per_uclk_dpm_params[i].minimum_uclk_khz == 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
#if defined(__DML_VBA_DEBUG__)
|
||||
dml2_printf("DML::%s: uclk_freq_khz = %d\n", __func__, uclk_freq_khz);
|
||||
dml2_printf("DML::%s: index = %d\n", __func__, index);
|
||||
#endif
|
||||
return index;
|
||||
}
|
||||
|
||||
unsigned int dml2_core_utils_get_active_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table)
|
||||
{
|
||||
unsigned int i;
|
||||
bool clk_entry_found = 0;
|
||||
|
||||
for (i = 0; i < clk_table->uclk.num_clk_values; i++) {
|
||||
dml2_printf("DML::%s: clk_table.uclk.clk_values_khz[%d] = %d\n", __func__, i, clk_table->uclk.clk_values_khz[i]);
|
||||
|
||||
if (uclk_freq_khz == clk_table->uclk.clk_values_khz[i]) {
|
||||
clk_entry_found = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
dml2_assert(clk_entry_found);
|
||||
#if defined(__DML_VBA_DEBUG__)
|
||||
dml2_printf("DML::%s: uclk_freq_khz = %ld\n", __func__, uclk_freq_khz);
|
||||
dml2_printf("DML::%s: index = %d\n", __func__, i);
|
||||
#endif
|
||||
return i;
|
||||
}
|
||||
|
||||
bool dml2_core_utils_is_dual_plane(enum dml2_source_format_class source_format)
|
||||
{
|
||||
bool ret_val = 0;
|
||||
|
||||
if ((source_format == dml2_420_12) || (source_format == dml2_420_8) || (source_format == dml2_420_10) || (source_format == dml2_rgbe_alpha))
|
||||
ret_val = 1;
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
unsigned int dml2_core_utils_log_and_substract_if_non_zero(unsigned int a, unsigned int subtrahend)
|
||||
{
|
||||
if (a == 0)
|
||||
return 0;
|
||||
|
||||
return (math_log2_approx(a) - subtrahend);
|
||||
}
|
||||
|
||||
static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters *phantom, const struct dml2_stream_parameters *main,
|
||||
const struct dml2_implicit_svp_meta *meta)
|
||||
{
|
||||
memcpy(phantom, main, sizeof(struct dml2_stream_parameters));
|
||||
|
||||
phantom->timing.v_total = meta->v_total;
|
||||
phantom->timing.v_active = meta->v_active;
|
||||
phantom->timing.v_front_porch = meta->v_front_porch;
|
||||
phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active;
|
||||
phantom->timing.drr_config.enabled = false;
|
||||
}
|
||||
|
||||
static void create_phantom_plane_from_main_plane(struct dml2_plane_parameters *phantom, const struct dml2_plane_parameters *main,
|
||||
const struct dml2_stream_parameters *phantom_stream, int phantom_stream_index, const struct dml2_stream_parameters *main_stream)
|
||||
{
|
||||
memcpy(phantom, main, sizeof(struct dml2_plane_parameters));
|
||||
|
||||
phantom->stream_index = phantom_stream_index;
|
||||
phantom->overrides.refresh_from_mall = dml2_refresh_from_mall_mode_override_force_disable;
|
||||
phantom->overrides.legacy_svp_config = dml2_svp_mode_override_phantom_pipe_no_data_return;
|
||||
phantom->composition.viewport.plane0.height = (long int unsigned) math_min2(math_ceil2(
|
||||
(double)main->composition.scaler_info.plane0.v_ratio * (double)phantom_stream->timing.v_active, 16.0),
|
||||
(double)main->composition.viewport.plane0.height);
|
||||
phantom->composition.viewport.plane1.height = (long int unsigned) math_min2(math_ceil2(
|
||||
(double)main->composition.scaler_info.plane1.v_ratio * (double)phantom_stream->timing.v_active, 16.0),
|
||||
(double)main->composition.viewport.plane1.height);
|
||||
phantom->immediate_flip = false;
|
||||
phantom->dynamic_meta_data.enable = false;
|
||||
phantom->cursor.num_cursors = 0;
|
||||
phantom->cursor.cursor_width = 0;
|
||||
phantom->tdlut.setup_for_tdlut = false;
|
||||
}
|
||||
|
||||
void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct dml2_display_cfg *svp_expanded_display_cfg,
|
||||
struct dml2_core_scratch *scratch)
|
||||
{
|
||||
unsigned int stream_index, plane_index;
|
||||
const struct dml2_plane_parameters *main_plane;
|
||||
const struct dml2_stream_parameters *main_stream;
|
||||
const struct dml2_stream_parameters *phantom_stream;
|
||||
|
||||
memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg));
|
||||
memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);
|
||||
memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES);
|
||||
memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES);
|
||||
|
||||
if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo)
|
||||
return;
|
||||
|
||||
/* disable unbounded requesting for all planes until stage 3 has been performed */
|
||||
if (!display_cfg->stage3.performed) {
|
||||
svp_expanded_display_cfg->overrides.hw.force_unbounded_requesting.enable = true;
|
||||
svp_expanded_display_cfg->overrides.hw.force_unbounded_requesting.value = false;
|
||||
}
|
||||
// Create the phantom streams
|
||||
for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) {
|
||||
main_stream = &display_cfg->display_config.stream_descriptors[stream_index];
|
||||
scratch->main_stream_index_from_svp_stream_index[stream_index] = stream_index;
|
||||
scratch->svp_stream_index_from_main_stream_index[stream_index] = stream_index;
|
||||
|
||||
if (display_cfg->stage3.stream_svp_meta[stream_index].valid) {
|
||||
// Create the phantom stream
|
||||
create_phantom_stream_from_main_stream(&svp_expanded_display_cfg->stream_descriptors[svp_expanded_display_cfg->num_streams],
|
||||
main_stream, &display_cfg->stage3.stream_svp_meta[stream_index]);
|
||||
|
||||
// Associate this phantom stream to the main stream
|
||||
scratch->main_stream_index_from_svp_stream_index[svp_expanded_display_cfg->num_streams] = stream_index;
|
||||
scratch->svp_stream_index_from_main_stream_index[stream_index] = svp_expanded_display_cfg->num_streams;
|
||||
|
||||
// Increment num streams
|
||||
svp_expanded_display_cfg->num_streams++;
|
||||
}
|
||||
}
|
||||
|
||||
// Create the phantom planes
|
||||
for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) {
|
||||
main_plane = &display_cfg->display_config.plane_descriptors[plane_index];
|
||||
|
||||
if (display_cfg->stage3.stream_svp_meta[main_plane->stream_index].valid) {
|
||||
main_stream = &display_cfg->display_config.stream_descriptors[main_plane->stream_index];
|
||||
phantom_stream = &svp_expanded_display_cfg->stream_descriptors[scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index]];
|
||||
create_phantom_plane_from_main_plane(&svp_expanded_display_cfg->plane_descriptors[svp_expanded_display_cfg->num_planes],
|
||||
main_plane, phantom_stream, scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index], main_stream);
|
||||
|
||||
// Associate this phantom plane to the main plane
|
||||
scratch->phantom_plane_index_to_main_plane_index[svp_expanded_display_cfg->num_planes] = plane_index;
|
||||
scratch->main_plane_index_to_phantom_plane_index[plane_index] = svp_expanded_display_cfg->num_planes;
|
||||
|
||||
// Increment num planes
|
||||
svp_expanded_display_cfg->num_planes++;
|
||||
|
||||
// Adjust the main plane settings
|
||||
svp_expanded_display_cfg->plane_descriptors[plane_index].overrides.legacy_svp_config = dml2_svp_mode_override_main_pipe;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool dml2_core_utils_is_stream_encoder_required(const struct dml2_stream_parameters *stream_descriptor)
|
||||
{
|
||||
switch (stream_descriptor->output.output_encoder) {
|
||||
case dml2_dp:
|
||||
case dml2_dp2p0:
|
||||
case dml2_edp:
|
||||
case dml2_hdmi:
|
||||
case dml2_hdmifrl:
|
||||
return true;
|
||||
case dml2_none:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
bool dml2_core_utils_is_encoder_dsc_capable(const struct dml2_stream_parameters *stream_descriptor)
|
||||
{
|
||||
switch (stream_descriptor->output.output_encoder) {
|
||||
case dml2_dp:
|
||||
case dml2_dp2p0:
|
||||
case dml2_edp:
|
||||
case dml2_hdmifrl:
|
||||
return true;
|
||||
case dml2_hdmi:
|
||||
case dml2_none:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
bool dml2_core_utils_is_dio_dp_encoder(const struct dml2_stream_parameters *stream_descriptor)
|
||||
{
|
||||
switch (stream_descriptor->output.output_encoder) {
|
||||
case dml2_dp:
|
||||
case dml2_edp:
|
||||
return true;
|
||||
case dml2_dp2p0:
|
||||
case dml2_hdmi:
|
||||
case dml2_hdmifrl:
|
||||
case dml2_none:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool dml2_core_utils_is_hpo_dp_encoder(const struct dml2_stream_parameters *stream_descriptor)
|
||||
{
|
||||
switch (stream_descriptor->output.output_encoder) {
|
||||
case dml2_dp2p0:
|
||||
return true;
|
||||
case dml2_dp:
|
||||
case dml2_edp:
|
||||
case dml2_hdmi:
|
||||
case dml2_hdmifrl:
|
||||
case dml2_none:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool dml2_core_utils_is_dp_encoder(const struct dml2_stream_parameters *stream_descriptor)
|
||||
{
|
||||
return dml2_core_utils_is_dio_dp_encoder(stream_descriptor)
|
||||
|| dml2_core_utils_is_hpo_dp_encoder(stream_descriptor);
|
||||
}
|
||||
|
||||
|
||||
bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate)
|
||||
{
|
||||
switch (rate) {
|
||||
case dml2_dp_rate_hbr:
|
||||
case dml2_dp_rate_hbr2:
|
||||
case dml2_dp_rate_hbr3:
|
||||
return true;
|
||||
case dml2_dp_rate_na:
|
||||
case dml2_dp_rate_uhbr10:
|
||||
case dml2_dp_rate_uhbr13p5:
|
||||
case dml2_dp_rate_uhbr20:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate)
|
||||
{
|
||||
switch (rate) {
|
||||
case dml2_dp_rate_uhbr10:
|
||||
case dml2_dp_rate_uhbr13p5:
|
||||
case dml2_dp_rate_uhbr20:
|
||||
return true;
|
||||
case dml2_dp_rate_hbr:
|
||||
case dml2_dp_rate_hbr2:
|
||||
case dml2_dp_rate_hbr3:
|
||||
case dml2_dp_rate_na:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode)
|
||||
{
|
||||
switch (odm_mode) {
|
||||
case dml2_odm_mode_split_1to2:
|
||||
case dml2_odm_mode_mso_1to2:
|
||||
case dml2_odm_mode_mso_1to4:
|
||||
return true;
|
||||
case dml2_odm_mode_auto:
|
||||
case dml2_odm_mode_bypass:
|
||||
case dml2_odm_mode_combine_2to1:
|
||||
case dml2_odm_mode_combine_3to1:
|
||||
case dml2_odm_mode_combine_4to1:
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,39 @@
|
||||
// SPDX-License-Identifier: MIT
|
||||
//
|
||||
// Copyright 2024 Advanced Micro Devices, Inc.
|
||||
|
||||
#ifndef __DML2_CORE_UTILS_H__
|
||||
#define __DML2_CORE_UTILS_H__
|
||||
#include "dml2_internal_shared_types.h"
|
||||
#include "dml2_debug.h"
|
||||
#include "lib_float_math.h"
|
||||
|
||||
double dml2_core_utils_div_rem(double dividend, unsigned int divisor, unsigned int *remainder);
|
||||
const char *dml2_core_utils_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type);
|
||||
bool dml2_core_utils_is_420(enum dml2_source_format_class source_format);
|
||||
void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only);
|
||||
const char *dml2_core_utils_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type);
|
||||
void dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg);
|
||||
unsigned int dml2_core_utils_round_to_multiple(unsigned int num, unsigned int multiple, bool up);
|
||||
unsigned int dml2_core_util_get_num_active_pipes(int unsigned num_planes, const struct core_display_cfg_support_info *cfg_support_info);
|
||||
void dml2_core_utils_pipe_plane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane);
|
||||
bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg);
|
||||
unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode);
|
||||
bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan);
|
||||
int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode);
|
||||
unsigned int dml2_core_utils_get_qos_param_index(unsigned long uclk_freq_khz, const struct dml2_dcn4_uclk_dpm_dependent_qos_params *per_uclk_dpm_params);
|
||||
unsigned int dml2_core_utils_get_active_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table);
|
||||
bool dml2_core_utils_is_dual_plane(enum dml2_source_format_class source_format);
|
||||
unsigned int dml2_core_utils_log_and_substract_if_non_zero(unsigned int a, unsigned int subtrahend);
|
||||
void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct dml2_display_cfg *svp_expanded_display_cfg,
|
||||
struct dml2_core_scratch *scratch);
|
||||
bool dml2_core_utils_is_stream_encoder_required(const struct dml2_stream_parameters *stream_descriptor);
|
||||
bool dml2_core_utils_is_encoder_dsc_capable(const struct dml2_stream_parameters *stream_descriptor);
|
||||
bool dml2_core_utils_is_dp_encoder(const struct dml2_stream_parameters *stream_descriptor);
|
||||
bool dml2_core_utils_is_dio_dp_encoder(const struct dml2_stream_parameters *stream_descriptor);
|
||||
bool dml2_core_utils_is_hpo_dp_encoder(const struct dml2_stream_parameters *stream_descriptor);
|
||||
bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate);
|
||||
bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate);
|
||||
bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode);
|
||||
|
||||
#endif /* __DML2_CORE_UTILS_H__ */
|
||||
@ -203,6 +203,26 @@ static bool add_margin_and_round_to_dfs_grainularity(double clock_khz, double ma
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool round_to_non_dfs_granularity(unsigned long dispclk_khz, unsigned long dpprefclk_khz, unsigned long dtbrefclk_khz,
|
||||
unsigned long *rounded_dispclk_khz, unsigned long *rounded_dpprefclk_khz, unsigned long *rounded_dtbrefclk_khz)
|
||||
{
|
||||
unsigned long pll_frequency_khz;
|
||||
|
||||
pll_frequency_khz = (unsigned long) math_max2(600000, math_ceil2(math_max3(dispclk_khz, dpprefclk_khz, dtbrefclk_khz), 1000));
|
||||
|
||||
*rounded_dispclk_khz = pll_frequency_khz / (unsigned long) math_min2(pll_frequency_khz / dispclk_khz, 32);
|
||||
|
||||
*rounded_dpprefclk_khz = pll_frequency_khz / (unsigned long) math_min2(pll_frequency_khz / dpprefclk_khz, 32);
|
||||
|
||||
if (dtbrefclk_khz > 0) {
|
||||
*rounded_dtbrefclk_khz = pll_frequency_khz / (unsigned long) math_min2(pll_frequency_khz / dtbrefclk_khz, 32);
|
||||
} else {
|
||||
*rounded_dtbrefclk_khz = 0;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool round_up_and_copy_to_next_dpm(unsigned long min_value, unsigned long *rounded_value, const struct dml2_clk_table *clock_table)
|
||||
{
|
||||
bool result = false;
|
||||
@ -555,31 +575,39 @@ static bool map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_o
|
||||
// but still the required dispclk can be more than the maximum dispclk speed:
|
||||
dispclk_khz = math_max2(dispclk_khz, mode_support_result->global.dispclk_khz * (1 + in_out->soc_bb->dcn_downspread_percent / 100.0));
|
||||
|
||||
add_margin_and_round_to_dfs_grainularity(dispclk_khz, 0.0,
|
||||
(unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dispclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dispclk_did);
|
||||
|
||||
// DPP Ref is always set to max of all DPP clocks
|
||||
for (i = 0; i < DML2_MAX_DCN_PIPES; i++) {
|
||||
if (in_out->programming->min_clocks.dcn4x.dpprefclk_khz < mode_support_result->per_plane[i].dppclk_khz)
|
||||
in_out->programming->min_clocks.dcn4x.dpprefclk_khz = mode_support_result->per_plane[i].dppclk_khz;
|
||||
}
|
||||
|
||||
add_margin_and_round_to_dfs_grainularity(in_out->programming->min_clocks.dcn4x.dpprefclk_khz, in_out->soc_bb->dcn_downspread_percent / 100.0,
|
||||
(unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dpprefclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dpprefclk_did);
|
||||
|
||||
for (i = 0; i < DML2_MAX_DCN_PIPES; i++) {
|
||||
in_out->programming->plane_programming[i].min_clocks.dcn4x.dppclk_khz = (unsigned long)(in_out->programming->min_clocks.dcn4x.dpprefclk_khz / 255.0
|
||||
* math_ceil2(in_out->display_cfg->mode_support_result.per_plane[i].dppclk_khz * (1.0 + in_out->soc_bb->dcn_downspread_percent / 100.0) * 255.0 / in_out->programming->min_clocks.dcn4x.dpprefclk_khz, 1.0));
|
||||
}
|
||||
in_out->programming->min_clocks.dcn4x.dpprefclk_khz = (unsigned long) (in_out->programming->min_clocks.dcn4x.dpprefclk_khz * (1 + in_out->soc_bb->dcn_downspread_percent / 100.0));
|
||||
|
||||
// DTB Ref is always set to max of all DTB clocks
|
||||
for (i = 0; i < DML2_MAX_DCN_PIPES; i++) {
|
||||
if (in_out->programming->min_clocks.dcn4x.dtbrefclk_khz < mode_support_result->per_stream[i].dtbclk_khz)
|
||||
in_out->programming->min_clocks.dcn4x.dtbrefclk_khz = mode_support_result->per_stream[i].dtbclk_khz;
|
||||
}
|
||||
in_out->programming->min_clocks.dcn4x.dtbrefclk_khz = (unsigned long)(in_out->programming->min_clocks.dcn4x.dtbrefclk_khz * (1 + in_out->soc_bb->dcn_downspread_percent / 100.0));
|
||||
|
||||
add_margin_and_round_to_dfs_grainularity(in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, in_out->soc_bb->dcn_downspread_percent / 100.0,
|
||||
(unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dtbrefclk_did);
|
||||
if (in_out->soc_bb->no_dfs) {
|
||||
round_to_non_dfs_granularity((unsigned long)dispclk_khz, in_out->programming->min_clocks.dcn4x.dpprefclk_khz, in_out->programming->min_clocks.dcn4x.dtbrefclk_khz,
|
||||
&in_out->programming->min_clocks.dcn4x.dispclk_khz, &in_out->programming->min_clocks.dcn4x.dpprefclk_khz, &in_out->programming->min_clocks.dcn4x.dtbrefclk_khz);
|
||||
} else {
|
||||
add_margin_and_round_to_dfs_grainularity(dispclk_khz, 0.0,
|
||||
(unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dispclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dispclk_did);
|
||||
|
||||
add_margin_and_round_to_dfs_grainularity(in_out->programming->min_clocks.dcn4x.dpprefclk_khz, 0.0,
|
||||
(unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dpprefclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dpprefclk_did);
|
||||
|
||||
add_margin_and_round_to_dfs_grainularity(in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, 0.0,
|
||||
(unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dtbrefclk_did);
|
||||
}
|
||||
|
||||
|
||||
for (i = 0; i < DML2_MAX_DCN_PIPES; i++) {
|
||||
in_out->programming->plane_programming[i].min_clocks.dcn4x.dppclk_khz = (unsigned long)(in_out->programming->min_clocks.dcn4x.dpprefclk_khz / 255.0
|
||||
* math_ceil2(in_out->display_cfg->mode_support_result.per_plane[i].dppclk_khz * (1.0 + in_out->soc_bb->dcn_downspread_percent / 100.0) * 255.0 / in_out->programming->min_clocks.dcn4x.dpprefclk_khz, 1.0));
|
||||
}
|
||||
|
||||
in_out->programming->min_clocks.dcn4x.deepsleep_dcfclk_khz = mode_support_result->global.dcfclk_deepsleep_khz;
|
||||
in_out->programming->min_clocks.dcn4x.socclk_khz = mode_support_result->global.socclk_khz;
|
||||
|
||||
@ -20,7 +20,7 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance
|
||||
{
|
||||
bool result = false;
|
||||
|
||||
if (!out)
|
||||
if (out == 0)
|
||||
return false;
|
||||
|
||||
memset(out, 0, sizeof(struct dml2_dpmm_instance));
|
||||
|
||||
@ -718,7 +718,7 @@ bool pmo_dcn4_fams2_init_for_vmin(struct dml2_pmo_init_for_vmin_in_out *in_out)
|
||||
const struct dml2_core_mode_support_result *mode_support_result =
|
||||
&in_out->base_display_config->mode_support_result;
|
||||
struct dml2_optimization_stage4_state *state =
|
||||
&in_out->base_display_config->stage4;
|
||||
&in_out->base_display_config->stage4;
|
||||
|
||||
if (in_out->instance->options->disable_dyn_odm ||
|
||||
(in_out->instance->options->disable_dyn_odm_for_multi_stream && display_config->num_streams > 1))
|
||||
@ -1444,7 +1444,7 @@ static bool stream_matches_drr_policy(struct dml2_pmo_instance *pmo,
|
||||
/* DRR variable strategies are disallowed due to settings or policy */
|
||||
strategy_matches_drr_requirements = false;
|
||||
} else if (is_bit_set_in_bitfield(PMO_DRR_CLAMPED_STRATEGY_MASK, stream_pstate_method) &&
|
||||
(pmo->options->disable_drr_clamped ||
|
||||
(pmo->options->disable_drr_clamped ||
|
||||
(!stream_descriptor->timing.drr_config.enabled ||
|
||||
(!stream_descriptor->timing.drr_config.drr_active_fixed && !stream_descriptor->timing.drr_config.drr_active_variable)) ||
|
||||
(pmo->options->disable_drr_clamped_when_var_active &&
|
||||
@ -1910,7 +1910,8 @@ static void setup_planes_for_vblank_by_mask(struct display_configuation_with_met
|
||||
if (is_bit_set_in_bitfield(plane_mask, plane_index)) {
|
||||
plane = &display_config->display_config.plane_descriptors[plane_index];
|
||||
|
||||
plane->overrides.reserved_vblank_time_ns = (long)(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us * 1000);
|
||||
plane->overrides.reserved_vblank_time_ns = (long)math_max2(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us * 1000.0,
|
||||
plane->overrides.reserved_vblank_time_ns);
|
||||
|
||||
display_config->stage3.pstate_switch_modes[plane_index] = dml2_uclk_pstate_support_method_vblank;
|
||||
|
||||
@ -2196,15 +2197,15 @@ bool pmo_dcn4_fams2_test_for_stutter(struct dml2_pmo_test_for_stutter_in_out *in
|
||||
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < in_out->base_display_config->display_config.num_streams; i++) {
|
||||
for (i = 0; i < in_out->base_display_config->display_config.num_planes; i++) {
|
||||
if (pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us > 0 &&
|
||||
pmo->scratch.pmo_dcn4.z8_vblank_optimizable &&
|
||||
in_out->base_display_config->display_config.stream_descriptors[i].overrides.minimum_vblank_idle_requirement_us < (int)pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us) {
|
||||
in_out->base_display_config->display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns < (int)pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us * 1000) {
|
||||
success = false;
|
||||
break;
|
||||
}
|
||||
if (pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us > 0 &&
|
||||
in_out->base_display_config->display_config.stream_descriptors[i].overrides.minimum_vblank_idle_requirement_us < (int)pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us) {
|
||||
in_out->base_display_config->display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns < (int)pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us * 1000) {
|
||||
success = false;
|
||||
break;
|
||||
}
|
||||
@ -2223,8 +2224,11 @@ bool pmo_dcn4_fams2_optimize_for_stutter(struct dml2_pmo_optimize_for_stutter_in
|
||||
|
||||
if (!in_out->last_candidate_failed) {
|
||||
if (pmo->scratch.pmo_dcn4.cur_stutter_candidate < pmo->scratch.pmo_dcn4.num_stutter_candidates) {
|
||||
for (i = 0; i < in_out->optimized_display_config->display_config.num_streams; i++) {
|
||||
in_out->optimized_display_config->display_config.stream_descriptors[i].overrides.minimum_vblank_idle_requirement_us = pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.cur_stutter_candidate];
|
||||
for (i = 0; i < in_out->optimized_display_config->display_config.num_planes; i++) {
|
||||
/* take the max of the current and the optimal reserved time */
|
||||
in_out->optimized_display_config->display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns =
|
||||
(long)math_max2(pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.cur_stutter_candidate] * 1000,
|
||||
in_out->optimized_display_config->display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns);
|
||||
}
|
||||
|
||||
success = true;
|
||||
|
||||
@ -26,7 +26,7 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance *
|
||||
{
|
||||
bool result = false;
|
||||
|
||||
if (!out)
|
||||
if (out == 0)
|
||||
return false;
|
||||
|
||||
memset(out, 0, sizeof(struct dml2_pmo_instance));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user