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pinctrl: renesas: r8a779g0: Add missing HSCIF1_X
This patch adds missing HSCIF1. Because Document (Rev.0.51) has 2x HSCIF1 with no suffix (_A, _B), this patch names it as _X. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87wncxsjah.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Kuninori Morimoto
Geert Uytterhoeven
parent
213b713255
commit
cf4f789184
@ -301,13 +301,13 @@
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#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_27_24 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_31_28 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
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#define IP1SR1_3_0 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_7_4 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_11_8 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_N_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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@ -809,15 +809,22 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
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PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
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PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
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PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_X),
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PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
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PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_X),
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/* IP1SR1 */
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PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
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PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_N_X),
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PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
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PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_N_X),
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PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
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PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_X),
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PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
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@ -1524,6 +1531,29 @@ static const unsigned int hscif1_ctrl_mux[] = {
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HRTS1_N_MARK, HCTS1_N_MARK,
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};
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/* - HSCIF1_X---------------------------------------------------------------- */
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static const unsigned int hscif1_data_x_pins[] = {
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/* HRX1_X, HTX1_X */
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RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
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};
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static const unsigned int hscif1_data_x_mux[] = {
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HRX1_X_MARK, HTX1_X_MARK,
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};
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static const unsigned int hscif1_clk_x_pins[] = {
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/* HSCK1_X */
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RCAR_GP_PIN(1, 10),
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};
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static const unsigned int hscif1_clk_x_mux[] = {
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HSCK1_X_MARK,
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};
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static const unsigned int hscif1_ctrl_x_pins[] = {
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/* HRTS1_N_X, HCTS1_N_X */
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RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
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};
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static const unsigned int hscif1_ctrl_x_mux[] = {
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HRTS1_N_X_MARK, HCTS1_N_X_MARK,
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};
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/* - HSCIF2 ----------------------------------------------------------------- */
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static const unsigned int hscif2_data_pins[] = {
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/* HRX2, HTX2 */
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@ -2345,9 +2375,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(hscif0_data),
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SH_PFC_PIN_GROUP(hscif0_clk),
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SH_PFC_PIN_GROUP(hscif0_ctrl),
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SH_PFC_PIN_GROUP(hscif1_data),
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SH_PFC_PIN_GROUP(hscif1_clk),
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SH_PFC_PIN_GROUP(hscif1_ctrl),
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SH_PFC_PIN_GROUP(hscif1_data), /* suffix might be updated */
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SH_PFC_PIN_GROUP(hscif1_clk), /* suffix might be updated */
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SH_PFC_PIN_GROUP(hscif1_ctrl), /* suffix might be updated */
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SH_PFC_PIN_GROUP(hscif1_data_x), /* suffix might be updated */
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SH_PFC_PIN_GROUP(hscif1_clk_x), /* suffix might be updated */
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SH_PFC_PIN_GROUP(hscif1_ctrl_x), /* suffix might be updated */
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SH_PFC_PIN_GROUP(hscif2_data),
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SH_PFC_PIN_GROUP(hscif2_clk),
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SH_PFC_PIN_GROUP(hscif2_ctrl),
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@ -2544,9 +2577,13 @@ static const char * const hscif0_groups[] = {
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};
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static const char * const hscif1_groups[] = {
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/* suffix might be updated */
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"hscif1_data",
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"hscif1_clk",
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"hscif1_ctrl",
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"hscif1_data_x",
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"hscif1_clk_x",
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"hscif1_ctrl_x",
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};
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static const char * const hscif2_groups[] = {
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