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arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC
Add initial DTSI for RZ/G2UL SoC. Both RZ/G2L and RZ/G2UL uses the same SMARC EVK. Therefore they share the common dtsi (rz-smarc.dtsi) file. Place holders are added in device nodes to avoid compilation errors for the devices which have not been enabled yet on RZ/G2UL SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220412161314.13800-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das
Geert Uytterhoeven
parent
0faf567d6d
commit
cf40c9689e
413
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
Normal file
413
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
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@ -0,0 +1,413 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the RZ/G2UL SoC
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*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r9a07g043-cpg.h>
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/ {
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compatible = "renesas,r9a07g043";
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#address-cells = <2>;
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#size-cells = <2>;
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audio_clk1: audio-clk1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by boards that provide it */
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clock-frequency = <0>;
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};
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audio_clk2: audio-clk2 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by boards that provide it */
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clock-frequency = <0>;
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};
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/* External CAN clock - to be overridden by boards that provide it */
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can_clk: can-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
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extal_clk: extal-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a55";
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reg = <0>;
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device_type = "cpu";
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next-level-cache = <&L3_CA55>;
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enable-method = "psci";
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clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
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};
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L3_CA55: cache-controller-0 {
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compatible = "cache";
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cache-unified;
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cache-size = <0x40000>;
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};
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ssi0: ssi@10049c00 {
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reg = <0 0x10049c00 0 0x400>;
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#sound-dai-cells = <0>;
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/* place holder */
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};
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spi1: spi@1004b000 {
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reg = <0 0x1004b000 0 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* place holder */
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};
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scif0: serial@1004b800 {
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compatible = "renesas,scif-r9a07g043",
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"renesas,scif-r9a07g044";
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reg = <0 0x1004b800 0 0x400>;
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interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi",
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"bri", "dri", "tei";
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clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
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status = "disabled";
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};
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scif1: serial@1004bc00 {
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compatible = "renesas,scif-r9a07g043",
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"renesas,scif-r9a07g044";
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reg = <0 0x1004bc00 0 0x400>;
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interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi",
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"bri", "dri", "tei";
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clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>;
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status = "disabled";
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};
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scif2: serial@1004c000 {
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compatible = "renesas,scif-r9a07g043",
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"renesas,scif-r9a07g044";
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reg = <0 0x1004c000 0 0x400>;
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interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi",
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"bri", "dri", "tei";
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clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>;
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status = "disabled";
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};
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scif3: serial@1004c400 {
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compatible = "renesas,scif-r9a07g043",
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"renesas,scif-r9a07g044";
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reg = <0 0x1004c400 0 0x400>;
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interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi",
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"bri", "dri", "tei";
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clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>;
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status = "disabled";
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};
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scif4: serial@1004c800 {
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compatible = "renesas,scif-r9a07g043",
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"renesas,scif-r9a07g044";
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reg = <0 0x1004c800 0 0x400>;
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interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi",
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"bri", "dri", "tei";
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clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>;
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status = "disabled";
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};
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sci0: serial@1004d000 {
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compatible = "renesas,r9a07g043-sci", "renesas,sci";
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reg = <0 0x1004d000 0 0x400>;
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interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_SCI0_RST>;
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status = "disabled";
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};
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sci1: serial@1004d400 {
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compatible = "renesas,r9a07g043-sci", "renesas,sci";
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reg = <0 0x1004d400 0 0x400>;
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interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eri", "rxi", "txi", "tei";
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clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
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clock-names = "fck";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_SCI1_RST>;
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status = "disabled";
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};
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canfd: can@10050000 {
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reg = <0 0x10050000 0 0x8000>;
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/* place holder */
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};
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i2c0: i2c@10058000 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x10058000 0 0x400>;
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/* place holder */
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};
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i2c1: i2c@10058400 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x10058400 0 0x400>;
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/* place holder */
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};
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i2c3: i2c@10058c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x10058c00 0 0x400>;
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/* place holder */
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};
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adc: adc@10059000 {
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reg = <0 0x10059000 0 0x400>;
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/* place holder */
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};
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sbc: spi@10060000 {
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reg = <0 0x10060000 0 0x10000>,
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<0 0x20000000 0 0x10000000>,
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<0 0x10070000 0 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* place holder */
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};
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cpg: clock-controller@11010000 {
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compatible = "renesas,r9a07g043-cpg";
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reg = <0 0x11010000 0 0x10000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#reset-cells = <1>;
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#power-domain-cells = <0>;
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};
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sysc: system-controller@11020000 {
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compatible = "renesas,r9a07g043-sysc";
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reg = <0 0x11020000 0 0x10000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "lpm_int", "ca55stbydone_int",
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"cm33stbyr_int", "ca55_deny";
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status = "disabled";
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};
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pinctrl: pinctrl@11030000 {
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reg = <0 0x11030000 0 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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/* place holder */
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};
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dmac: dma-controller@11820000 {
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compatible = "renesas,r9a07g043-dmac",
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"renesas,rz-dmac";
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reg = <0 0x11820000 0 0x10000>,
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<0 0x11830000 0 0x10000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14", "ch15";
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clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
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<&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
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power-domains = <&cpg>;
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resets = <&cpg R9A07G043_DMAC_ARESETN>,
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<&cpg R9A07G043_DMAC_RST_ASYNC>;
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#dma-cells = <1>;
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dma-channels = <16>;
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};
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gic: interrupt-controller@11900000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0x11900000 0 0x40000>,
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<0x0 0x11940000 0 0x60000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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sdhi0: mmc@11c00000 {
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reg = <0x0 0x11c00000 0 0x10000>;
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/* place holder */
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};
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sdhi1: mmc@11c10000 {
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reg = <0x0 0x11c10000 0 0x10000>;
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/* place holder */
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};
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phyrst: usbphy-ctrl@11c40000 {
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reg = <0 0x11c40000 0 0x10000>;
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/* place holder */
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};
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ohci0: usb@11c50000 {
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reg = <0 0x11c50000 0 0x100>;
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/* place holder */
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};
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ohci1: usb@11c70000 {
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reg = <0 0x11c70000 0 0x100>;
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/* place holder */
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};
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ehci0: usb@11c50100 {
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reg = <0 0x11c50100 0 0x100>;
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/* place holder */
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};
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ehci1: usb@11c70100 {
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reg = <0 0x11c70100 0 0x100>;
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/* place holder */
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};
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usb2_phy0: usb-phy@11c50200 {
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reg = <0 0x11c50200 0 0x700>;
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/* place holder */
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};
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usb2_phy1: usb-phy@11c70200 {
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reg = <0 0x11c70200 0 0x700>;
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/* place holder */
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};
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hsusb: usb@11c60000 {
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reg = <0 0x11c60000 0 0x10000>;
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/* place holder */
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};
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wdt0: watchdog@12800800 {
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reg = <0 0x12800800 0 0x400>;
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/* place holder */
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};
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wdt2: watchdog@12800400 {
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reg = <0 0x12800400 0 0x400>;
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/* place holder */
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};
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ostm0: timer@12801000 {
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reg = <0x0 0x12801000 0x0 0x400>;
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/* place holder */
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};
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ostm1: timer@12801400 {
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reg = <0x0 0x12801400 0x0 0x400>;
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/* place holder */
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};
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ostm2: timer@12801800 {
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reg = <0x0 0x12801800 0x0 0x400>;
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/* place holder */
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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