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drm/i915: Replace to_bpp_int_roundup() with fxp_q4_to_int_roundup()

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Replace the to_bpp_int_roundup() helper defined by the driver with the
equivalent fxp_q4_to_int_roundup() helper defined by DRM core.

v2: Rebase on s/drm_x16/fxp_q4 change.

Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240805150802.3568970-4-imre.deak@intel.com
This commit is contained in:
Imre Deak 2024-08-05 18:07:52 +03:00
parent 8466a14173
commit ce9b1466f5
4 changed files with 8 additions and 10 deletions
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5
drivers/gpu/drm/i915/display/intel_cdclk.c
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@ -23,7 +23,10 @@
#include <linux/time.h>
#include <drm/drm_fixed.h>
#include "soc/intel_dram.h"
#include "hsw_ips.h"
#include "i915_reg.h"
#include "intel_atomic.h"
@ -2750,7 +2753,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
*/
int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
int min_cdclk_bj =
(to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
(fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
pixel_clock) / (2 * bigjoiner_interface_bits);
min_cdclk = max(min_cdclk, min_cdclk_bj);

5
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -2208,11 +2208,6 @@ static inline int to_bpp_frac(int bpp_x16)
#define BPP_X16_FMT "%d.%04d"
#define BPP_X16_ARGS(bpp_x16) fxp_q4_to_int(bpp_x16), (to_bpp_frac(bpp_x16) * 625)
static inline int to_bpp_int_roundup(int bpp_x16)
{
return (bpp_x16 + 0xf) >> 4;
}
/*
* Conversion functions/macros from various pointer types to struct
* intel_display pointer.

6
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -2101,7 +2101,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
@ -2263,7 +2263,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
@ -2489,7 +2489,7 @@ int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
int bpp = crtc_state->dsc.compression_enable ?
to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
crtc_state->pipe_bpp;
return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);

2
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@ -379,7 +379,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
min_compressed_bpp = max(min_compressed_bpp,
to_bpp_int_roundup(limits->link.min_bpp_x16));
fxp_q4_to_int_roundup(limits->link.min_bpp_x16));
drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",
min_compressed_bpp, max_compressed_bpp);