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MIPS: OCTEON: Add support for OCTEON III interrupt controller.
Add irq_chip support for both IPI and "normal" interrupts of the CIU3 controller. Document the device tree binding for the CIU3. Some functions are non-static as they will be used by follow-on support for MSI-X. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: devicetree@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12500/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
9bc2223995
commit
ce210d35bb
27
Documentation/devicetree/bindings/mips/cavium/ciu3.txt
Normal file
27
Documentation/devicetree/bindings/mips/cavium/ciu3.txt
Normal file
@ -0,0 +1,27 @@
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* Central Interrupt Unit v3
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Properties:
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- compatible: "cavium,octeon-7890-ciu3"
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Compatibility with 78XX and 73XX SOCs.
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- interrupt-controller: This is an interrupt controller.
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- reg: The base address of the CIU's register bank.
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- #interrupt-cells: Must be <2>. The first cell is source number.
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The second cell indicates the triggering semantics, and may have a
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value of either 4 for level semantics, or 1 for edge semantics.
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Example:
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interrupt-controller@1010000000000 {
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compatible = "cavium,octeon-7890-ciu3";
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interrupt-controller;
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/* Interrupts are specified by two parts:
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* 1) Source number (20 significant bits)
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* 2) Trigger type: (4 == level, 1 == edge)
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*/
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x10100 0x00000000 0x0 0xb0000000>;
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};
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@ -19,15 +19,52 @@
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-ciu2-defs.h>
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#include <asm/octeon/cvmx-ciu3-defs.h>
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static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror);
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static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror);
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static DEFINE_PER_CPU(raw_spinlock_t, octeon_irq_ciu_spinlock);
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static DEFINE_PER_CPU(unsigned int, octeon_irq_ciu3_idt_ip2);
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static DEFINE_PER_CPU(unsigned int, octeon_irq_ciu3_idt_ip3);
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static DEFINE_PER_CPU(struct octeon_ciu3_info *, octeon_ciu3_info);
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#define CIU3_MBOX_PER_CORE 10
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/*
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* The 8 most significant bits of the intsn identify the interrupt major block.
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* Each major block might use its own interrupt domain. Thus 256 domains are
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* needed.
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*/
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#define MAX_CIU3_DOMAINS 256
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typedef irq_hw_number_t (*octeon_ciu3_intsn2hw_t)(struct irq_domain *, unsigned int);
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/* Information for each ciu3 in the system */
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struct octeon_ciu3_info {
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u64 ciu3_addr;
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int node;
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struct irq_domain *domain[MAX_CIU3_DOMAINS];
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octeon_ciu3_intsn2hw_t intsn2hw[MAX_CIU3_DOMAINS];
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};
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/* Each ciu3 in the system uses its own data (one ciu3 per node) */
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static struct octeon_ciu3_info *octeon_ciu3_info_per_node[4];
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struct octeon_irq_ciu_domain_data {
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int num_sum; /* number of sum registers (2 or 3). */
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};
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/* Register offsets from ciu3_addr */
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#define CIU3_CONST 0x220
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#define CIU3_IDT_CTL(_idt) ((_idt) * 8 + 0x110000)
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#define CIU3_IDT_PP(_idt, _idx) ((_idt) * 32 + (_idx) * 8 + 0x120000)
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#define CIU3_IDT_IO(_idt) ((_idt) * 8 + 0x130000)
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#define CIU3_DEST_PP_INT(_pp_ip) ((_pp_ip) * 8 + 0x200000)
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#define CIU3_DEST_IO_INT(_io) ((_io) * 8 + 0x210000)
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#define CIU3_ISC_CTL(_intsn) ((_intsn) * 8 + 0x80000000)
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#define CIU3_ISC_W1C(_intsn) ((_intsn) * 8 + 0x90000000)
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#define CIU3_ISC_W1S(_intsn) ((_intsn) * 8 + 0xa0000000)
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static __read_mostly int octeon_irq_ciu_to_irq[8][64];
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struct octeon_ciu_chip_data {
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@ -39,10 +76,11 @@ struct octeon_ciu_chip_data {
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struct { /* only used for ciu/ciu2 */
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u8 line;
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u8 bit;
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u8 gpio_line;
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};
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};
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int gpio_line;
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int current_cpu; /* Next CPU expected to take this irq */
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int ciu_node; /* NUMA node number of the CIU */
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};
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struct octeon_core_chip_data {
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@ -626,6 +664,18 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data)
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}
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}
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static int octeon_irq_ciu_set_type(struct irq_data *data, unsigned int t)
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{
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irqd_set_trigger_type(data, t);
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if (t & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(data, handle_edge_irq);
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else
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irq_set_handler_locked(data, handle_level_irq);
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return IRQ_SET_MASK_OK;
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}
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static void octeon_irq_gpio_setup(struct irq_data *data)
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{
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union cvmx_gpio_bit_cfgx cfg;
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@ -863,6 +913,16 @@ static int octeon_irq_ciu_set_affinity_sum2(struct irq_data *data,
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}
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#endif
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static unsigned int edge_startup(struct irq_data *data)
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{
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/* ack any pending edge-irq at startup, so there is
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* an _edge_ to fire on when the event reappears.
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*/
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data->chip->irq_ack(data);
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data->chip->irq_enable(data);
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return 0;
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}
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/*
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* Newer octeon chips have support for lockless CIU operation.
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*/
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@ -2271,10 +2331,598 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
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return 0;
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}
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int octeon_irq_ciu3_xlat(struct irq_domain *d,
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struct device_node *node,
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const u32 *intspec,
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unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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struct octeon_ciu3_info *ciu3_info = d->host_data;
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unsigned int hwirq, type, intsn_major;
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union cvmx_ciu3_iscx_ctl isc;
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if (intsize < 2)
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return -EINVAL;
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hwirq = intspec[0];
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type = intspec[1];
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if (hwirq >= (1 << 20))
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return -EINVAL;
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intsn_major = hwirq >> 12;
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switch (intsn_major) {
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case 0x04: /* Software handled separately. */
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return -EINVAL;
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default:
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break;
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}
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isc.u64 = cvmx_read_csr(ciu3_info->ciu3_addr + CIU3_ISC_CTL(hwirq));
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if (!isc.s.imp)
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return -EINVAL;
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switch (type) {
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case 4: /* official value for level triggering. */
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*out_type = IRQ_TYPE_LEVEL_HIGH;
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break;
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case 0: /* unofficial value, but we might as well let it work. */
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case 1: /* official value for edge triggering. */
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*out_type = IRQ_TYPE_EDGE_RISING;
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break;
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default: /* Nothing else is acceptable. */
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return -EINVAL;
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}
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*out_hwirq = hwirq;
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return 0;
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}
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void octeon_irq_ciu3_enable(struct irq_data *data)
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{
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int cpu;
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union cvmx_ciu3_iscx_ctl isc_ctl;
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union cvmx_ciu3_iscx_w1c isc_w1c;
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u64 isc_ctl_addr;
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struct octeon_ciu_chip_data *cd;
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cpu = next_cpu_for_irq(data);
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cd = irq_data_get_irq_chip_data(data);
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isc_w1c.u64 = 0;
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isc_w1c.s.en = 1;
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cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64);
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isc_ctl_addr = cd->ciu3_addr + CIU3_ISC_CTL(cd->intsn);
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isc_ctl.u64 = 0;
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isc_ctl.s.en = 1;
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isc_ctl.s.idt = per_cpu(octeon_irq_ciu3_idt_ip2, cpu);
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cvmx_write_csr(isc_ctl_addr, isc_ctl.u64);
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cvmx_read_csr(isc_ctl_addr);
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}
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void octeon_irq_ciu3_disable(struct irq_data *data)
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{
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u64 isc_ctl_addr;
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union cvmx_ciu3_iscx_w1c isc_w1c;
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struct octeon_ciu_chip_data *cd;
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cd = irq_data_get_irq_chip_data(data);
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isc_w1c.u64 = 0;
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isc_w1c.s.en = 1;
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isc_ctl_addr = cd->ciu3_addr + CIU3_ISC_CTL(cd->intsn);
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cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64);
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cvmx_write_csr(isc_ctl_addr, 0);
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cvmx_read_csr(isc_ctl_addr);
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}
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void octeon_irq_ciu3_ack(struct irq_data *data)
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{
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u64 isc_w1c_addr;
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union cvmx_ciu3_iscx_w1c isc_w1c;
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struct octeon_ciu_chip_data *cd;
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u32 trigger_type = irqd_get_trigger_type(data);
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/*
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* We use a single irq_chip, so we have to do nothing to ack a
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* level interrupt.
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*/
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if (!(trigger_type & IRQ_TYPE_EDGE_BOTH))
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return;
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cd = irq_data_get_irq_chip_data(data);
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isc_w1c.u64 = 0;
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isc_w1c.s.raw = 1;
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isc_w1c_addr = cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn);
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cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);
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cvmx_read_csr(isc_w1c_addr);
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}
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void octeon_irq_ciu3_mask(struct irq_data *data)
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{
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union cvmx_ciu3_iscx_w1c isc_w1c;
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u64 isc_w1c_addr;
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struct octeon_ciu_chip_data *cd;
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cd = irq_data_get_irq_chip_data(data);
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isc_w1c.u64 = 0;
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isc_w1c.s.en = 1;
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isc_w1c_addr = cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn);
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cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);
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cvmx_read_csr(isc_w1c_addr);
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}
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void octeon_irq_ciu3_mask_ack(struct irq_data *data)
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{
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union cvmx_ciu3_iscx_w1c isc_w1c;
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u64 isc_w1c_addr;
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struct octeon_ciu_chip_data *cd;
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u32 trigger_type = irqd_get_trigger_type(data);
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cd = irq_data_get_irq_chip_data(data);
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isc_w1c.u64 = 0;
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isc_w1c.s.en = 1;
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/*
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* We use a single irq_chip, so only ack an edge (!level)
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* interrupt.
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*/
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if (trigger_type & IRQ_TYPE_EDGE_BOTH)
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isc_w1c.s.raw = 1;
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isc_w1c_addr = cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn);
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cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);
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cvmx_read_csr(isc_w1c_addr);
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}
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#ifdef CONFIG_SMP
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int octeon_irq_ciu3_set_affinity(struct irq_data *data,
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const struct cpumask *dest, bool force)
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{
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union cvmx_ciu3_iscx_ctl isc_ctl;
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union cvmx_ciu3_iscx_w1c isc_w1c;
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u64 isc_ctl_addr;
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int cpu;
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bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
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struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data);
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if (!cpumask_subset(dest, cpumask_of_node(cd->ciu_node)))
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return -EINVAL;
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if (!enable_one)
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return IRQ_SET_MASK_OK;
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cd = irq_data_get_irq_chip_data(data);
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cpu = cpumask_first(dest);
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if (cpu >= nr_cpu_ids)
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cpu = smp_processor_id();
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cd->current_cpu = cpu;
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isc_w1c.u64 = 0;
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isc_w1c.s.en = 1;
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cvmx_write_csr(cd->ciu3_addr + CIU3_ISC_W1C(cd->intsn), isc_w1c.u64);
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isc_ctl_addr = cd->ciu3_addr + CIU3_ISC_CTL(cd->intsn);
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isc_ctl.u64 = 0;
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isc_ctl.s.en = 1;
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isc_ctl.s.idt = per_cpu(octeon_irq_ciu3_idt_ip2, cpu);
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cvmx_write_csr(isc_ctl_addr, isc_ctl.u64);
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cvmx_read_csr(isc_ctl_addr);
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return IRQ_SET_MASK_OK;
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}
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#endif
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static struct irq_chip octeon_irq_chip_ciu3 = {
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.name = "CIU3",
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.irq_startup = edge_startup,
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.irq_enable = octeon_irq_ciu3_enable,
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.irq_disable = octeon_irq_ciu3_disable,
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.irq_ack = octeon_irq_ciu3_ack,
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.irq_mask = octeon_irq_ciu3_mask,
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.irq_mask_ack = octeon_irq_ciu3_mask_ack,
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.irq_unmask = octeon_irq_ciu3_enable,
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.irq_set_type = octeon_irq_ciu_set_type,
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#ifdef CONFIG_SMP
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.irq_set_affinity = octeon_irq_ciu3_set_affinity,
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.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
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#endif
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};
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int octeon_irq_ciu3_mapx(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw, struct irq_chip *chip)
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{
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struct octeon_ciu3_info *ciu3_info = d->host_data;
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struct octeon_ciu_chip_data *cd = kzalloc_node(sizeof(*cd), GFP_KERNEL,
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ciu3_info->node);
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if (!cd)
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return -ENOMEM;
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cd->intsn = hw;
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cd->current_cpu = -1;
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cd->ciu3_addr = ciu3_info->ciu3_addr;
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cd->ciu_node = ciu3_info->node;
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irq_set_chip_and_handler(virq, chip, handle_edge_irq);
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irq_set_chip_data(virq, cd);
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return 0;
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}
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static int octeon_irq_ciu3_map(struct irq_domain *d,
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unsigned int virq, irq_hw_number_t hw)
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{
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return octeon_irq_ciu3_mapx(d, virq, hw, &octeon_irq_chip_ciu3);
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}
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static struct irq_domain_ops octeon_dflt_domain_ciu3_ops = {
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.map = octeon_irq_ciu3_map,
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.unmap = octeon_irq_free_cd,
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.xlate = octeon_irq_ciu3_xlat,
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};
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static void octeon_irq_ciu3_ip2(void)
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{
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union cvmx_ciu3_destx_pp_int dest_pp_int;
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struct octeon_ciu3_info *ciu3_info;
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u64 ciu3_addr;
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ciu3_info = __this_cpu_read(octeon_ciu3_info);
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ciu3_addr = ciu3_info->ciu3_addr;
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dest_pp_int.u64 = cvmx_read_csr(ciu3_addr + CIU3_DEST_PP_INT(3 * cvmx_get_local_core_num()));
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if (likely(dest_pp_int.s.intr)) {
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irq_hw_number_t intsn = dest_pp_int.s.intsn;
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irq_hw_number_t hw;
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struct irq_domain *domain;
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/* Get the domain to use from the major block */
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int block = intsn >> 12;
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int ret;
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domain = ciu3_info->domain[block];
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if (ciu3_info->intsn2hw[block])
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hw = ciu3_info->intsn2hw[block](domain, intsn);
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else
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hw = intsn;
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ret = handle_domain_irq(domain, hw, NULL);
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if (ret < 0) {
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union cvmx_ciu3_iscx_w1c isc_w1c;
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u64 isc_w1c_addr = ciu3_addr + CIU3_ISC_W1C(intsn);
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|
||||
isc_w1c.u64 = 0;
|
||||
isc_w1c.s.en = 1;
|
||||
cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);
|
||||
cvmx_read_csr(isc_w1c_addr);
|
||||
spurious_interrupt();
|
||||
}
|
||||
} else {
|
||||
spurious_interrupt();
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* 10 mbox per core starting from zero.
|
||||
* Base mbox is core * 10
|
||||
*/
|
||||
static unsigned int octeon_irq_ciu3_base_mbox_intsn(int core)
|
||||
{
|
||||
/* SW (mbox) are 0x04 in bits 12..19 */
|
||||
return 0x04000 + CIU3_MBOX_PER_CORE * core;
|
||||
}
|
||||
|
||||
static unsigned int octeon_irq_ciu3_mbox_intsn_for_core(int core, unsigned int mbox)
|
||||
{
|
||||
return octeon_irq_ciu3_base_mbox_intsn(core) + mbox;
|
||||
}
|
||||
|
||||
static unsigned int octeon_irq_ciu3_mbox_intsn_for_cpu(int cpu, unsigned int mbox)
|
||||
{
|
||||
int local_core = octeon_coreid_for_cpu(cpu) & 0x3f;
|
||||
|
||||
return octeon_irq_ciu3_mbox_intsn_for_core(local_core, mbox);
|
||||
}
|
||||
|
||||
static void octeon_irq_ciu3_mbox(void)
|
||||
{
|
||||
union cvmx_ciu3_destx_pp_int dest_pp_int;
|
||||
struct octeon_ciu3_info *ciu3_info;
|
||||
u64 ciu3_addr;
|
||||
int core = cvmx_get_local_core_num();
|
||||
|
||||
ciu3_info = __this_cpu_read(octeon_ciu3_info);
|
||||
ciu3_addr = ciu3_info->ciu3_addr;
|
||||
|
||||
dest_pp_int.u64 = cvmx_read_csr(ciu3_addr + CIU3_DEST_PP_INT(1 + 3 * core));
|
||||
|
||||
if (likely(dest_pp_int.s.intr)) {
|
||||
irq_hw_number_t intsn = dest_pp_int.s.intsn;
|
||||
int mbox = intsn - octeon_irq_ciu3_base_mbox_intsn(core);
|
||||
|
||||
if (likely(mbox >= 0 && mbox < CIU3_MBOX_PER_CORE)) {
|
||||
do_IRQ(mbox + OCTEON_IRQ_MBOX0);
|
||||
} else {
|
||||
union cvmx_ciu3_iscx_w1c isc_w1c;
|
||||
u64 isc_w1c_addr = ciu3_addr + CIU3_ISC_W1C(intsn);
|
||||
|
||||
isc_w1c.u64 = 0;
|
||||
isc_w1c.s.en = 1;
|
||||
cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);
|
||||
cvmx_read_csr(isc_w1c_addr);
|
||||
spurious_interrupt();
|
||||
}
|
||||
} else {
|
||||
spurious_interrupt();
|
||||
}
|
||||
}
|
||||
|
||||
void octeon_ciu3_mbox_send(int cpu, unsigned int mbox)
|
||||
{
|
||||
struct octeon_ciu3_info *ciu3_info;
|
||||
unsigned int intsn;
|
||||
union cvmx_ciu3_iscx_w1s isc_w1s;
|
||||
u64 isc_w1s_addr;
|
||||
|
||||
if (WARN_ON_ONCE(mbox >= CIU3_MBOX_PER_CORE))
|
||||
return;
|
||||
|
||||
intsn = octeon_irq_ciu3_mbox_intsn_for_cpu(cpu, mbox);
|
||||
ciu3_info = per_cpu(octeon_ciu3_info, cpu);
|
||||
isc_w1s_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1S(intsn);
|
||||
|
||||
isc_w1s.u64 = 0;
|
||||
isc_w1s.s.raw = 1;
|
||||
|
||||
cvmx_write_csr(isc_w1s_addr, isc_w1s.u64);
|
||||
cvmx_read_csr(isc_w1s_addr);
|
||||
}
|
||||
|
||||
static void octeon_irq_ciu3_mbox_set_enable(struct irq_data *data, int cpu, bool en)
|
||||
{
|
||||
struct octeon_ciu3_info *ciu3_info;
|
||||
unsigned int intsn;
|
||||
u64 isc_ctl_addr, isc_w1c_addr;
|
||||
union cvmx_ciu3_iscx_ctl isc_ctl;
|
||||
unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0;
|
||||
|
||||
intsn = octeon_irq_ciu3_mbox_intsn_for_cpu(cpu, mbox);
|
||||
ciu3_info = per_cpu(octeon_ciu3_info, cpu);
|
||||
isc_w1c_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1C(intsn);
|
||||
isc_ctl_addr = ciu3_info->ciu3_addr + CIU3_ISC_CTL(intsn);
|
||||
|
||||
isc_ctl.u64 = 0;
|
||||
isc_ctl.s.en = 1;
|
||||
|
||||
cvmx_write_csr(isc_w1c_addr, isc_ctl.u64);
|
||||
cvmx_write_csr(isc_ctl_addr, 0);
|
||||
if (en) {
|
||||
unsigned int idt = per_cpu(octeon_irq_ciu3_idt_ip3, cpu);
|
||||
|
||||
isc_ctl.u64 = 0;
|
||||
isc_ctl.s.en = 1;
|
||||
isc_ctl.s.idt = idt;
|
||||
cvmx_write_csr(isc_ctl_addr, isc_ctl.u64);
|
||||
}
|
||||
cvmx_read_csr(isc_ctl_addr);
|
||||
}
|
||||
|
||||
static void octeon_irq_ciu3_mbox_enable(struct irq_data *data)
|
||||
{
|
||||
int cpu;
|
||||
unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0;
|
||||
|
||||
WARN_ON(mbox >= CIU3_MBOX_PER_CORE);
|
||||
|
||||
for_each_online_cpu(cpu)
|
||||
octeon_irq_ciu3_mbox_set_enable(data, cpu, true);
|
||||
}
|
||||
|
||||
static void octeon_irq_ciu3_mbox_disable(struct irq_data *data)
|
||||
{
|
||||
int cpu;
|
||||
unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0;
|
||||
|
||||
WARN_ON(mbox >= CIU3_MBOX_PER_CORE);
|
||||
|
||||
for_each_online_cpu(cpu)
|
||||
octeon_irq_ciu3_mbox_set_enable(data, cpu, false);
|
||||
}
|
||||
|
||||
static void octeon_irq_ciu3_mbox_ack(struct irq_data *data)
|
||||
{
|
||||
struct octeon_ciu3_info *ciu3_info;
|
||||
unsigned int intsn;
|
||||
u64 isc_w1c_addr;
|
||||
union cvmx_ciu3_iscx_w1c isc_w1c;
|
||||
unsigned int mbox = data->irq - OCTEON_IRQ_MBOX0;
|
||||
|
||||
intsn = octeon_irq_ciu3_mbox_intsn_for_core(cvmx_get_local_core_num(), mbox);
|
||||
|
||||
isc_w1c.u64 = 0;
|
||||
isc_w1c.s.raw = 1;
|
||||
|
||||
ciu3_info = __this_cpu_read(octeon_ciu3_info);
|
||||
isc_w1c_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1C(intsn);
|
||||
cvmx_write_csr(isc_w1c_addr, isc_w1c.u64);
|
||||
cvmx_read_csr(isc_w1c_addr);
|
||||
}
|
||||
|
||||
static void octeon_irq_ciu3_mbox_cpu_online(struct irq_data *data)
|
||||
{
|
||||
octeon_irq_ciu3_mbox_set_enable(data, smp_processor_id(), true);
|
||||
}
|
||||
|
||||
static void octeon_irq_ciu3_mbox_cpu_offline(struct irq_data *data)
|
||||
{
|
||||
octeon_irq_ciu3_mbox_set_enable(data, smp_processor_id(), false);
|
||||
}
|
||||
|
||||
static int octeon_irq_ciu3_alloc_resources(struct octeon_ciu3_info *ciu3_info)
|
||||
{
|
||||
u64 b = ciu3_info->ciu3_addr;
|
||||
int idt_ip2, idt_ip3, idt_ip4;
|
||||
int unused_idt2;
|
||||
int core = cvmx_get_local_core_num();
|
||||
int i;
|
||||
|
||||
__this_cpu_write(octeon_ciu3_info, ciu3_info);
|
||||
|
||||
/*
|
||||
* 4 idt per core starting from 1 because zero is reserved.
|
||||
* Base idt per core is 4 * core + 1
|
||||
*/
|
||||
idt_ip2 = core * 4 + 1;
|
||||
idt_ip3 = core * 4 + 2;
|
||||
idt_ip4 = core * 4 + 3;
|
||||
unused_idt2 = core * 4 + 4;
|
||||
__this_cpu_write(octeon_irq_ciu3_idt_ip2, idt_ip2);
|
||||
__this_cpu_write(octeon_irq_ciu3_idt_ip3, idt_ip3);
|
||||
|
||||
/* ip2 interrupts for this CPU */
|
||||
cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip2), 0);
|
||||
cvmx_write_csr(b + CIU3_IDT_PP(idt_ip2, 0), 1ull << core);
|
||||
cvmx_write_csr(b + CIU3_IDT_IO(idt_ip2), 0);
|
||||
|
||||
/* ip3 interrupts for this CPU */
|
||||
cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip3), 1);
|
||||
cvmx_write_csr(b + CIU3_IDT_PP(idt_ip3, 0), 1ull << core);
|
||||
cvmx_write_csr(b + CIU3_IDT_IO(idt_ip3), 0);
|
||||
|
||||
/* ip4 interrupts for this CPU */
|
||||
cvmx_write_csr(b + CIU3_IDT_CTL(idt_ip4), 2);
|
||||
cvmx_write_csr(b + CIU3_IDT_PP(idt_ip4, 0), 0);
|
||||
cvmx_write_csr(b + CIU3_IDT_IO(idt_ip4), 0);
|
||||
|
||||
cvmx_write_csr(b + CIU3_IDT_CTL(unused_idt2), 0);
|
||||
cvmx_write_csr(b + CIU3_IDT_PP(unused_idt2, 0), 0);
|
||||
cvmx_write_csr(b + CIU3_IDT_IO(unused_idt2), 0);
|
||||
|
||||
for (i = 0; i < CIU3_MBOX_PER_CORE; i++) {
|
||||
unsigned int intsn = octeon_irq_ciu3_mbox_intsn_for_core(core, i);
|
||||
|
||||
cvmx_write_csr(b + CIU3_ISC_W1C(intsn), 2);
|
||||
cvmx_write_csr(b + CIU3_ISC_CTL(intsn), 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void octeon_irq_setup_secondary_ciu3(void)
|
||||
{
|
||||
struct octeon_ciu3_info *ciu3_info;
|
||||
|
||||
ciu3_info = octeon_ciu3_info_per_node[cvmx_get_node_num()];
|
||||
octeon_irq_ciu3_alloc_resources(ciu3_info);
|
||||
irq_cpu_online();
|
||||
|
||||
/* Enable the CIU lines */
|
||||
set_c0_status(STATUSF_IP3 | STATUSF_IP2);
|
||||
if (octeon_irq_use_ip4)
|
||||
set_c0_status(STATUSF_IP4);
|
||||
else
|
||||
clear_c0_status(STATUSF_IP4);
|
||||
}
|
||||
|
||||
static struct irq_chip octeon_irq_chip_ciu3_mbox = {
|
||||
.name = "CIU3-M",
|
||||
.irq_enable = octeon_irq_ciu3_mbox_enable,
|
||||
.irq_disable = octeon_irq_ciu3_mbox_disable,
|
||||
.irq_ack = octeon_irq_ciu3_mbox_ack,
|
||||
|
||||
.irq_cpu_online = octeon_irq_ciu3_mbox_cpu_online,
|
||||
.irq_cpu_offline = octeon_irq_ciu3_mbox_cpu_offline,
|
||||
.flags = IRQCHIP_ONOFFLINE_ENABLED,
|
||||
};
|
||||
|
||||
static int __init octeon_irq_init_ciu3(struct device_node *ciu_node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
int i;
|
||||
int node;
|
||||
struct irq_domain *domain;
|
||||
struct octeon_ciu3_info *ciu3_info;
|
||||
const __be32 *zero_addr;
|
||||
u64 base_addr;
|
||||
union cvmx_ciu3_const consts;
|
||||
|
||||
node = 0; /* of_node_to_nid(ciu_node); */
|
||||
ciu3_info = kzalloc_node(sizeof(*ciu3_info), GFP_KERNEL, node);
|
||||
|
||||
if (!ciu3_info)
|
||||
return -ENOMEM;
|
||||
|
||||
zero_addr = of_get_address(ciu_node, 0, NULL, NULL);
|
||||
if (WARN_ON(!zero_addr))
|
||||
return -EINVAL;
|
||||
|
||||
base_addr = of_translate_address(ciu_node, zero_addr);
|
||||
base_addr = (u64)phys_to_virt(base_addr);
|
||||
|
||||
ciu3_info->ciu3_addr = base_addr;
|
||||
ciu3_info->node = node;
|
||||
|
||||
consts.u64 = cvmx_read_csr(base_addr + CIU3_CONST);
|
||||
|
||||
octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu3;
|
||||
|
||||
octeon_irq_ip2 = octeon_irq_ciu3_ip2;
|
||||
octeon_irq_ip3 = octeon_irq_ciu3_mbox;
|
||||
octeon_irq_ip4 = octeon_irq_ip4_mask;
|
||||
|
||||
if (node == cvmx_get_node_num()) {
|
||||
/* Mips internal */
|
||||
octeon_irq_init_core();
|
||||
|
||||
/* Only do per CPU things if it is the CIU of the boot node. */
|
||||
i = irq_alloc_descs_from(OCTEON_IRQ_MBOX0, 8, node);
|
||||
WARN_ON(i < 0);
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
irq_set_chip_and_handler(i + OCTEON_IRQ_MBOX0,
|
||||
&octeon_irq_chip_ciu3_mbox, handle_percpu_irq);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize all domains to use the default domain. Specific major
|
||||
* blocks will overwrite the default domain as needed.
|
||||
*/
|
||||
domain = irq_domain_add_tree(ciu_node, &octeon_dflt_domain_ciu3_ops,
|
||||
ciu3_info);
|
||||
for (i = 0; i < MAX_CIU3_DOMAINS; i++)
|
||||
ciu3_info->domain[i] = domain;
|
||||
|
||||
octeon_ciu3_info_per_node[node] = ciu3_info;
|
||||
|
||||
if (node == cvmx_get_node_num()) {
|
||||
/* Only do per CPU things if it is the CIU of the boot node. */
|
||||
octeon_irq_ciu3_alloc_resources(ciu3_info);
|
||||
if (node == 0)
|
||||
irq_set_default_host(domain);
|
||||
|
||||
octeon_irq_use_ip4 = false;
|
||||
/* Enable the CIU lines */
|
||||
set_c0_status(STATUSF_IP2 | STATUSF_IP3);
|
||||
clear_c0_status(STATUSF_IP4);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id ciu_types[] __initdata = {
|
||||
{.compatible = "cavium,octeon-3860-ciu", .data = octeon_irq_init_ciu},
|
||||
{.compatible = "cavium,octeon-3860-gpio", .data = octeon_irq_init_gpio},
|
||||
{.compatible = "cavium,octeon-6880-ciu2", .data = octeon_irq_init_ciu2},
|
||||
{.compatible = "cavium,octeon-7890-ciu3", .data = octeon_irq_init_ciu3},
|
||||
{.compatible = "cavium,octeon-7130-cib", .data = octeon_irq_init_cib},
|
||||
{}
|
||||
};
|
||||
|
||||
@ -299,6 +299,25 @@ static inline void octeon_npi_write32(uint64_t address, uint32_t val)
|
||||
cvmx_read64_uint32(address ^ 4);
|
||||
}
|
||||
|
||||
struct irq_domain;
|
||||
struct device_node;
|
||||
struct irq_data;
|
||||
struct irq_chip;
|
||||
void octeon_ciu3_mbox_send(int cpu, unsigned int mbox);
|
||||
int octeon_irq_ciu3_xlat(struct irq_domain *d,
|
||||
struct device_node *node,
|
||||
const u32 *intspec,
|
||||
unsigned int intsize,
|
||||
unsigned long *out_hwirq,
|
||||
unsigned int *out_type);
|
||||
void octeon_irq_ciu3_enable(struct irq_data *data);
|
||||
void octeon_irq_ciu3_disable(struct irq_data *data);
|
||||
void octeon_irq_ciu3_ack(struct irq_data *data);
|
||||
void octeon_irq_ciu3_mask(struct irq_data *data);
|
||||
void octeon_irq_ciu3_mask_ack(struct irq_data *data);
|
||||
int octeon_irq_ciu3_mapx(struct irq_domain *d, unsigned int virq,
|
||||
irq_hw_number_t hw, struct irq_chip *chip);
|
||||
|
||||
/* Octeon multiplier save/restore routines from octeon_switch.S */
|
||||
void octeon_mult_save(void);
|
||||
void octeon_mult_restore(void);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user