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[MTD] Add initial support for OneNAND flash chips
OneNAND is a new flash technology from Samsung with integrated SRAM buffers and logic interface. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Kyungmin Park
Thomas Gleixner
parent
4ce1f56218
commit
cd5f6346bc
@ -1,4 +1,4 @@
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# $Id: Kconfig,v 1.9 2005/06/16 08:49:29 sean Exp $
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# $Id: Kconfig,v 1.10 2005/07/11 10:39:27 gleixner Exp $
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menu "Memory Technology Devices (MTD)"
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@ -259,9 +259,9 @@ config RFD_FTL
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---help---
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This provides support for the flash translation layer known
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as the Resident Flash Disk (RFD), as used by the Embedded BIOS
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of General Software.
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See http://www.gensw.com/pages/prod/bios/rfd.htm for further
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information.
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of General Software. There is a blurb at:
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http://www.gensw.com/pages/prod/bios/rfd.htm
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source "drivers/mtd/chips/Kconfig"
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@ -271,5 +271,7 @@ source "drivers/mtd/devices/Kconfig"
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source "drivers/mtd/nand/Kconfig"
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source "drivers/mtd/onenand/Kconfig"
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endmenu
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@ -1,7 +1,7 @@
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#
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# Makefile for the memory technology device drivers.
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#
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# $Id: Makefile.common,v 1.6 2005/06/16 08:49:29 sean Exp $
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# $Id: Makefile.common,v 1.7 2005/07/11 10:39:27 gleixner Exp $
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# Core functionality.
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mtd-y := mtdcore.o
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@ -25,4 +25,4 @@ obj-$(CONFIG_RFD_FTL) += rfd_ftl.o mtd_blkdevs.o
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nftl-objs := nftlcore.o nftlmount.o
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inftl-objs := inftlcore.o inftlmount.o
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obj-y += chips/ maps/ devices/ nand/
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obj-y += chips/ maps/ devices/ nand/ onenand/
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32
drivers/mtd/onenand/Kconfig
Normal file
32
drivers/mtd/onenand/Kconfig
Normal file
@ -0,0 +1,32 @@
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#
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# linux/drivers/mtd/onenand/Kconfig
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#
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menu "OneNAND Flash Device Drivers (EXPERIMENTAL)"
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depends on MTD != n && EXPERIMENTAL
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config MTD_ONENAND
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tristate "OneNAND Device Support"
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depends on MTD
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help
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This enables support for accessing all type of OneNAND flash
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devices. For further information see
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<http://www.samsung.com/Products/Semiconductor/Flash/OneNAND_TM/index.htm>.
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config MTD_ONENAND_VERIFY_WRITE
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bool "Verify OneNAND page writes"
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depends on MTD_ONENAND
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help
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This adds an extra check when data is written to the flash. The
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OneNAND flash device internally checks only bits transitioning
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from 1 to 0. There is a rare possibility that even though the
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device thinks the write was successful, a bit could have been
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flipped accidentaly due to device wear or something else.
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config MTD_ONENAND_OMAP
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tristate "OneNAND Flash device on OMAP board"
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depends on ARCH_OMAP && MTD_ONENAND
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help
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Support for OneNAND flash on TI OMAP board.
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endmenu
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9
drivers/mtd/onenand/Makefile
Normal file
9
drivers/mtd/onenand/Makefile
Normal file
@ -0,0 +1,9 @@
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#
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# Makefile for the OneNAND MTD
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#
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# Core functionality.
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obj-$(CONFIG_MTD_ONENAND) += onenand_base.o
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# Board specific.
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obj-$(CONFIG_MTD_ONENAND_OMAP) += omap-onenand.o
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178
drivers/mtd/onenand/omap-onenand.c
Normal file
178
drivers/mtd/onenand/omap-onenand.c
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@ -0,0 +1,178 @@
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/*
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* linux/drivers/mtd/onenand/omap-onenand.c
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*
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* Copyright (c) 2005 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* Derived from linux/drivers/mtd/nand/omap-nand-flash.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Overview:
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* This is a device driver for the OneNAND flash device for TI OMAP boards.
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*/
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/onenand.h>
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#include <linux/mtd/partitions.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/tc.h>
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#include <asm/sizes.h>
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#define OMAP_ONENAND_FLASH_START1 OMAP_CS2A_PHYS
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#define OMAP_ONENAND_FLASH_START2 OMAP_CS0_PHYS
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/*
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* MTD structure for OMAP board
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*/
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static struct mtd_info *omap_onenand_mtd = NULL;
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/*
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* Define partitions for flash devices
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*/
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#ifdef CONFIG_MTD_PARTITIONS
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static struct mtd_partition static_partition[] = {
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{
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.name = "X-Loader + U-Boot",
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.offset = 0,
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.size = SZ_128K,
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.mask_flags = MTD_WRITEABLE /* force read-only */
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},
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{
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.name = "U-Boot Environment",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_128K,
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.mask_flags = MTD_WRITEABLE /* force read-only */
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},
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{
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.name = "kernel",
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.offset = MTDPART_OFS_APPEND,
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.size = 2 * SZ_1M
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},
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{
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.name = "filesystem0",
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.offset = MTDPART_OFS_APPEND,
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.size = SZ_16M,
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},
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{
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.name = "filesystem1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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const char *part_probes[] = { "cmdlinepart", NULL, };
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#endif
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/* Scan to find existance of the device at base.
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This also allocates oob and data internal buffers */
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static char onenand_name[] = "onenand";
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/*
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* Main initialization routine
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*/
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static int __init omap_onenand_init (void)
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{
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struct onenand_chip *this;
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struct mtd_partition *dynamic_partition = 0;
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int err = 0;
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/* Allocate memory for MTD device structure and private data */
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omap_onenand_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct onenand_chip),
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GFP_KERNEL);
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if (!omap_onenand_mtd) {
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printk (KERN_WARNING "Unable to allocate OneNAND MTD device structure.\n");
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err = -ENOMEM;
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goto out;
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}
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/* Get pointer to private data */
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this = (struct onenand_chip *) (&omap_onenand_mtd[1]);
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/* Initialize structures */
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memset((char *) omap_onenand_mtd, 0, sizeof(struct mtd_info) + sizeof(struct onenand_chip));
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/* Link the private data with the MTD structure */
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omap_onenand_mtd->priv = this;
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/* try the first address */
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this->base = ioremap(OMAP_ONENAND_FLASH_START1, SZ_128K);
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omap_onenand_mtd->name = onenand_name;
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if (onenand_scan(omap_onenand_mtd, 1)){
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/* try the second address */
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iounmap(this->base);
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this->base = ioremap(OMAP_ONENAND_FLASH_START2, SZ_128K);
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if (onenand_scan(omap_onenand_mtd, 1)) {
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iounmap(this->base);
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err = -ENXIO;
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goto out_mtd;
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}
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}
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/* Register the partitions */
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switch (omap_onenand_mtd->size) {
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case SZ_128M:
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case SZ_64M:
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case SZ_32M:
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#ifdef CONFIG_MTD_PARTITIONS
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err = parse_mtd_partitions(omap_onenand_mtd, part_probes,
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&dynamic_partition, 0);
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if (err > 0)
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err = add_mtd_partitions(omap_onenand_mtd,
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dynamic_partition, err);
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else if (1)
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err = add_mtd_partitions(omap_onenand_mtd,
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static_partition,
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ARRAY_SIZE(static_partition));
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else
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#endif
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err = add_mtd_device(omap_onenand_mtd);
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if (err)
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goto out_buf;
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break;
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default:
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printk(KERN_WARNING "Unsupported OneNAND device\n");
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err = -ENXIO;
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goto out_buf;
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}
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return 0;
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out_buf:
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onenand_release(omap_onenand_mtd);
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iounmap(this->base);
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out_mtd:
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kfree(omap_onenand_mtd);
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out:
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return err;
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}
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/*
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* Clean up routine
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*/
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static void __exit omap_onenand_cleanup (void)
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{
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struct onenand_chip *this = omap_onenand_mtd->priv;
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/* onenand_release frees MTD partitions, MTD structure
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and onenand internal buffers */
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onenand_release(omap_onenand_mtd);
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iounmap(this->base);
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kfree(omap_onenand_mtd);
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}
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module_init(omap_onenand_init);
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module_exit(omap_onenand_cleanup);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
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MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP boards");
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1462
drivers/mtd/onenand/onenand_base.c
Normal file
1462
drivers/mtd/onenand/onenand_base.c
Normal file
File diff suppressed because it is too large
Load Diff
134
include/linux/mtd/onenand.h
Normal file
134
include/linux/mtd/onenand.h
Normal file
@ -0,0 +1,134 @@
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/*
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* linux/include/linux/mtd/onenand.h
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*
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* Copyright (C) 2005 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __LINUX_MTD_ONENAND_H
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#define __LINUX_MTD_ONENAND_H
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#include <linux/spinlock.h>
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#include <linux/mtd/onenand_regs.h>
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#define MAX_BUFFERRAM 2
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/* Scan and identify a OneNAND device */
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extern int onenand_scan(struct mtd_info *mtd, int max_chips);
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/* Free resources held by the OneNAND device */
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extern void onenand_release(struct mtd_info *mtd);
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/**
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* onenand_state_t - chip states
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* Enumeration for OneNAND flash chip state
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*/
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typedef enum {
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FL_READY,
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FL_READING,
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FL_WRITING,
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FL_ERASING,
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FL_SYNCING,
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FL_UNLOCKING,
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FL_LOCKING,
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} onenand_state_t;
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/**
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* struct onenand_bufferram - OneNAND BufferRAM Data
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* @param block block address in BufferRAM
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* @param page page address in BufferRAM
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* @param valid valid flag
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*/
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struct onenand_bufferram {
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int block;
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int page;
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int valid;
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};
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/**
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* struct onenand_chip - OneNAND Private Flash Chip Data
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* @param base [BOARDSPECIFIC] address to access OneNAND
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* @param chipsize [INTERN] the size of one chip for multichip arrays
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* @param device_id [INTERN] device ID
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* @param verstion_id [INTERN] version ID
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* @param options [BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
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* @param erase_shift [INTERN] number of address bits in a block
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* @param page_shift [INTERN] number of address bits in a page
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* @param ppb_shift [INTERN] number of address bits in a pages per block
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* @param page_mask [INTERN] a page per block mask
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* @param bufferam_index [INTERN] BufferRAM index
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* @param bufferam [INTERN] BufferRAM info
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* @param readw [REPLACEABLE] hardware specific function for read short
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* @param writew [REPLACEABLE] hardware specific function for write short
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* @param command [REPLACEABLE] hardware specific function for writing commands to the chip
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* @param wait [REPLACEABLE] hardware specific function for wait on ready
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* @param read_bufferram [REPLACEABLE] hardware specific function for BufferRAM Area
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* @param write_bufferram [REPLACEABLE] hardware specific function for BufferRAM Area
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* @param chip_lock [INTERN] spinlock used to protect access to this structure and the chip
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* @param wq [INTERN] wait queue to sleep on if a OneNAND operation is in progress
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* @param state [INTERN] the current state of the OneNAND device
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* @param autooob [REPLACEABLE] the default (auto)placement scheme
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* @param priv [OPTIONAL] pointer to private chip date
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*/
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struct onenand_chip {
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void __iomem *base;
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unsigned int chipsize;
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unsigned int device_id;
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unsigned int options;
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unsigned int erase_shift;
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unsigned int page_shift;
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unsigned int ppb_shift; /* Pages per block shift */
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unsigned int page_mask;
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unsigned int bufferram_index;
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struct onenand_bufferram bufferram[MAX_BUFFERRAM];
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int (*command)(struct mtd_info *mtd, int cmd, loff_t address, size_t len);
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int (*wait)(struct mtd_info *mtd, int state);
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int (*read_bufferram)(struct mtd_info *mtd, int area,
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unsigned char *buffer, int offset, size_t count);
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int (*write_bufferram)(struct mtd_info *mtd, int area,
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const unsigned char *buffer, int offset, size_t count);
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unsigned short (*read_word)(void __iomem *addr);
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void (*write_word)(unsigned short value, void __iomem *addr);
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spinlock_t chip_lock;
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wait_queue_head_t wq;
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onenand_state_t state;
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struct nand_oobinfo *autooob;
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void *priv;
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};
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#define ONENAND_CURRENT_BUFFERRAM(this) (this->bufferram_index)
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#define ONENAND_NEXT_BUFFERRAM(this) (this->bufferram_index ^ 1)
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#define ONENAND_SET_NEXT_BUFFERRAM(this) (this->bufferram_index ^= 1)
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/*
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* Options bits
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*/
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#define ONENAND_CONT_LOCK (0x0001)
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/*
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* OneNAND Flash Manufacturer ID Codes
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*/
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#define ONENAND_MFR_SAMSUNG 0xec
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#define ONENAND_MFR_UNKNOWN 0x00
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/**
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* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
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* @param name: Manufacturer name
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* @param id: manufacturer ID code of device.
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*/
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struct onenand_manufacturers {
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int id;
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char *name;
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};
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#endif /* __LINUX_MTD_ONENAND_H */
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167
include/linux/mtd/onenand_regs.h
Normal file
167
include/linux/mtd/onenand_regs.h
Normal file
@ -0,0 +1,167 @@
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/*
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* linux/include/linux/mtd/onenand_regs.h
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*
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* OneNAND Register header file
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*
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* Copyright (C) 2005 Samsung Electronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ONENAND_REG_H
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#define __ONENAND_REG_H
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/* Memory Address Map Translation (Word order) */
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#define ONENAND_MEMORY_MAP(x) ((x) << 1)
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/*
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* External BufferRAM area
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*/
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#define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
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#define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
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#define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
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/*
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* OneNAND Registers
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*/
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#define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
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#define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
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#define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
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#define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
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#define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
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#define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
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#define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
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#define ONENAND_REG_START_ADDRESS1 ONENAND_MEMORY_MAP(0xF100)
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#define ONENAND_REG_START_ADDRESS2 ONENAND_MEMORY_MAP(0xF101)
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#define ONENAND_REG_START_ADDRESS3 ONENAND_MEMORY_MAP(0xF102)
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#define ONENAND_REG_START_ADDRESS4 ONENAND_MEMORY_MAP(0xF103)
|
||||
#define ONENAND_REG_START_ADDRESS5 ONENAND_MEMORY_MAP(0xF104)
|
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#define ONENAND_REG_START_ADDRESS6 ONENAND_MEMORY_MAP(0xF105)
|
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#define ONENAND_REG_START_ADDRESS7 ONENAND_MEMORY_MAP(0xF106)
|
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#define ONENAND_REG_START_ADDRESS8 ONENAND_MEMORY_MAP(0xF107)
|
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|
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#define ONENAND_REG_START_BUFFER ONENAND_MEMORY_MAP(0xF200)
|
||||
#define ONENAND_REG_COMMAND ONENAND_MEMORY_MAP(0xF220)
|
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#define ONENAND_REG_SYS_CFG1 ONENAND_MEMORY_MAP(0xF221)
|
||||
#define ONENAND_REG_SYS_CFG2 ONENAND_MEMORY_MAP(0xF222)
|
||||
#define ONENAND_REG_CTRL_STATUS ONENAND_MEMORY_MAP(0xF240)
|
||||
#define ONENAND_REG_INTERRUPT ONENAND_MEMORY_MAP(0xF241)
|
||||
#define ONENAND_REG_START_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24C)
|
||||
#define ONENAND_REG_END_BLOCK_ADDRESS ONENAND_MEMORY_MAP(0xF24D)
|
||||
#define ONENAND_REG_WP_STATUS ONENAND_MEMORY_MAP(0xF24E)
|
||||
|
||||
#define ONENAND_REG_ECC_STATUS ONENAND_MEMORY_MAP(0xFF00)
|
||||
#define ONENAND_REG_ECC_M0 ONENAND_MEMORY_MAP(0xFF01)
|
||||
#define ONENAND_REG_ECC_S0 ONENAND_MEMORY_MAP(0xFF02)
|
||||
#define ONENAND_REG_ECC_M1 ONENAND_MEMORY_MAP(0xFF03)
|
||||
#define ONENAND_REG_ECC_S1 ONENAND_MEMORY_MAP(0xFF04)
|
||||
#define ONENAND_REG_ECC_M2 ONENAND_MEMORY_MAP(0xFF05)
|
||||
#define ONENAND_REG_ECC_S2 ONENAND_MEMORY_MAP(0xFF06)
|
||||
#define ONENAND_REG_ECC_M3 ONENAND_MEMORY_MAP(0xFF07)
|
||||
#define ONENAND_REG_ECC_S3 ONENAND_MEMORY_MAP(0xFF08)
|
||||
|
||||
/*
|
||||
* Device ID Register F001h (R)
|
||||
*/
|
||||
#define ONENAND_DEVICE_DENSITY_SHIFT (4)
|
||||
#define ONENAND_DEVICE_IS_DDP (1 << 3)
|
||||
#define ONENAND_DEVICE_IS_DEMUX (1 << 2)
|
||||
#define ONENAND_DEVICE_VCC_MASK (0x3)
|
||||
|
||||
#define ONENAND_DEVICE_DENSITY_512Mb (0x002)
|
||||
|
||||
/*
|
||||
* Version ID Register F002h (R)
|
||||
*/
|
||||
#define ONENAND_VERSION_PROCESS_SHIFT (8)
|
||||
|
||||
/*
|
||||
* Start Address 1 F100h (R/W)
|
||||
*/
|
||||
#define ONENAND_DDP_SHIFT (15)
|
||||
|
||||
/*
|
||||
* Start Address 8 F107h (R/W)
|
||||
*/
|
||||
#define ONENAND_FPA_MASK (0x3f)
|
||||
#define ONENAND_FPA_SHIFT (2)
|
||||
#define ONENAND_FSA_MASK (0x03)
|
||||
|
||||
/*
|
||||
* Start Buffer Register F200h (R/W)
|
||||
*/
|
||||
#define ONENAND_BSA_MASK (0x03)
|
||||
#define ONENAND_BSA_SHIFT (8)
|
||||
#define ONENAND_BSA_BOOTRAM (0 << 2)
|
||||
#define ONENAND_BSA_DATARAM0 (2 << 2)
|
||||
#define ONENAND_BSA_DATARAM1 (3 << 2)
|
||||
#define ONENAND_BSC_MASK (0x03)
|
||||
|
||||
/*
|
||||
* Command Register F220h (R/W)
|
||||
*/
|
||||
#define ONENAND_CMD_READ (0x00)
|
||||
#define ONENAND_CMD_READOOB (0x13)
|
||||
#define ONENAND_CMD_PROG (0x80)
|
||||
#define ONENAND_CMD_PROGOOB (0x1A)
|
||||
#define ONENAND_CMD_UNLOCK (0x23)
|
||||
#define ONENAND_CMD_LOCK (0x2A)
|
||||
#define ONENAND_CMD_LOCK_TIGHT (0x2C)
|
||||
#define ONENAND_CMD_ERASE (0x94)
|
||||
#define ONENAND_CMD_RESET (0xF0)
|
||||
#define ONENAND_CMD_READID (0x90)
|
||||
|
||||
/* NOTE: Those are not *REAL* commands */
|
||||
#define ONENAND_CMD_BUFFERRAM (0x1978)
|
||||
|
||||
/*
|
||||
* System Configuration 1 Register F221h (R, R/W)
|
||||
*/
|
||||
#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15)
|
||||
#define ONENAND_SYS_CFG1_BRL (1 << 12)
|
||||
#define ONENAND_SYS_CFG1_BL (1 << 9)
|
||||
#define ONENAND_SYS_CFG1_NO_ECC (1 << 8)
|
||||
#define ONENAND_SYS_CFG1_RDY (1 << 7)
|
||||
#define ONENAND_SYS_CFG1_INT (1 << 6)
|
||||
#define ONENAND_SYS_CFG1_IOBE (1 << 5)
|
||||
#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4)
|
||||
|
||||
/*
|
||||
* Controller Status Register F240h (R)
|
||||
*/
|
||||
#define ONENAND_CTRL_ONGO (1 << 15)
|
||||
#define ONENAND_CTRL_LOCK (1 << 14)
|
||||
#define ONENAND_CTRL_LOAD (1 << 13)
|
||||
#define ONENAND_CTRL_PROGRAM (1 << 12)
|
||||
#define ONENAND_CTRL_ERASE (1 << 11)
|
||||
#define ONENAND_CTRL_ERROR (1 << 10)
|
||||
#define ONENAND_CTRL_RSTB (1 << 7)
|
||||
|
||||
/*
|
||||
* Interrupt Status Register F241h (R)
|
||||
*/
|
||||
#define ONENAND_INT_MASTER (1 << 15)
|
||||
#define ONENAND_INT_READ (1 << 7)
|
||||
#define ONENAND_INT_WRITE (1 << 6)
|
||||
#define ONENAND_INT_ERASE (1 << 5)
|
||||
#define ONENAND_INT_RESET (1 << 4)
|
||||
#define ONENAND_INT_CLEAR (0 << 0)
|
||||
|
||||
/*
|
||||
* NAND Flash Write Protection Status Register F24Eh (R)
|
||||
*/
|
||||
#define ONENAND_WP_US (1 << 2)
|
||||
#define ONENAND_WP_LS (1 << 1)
|
||||
#define ONENAND_WP_LTS (1 << 0)
|
||||
|
||||
/*
|
||||
* ECC Status Reigser FF00h (R)
|
||||
*/
|
||||
#define ONENAND_ECC_1BIT (1 << 0)
|
||||
#define ONENAND_ECC_2BIT (1 << 1)
|
||||
#define ONENAND_ECC_2BIT_ALL (0xAAAA)
|
||||
|
||||
#endif /* __ONENAND_REG_H */
|
||||
Loading…
Reference in New Issue
Block a user