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ALSA: hda/cs8409: Use enums for register names and coefficients
Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com> Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210811185654.6837-4-vitalyr@opensource.cirrus.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Stefan Binding
Takashi Iwai
parent
9e7647b507
commit
ccff0064a7
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@ -91,20 +91,20 @@ const struct hda_fixup cs8409_fixups[] = {
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};
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const struct hda_verb cs8409_cs42l42_init_verbs[] = {
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{ 0x01, AC_VERB_SET_GPIO_WAKE_MASK, 0x0018 }, /* WAKE from GPIO 3,4 */
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{ 0x47, AC_VERB_SET_PROC_STATE, 0x0001 }, /* Enable VPW processing */
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{ 0x47, AC_VERB_SET_COEF_INDEX, 0x0002 }, /* Configure GPIO 6,7 */
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{ 0x47, AC_VERB_SET_PROC_COEF, 0x0080 }, /* I2C mode */
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{ 0x47, AC_VERB_SET_COEF_INDEX, 0x005b }, /* Set I2C bus speed */
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{ 0x47, AC_VERB_SET_PROC_COEF, 0x0200 }, /* 100kHz I2C_STO = 2 */
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{ CS8409_PIN_AFG, AC_VERB_SET_GPIO_WAKE_MASK, 0x0018 }, /* WAKE from GPIO 3,4 */
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{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 }, /* Enable VPW processing */
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{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x0002 }, /* Configure GPIO 6,7 */
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{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF, 0x0080 }, /* I2C mode */
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{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x005b }, /* Set I2C bus speed */
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{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF, 0x0200 }, /* 100kHz I2C_STO = 2 */
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{} /* terminator */
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};
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const struct hda_pintbl cs8409_cs42l42_pincfgs[] = {
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{ 0x24, 0x042120f0 }, /* ASP-1-TX */
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{ 0x34, 0x04a12050 }, /* ASP-1-RX */
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{ 0x2c, 0x901000f0 }, /* ASP-2-TX */
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{ 0x44, 0x90a00090 }, /* DMIC-1 */
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{ CS8409_PIN_ASP1_TRANSMITTER_A, 0x042120f0 }, /* ASP-1-TX */
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{ CS8409_PIN_ASP1_RECEIVER_A, 0x04a12050 }, /* ASP-1-RX */
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{ CS8409_PIN_ASP2_TRANSMITTER_A, 0x901000f0 }, /* ASP-2-TX */
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{ CS8409_PIN_DMIC1_IN, 0x90a00090 }, /* DMIC-1 */
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{} /* terminator */
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};
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@ -164,57 +164,105 @@ const struct cs8409_i2c_param cs42l42_init_reg_seq[] = {
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/* Vendor specific hw configuration for CS8409 */
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const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[] = {
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{ 0x47, 0x00, 0xb008 }, /* +PLL1/2_EN, +I2C_EN */
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{ 0x47, 0x01, 0x0002 }, /* ASP1/2_EN=0, ASP1_STP=1 */
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{ 0x47, 0x02, 0x0a80 }, /* ASP1/2_BUS_IDLE=10, +GPIO_I2C */
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{ 0x47, 0x19, 0x0800 }, /* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
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{ 0x47, 0x1a, 0x0820 }, /* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */
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{ 0x47, 0x29, 0x0800 }, /* ASP2.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
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{ 0x47, 0x2a, 0x2800 }, /* ASP2.A: TX.RAP=1, TX.RSZ=24 bits, TX.RCS=0 */
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{ 0x47, 0x39, 0x0800 }, /* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */
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{ 0x47, 0x3a, 0x0800 }, /* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */
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{ 0x47, 0x03, 0x8000 }, /* ASP1: LCHI = 00h */
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{ 0x47, 0x04, 0x28ff }, /* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */
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{ 0x47, 0x05, 0x0062 }, /* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */
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{ 0x47, 0x06, 0x801f }, /* ASP2: LCHI=1Fh */
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{ 0x47, 0x07, 0x283f }, /* ASP2: MC/SC_SRCSEL=PLL1, LCPR=3Fh */
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{ 0x47, 0x08, 0x805c }, /* ASP2: 5050=1, MCEN=0, FSD=010, SCPOL_IN/OUT=1, SCDIV=1:16 */
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{ 0x47, 0x09, 0x0023 }, /* DMIC1_MO=10b, DMIC1/2_SR=1 */
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{ 0x47, 0x0a, 0x0000 }, /* ASP1/2_BEEP=0 */
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{ 0x47, 0x01, 0x0062 }, /* ASP1/2_EN=1, ASP1_STP=1 */
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{ 0x47, 0x00, 0x9008 }, /* -PLL2_EN */
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{ 0x47, 0x68, 0x0000 }, /* TX2.A: pre-scale att.=0 dB */
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{ 0x47, 0x82, 0xfc03 }, /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=1 */
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{ 0x47, 0xc0, 0x9999 }, /* test mode on */
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{ 0x47, 0xc5, 0x0000 }, /* GPIO hysteresis = 30 us */
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{ 0x47, 0xc0, 0x0000 }, /* test mode off */
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/* +PLL1/2_EN, +I2C_EN */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0xb008 },
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/* ASP1/2_EN=0, ASP1_STP=1 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0002 },
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/* ASP1/2_BUS_IDLE=10, +GPIO_I2C */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG3, 0x0a80 },
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/* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
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{ CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL1, 0x0800 },
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/* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */
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{ CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL2, 0x0820 },
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/* ASP2.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
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{ CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL1, 0x0800 },
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/* ASP2.A: TX.RAP=1, TX.RSZ=24 bits, TX.RCS=0 */
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{ CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL2, 0x2800 },
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/* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */
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{ CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL1, 0x0800 },
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/* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */
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{ CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL2, 0x0800 },
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/* ASP1: LCHI = 00h */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL1, 0x8000 },
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/* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL2, 0x28ff },
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/* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL3, 0x0062 },
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/* ASP2: LCHI=1Fh */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL1, 0x801f },
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/* ASP2: MC/SC_SRCSEL=PLL1, LCPR=3Fh */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL2, 0x283f },
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/* ASP2: 5050=1, MCEN=0, FSD=010, SCPOL_IN/OUT=1, SCDIV=1:16 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL3, 0x805c },
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/* DMIC1_MO=10b, DMIC1/2_SR=1 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_DMIC_CFG, 0x0023 },
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/* ASP1/2_BEEP=0 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_BEEP_CFG, 0x0000 },
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/* ASP1/2_EN=1, ASP1_STP=1 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0062 },
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/* -PLL2_EN */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0x9008 },
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/* TX2.A: pre-scale att.=0 dB */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PRE_SCALE_ATTN2, 0x0000 },
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/* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=1 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc03 },
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/* test mode on */
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{ CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x9999 },
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/* GPIO hysteresis = 30 us */
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{ CS8409_PIN_VENDOR_WIDGET, 0xc5, 0x0000 },
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/* test mode off */
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{ CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x0000 },
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{} /* Terminator */
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};
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const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[] = {
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{ 0x47, 0x65, 0x4000 }, /* EQ_SEL=1, EQ1/2_EN=0 */
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{ 0x47, 0x64, 0x4000 }, /* +EQ_ACC */
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{ 0x47, 0x65, 0x4010 }, /* +EQ2_EN */
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{ 0x47, 0x63, 0x0647 }, /* EQ_DATA_HI=0x0647 */
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{ 0x47, 0x64, 0xc0c7 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=0, EQ_DATA_LO=0x67 */
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{ 0x47, 0x63, 0x0647 }, /* EQ_DATA_HI=0x0647 */
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{ 0x47, 0x64, 0xc1c7 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=1, EQ_DATA_LO=0x67 */
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{ 0x47, 0x63, 0xf370 }, /* EQ_DATA_HI=0xf370 */
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{ 0x47, 0x64, 0xc271 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=2, EQ_DATA_LO=0x71 */
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{ 0x47, 0x63, 0x1ef8 }, /* EQ_DATA_HI=0x1ef8 */
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{ 0x47, 0x64, 0xc348 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=3, EQ_DATA_LO=0x48 */
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{ 0x47, 0x63, 0xc110 }, /* EQ_DATA_HI=0xc110 */
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{ 0x47, 0x64, 0xc45a }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=4, EQ_DATA_LO=0x5a */
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{ 0x47, 0x63, 0x1f29 }, /* EQ_DATA_HI=0x1f29 */
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{ 0x47, 0x64, 0xc574 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=5, EQ_DATA_LO=0x74 */
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{ 0x47, 0x63, 0x1d7a }, /* EQ_DATA_HI=0x1d7a */
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{ 0x47, 0x64, 0xc653 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=6, EQ_DATA_LO=0x53 */
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{ 0x47, 0x63, 0xc38c }, /* EQ_DATA_HI=0xc38c */
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{ 0x47, 0x64, 0xc714 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=7, EQ_DATA_LO=0x14 */
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{ 0x47, 0x63, 0x1ca3 }, /* EQ_DATA_HI=0x1ca3 */
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{ 0x47, 0x64, 0xc8c7 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=8, EQ_DATA_LO=0xc7 */
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{ 0x47, 0x63, 0xc38c }, /* EQ_DATA_HI=0xc38c */
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{ 0x47, 0x64, 0xc914 }, /* +EQ_WRT, +EQ_ACC, EQ_ADR=9, EQ_DATA_LO=0x14 */
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{ 0x47, 0x64, 0x0000 }, /* -EQ_ACC, -EQ_WRT */
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/* EQ_SEL=1, EQ1/2_EN=0 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_CTRL1, 0x4000 },
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/* +EQ_ACC */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0x4000 },
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/* +EQ2_EN */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_CTRL1, 0x4010 },
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/* EQ_DATA_HI=0x0647 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x0647 },
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/* +EQ_WRT, +EQ_ACC, EQ_ADR=0, EQ_DATA_LO=0x67 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc0c7 },
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/* EQ_DATA_HI=0x0647 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x0647 },
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/* +EQ_WRT, +EQ_ACC, EQ_ADR=1, EQ_DATA_LO=0x67 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc1c7 },
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/* EQ_DATA_HI=0xf370 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xf370 },
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/* +EQ_WRT, +EQ_ACC, EQ_ADR=2, EQ_DATA_LO=0x71 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc271 },
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/* EQ_DATA_HI=0x1ef8 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1ef8 },
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/* +EQ_WRT, +EQ_ACC, EQ_ADR=3, EQ_DATA_LO=0x48 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc348 },
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/* EQ_DATA_HI=0xc110 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc110 },
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/* +EQ_WRT, +EQ_ACC, EQ_ADR=4, EQ_DATA_LO=0x5a */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc45a },
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/* EQ_DATA_HI=0x1f29 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1f29 },
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/* +EQ_WRT, +EQ_ACC, EQ_ADR=5, EQ_DATA_LO=0x74 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc574 },
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/* EQ_DATA_HI=0x1d7a */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1d7a },
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/* +EQ_WRT, +EQ_ACC, EQ_ADR=6, EQ_DATA_LO=0x53 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc653 },
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/* EQ_DATA_HI=0xc38c */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc38c },
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/* +EQ_WRT, +EQ_ACC, EQ_ADR=7, EQ_DATA_LO=0x14 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc714 },
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/* EQ_DATA_HI=0x1ca3 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1ca3 },
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/* +EQ_WRT, +EQ_ACC, EQ_ADR=8, EQ_DATA_LO=0xc7 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc8c7 },
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/* EQ_DATA_HI=0xc38c */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc38c },
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/* +EQ_WRT, +EQ_ACC, EQ_ADR=9, EQ_DATA_LO=0x14 */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc914 },
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/* -EQ_ACC, -EQ_WRT */
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{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0x0000 },
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{} /* Terminator */
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};
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@ -61,15 +61,15 @@ static struct cs8409_spec *cs8409_alloc_spec(struct hda_codec *codec)
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static inline int cs8409_vendor_coef_get(struct hda_codec *codec, unsigned int idx)
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{
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snd_hda_codec_write(codec, CS8409_VENDOR_NID, 0, AC_VERB_SET_COEF_INDEX, idx);
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return snd_hda_codec_read(codec, CS8409_VENDOR_NID, 0, AC_VERB_GET_PROC_COEF, 0);
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snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
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return snd_hda_codec_read(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_GET_PROC_COEF, 0);
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}
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static inline void cs8409_vendor_coef_set(struct hda_codec *codec, unsigned int idx,
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unsigned int coef)
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{
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snd_hda_codec_write(codec, CS8409_VENDOR_NID, 0, AC_VERB_SET_COEF_INDEX, idx);
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snd_hda_codec_write(codec, CS8409_VENDOR_NID, 0, AC_VERB_SET_PROC_COEF, coef);
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snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
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snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_PROC_COEF, coef);
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}
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/**
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@ -102,7 +102,7 @@ static int cs8409_i2c_wait_complete(struct hda_codec *codec)
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unsigned int retval;
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do {
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retval = cs8409_vendor_coef_get(codec, CIR_I2C_STATUS);
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retval = cs8409_vendor_coef_get(codec, CS8409_I2C_STS);
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if ((retval & 0x18) != 0x18) {
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usleep_range(2000, 4000);
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--repeat;
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@ -131,10 +131,10 @@ static int cs8409_i2c_read(struct hda_codec *codec, unsigned int i2c_address, un
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unsigned int read_data;
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cs8409_enable_i2c_clock(codec, 1);
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cs8409_vendor_coef_set(codec, CIR_I2C_ADDR, i2c_address);
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cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, i2c_address);
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if (paged) {
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cs8409_vendor_coef_set(codec, CIR_I2C_QWRITE, i2c_reg >> 8);
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cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8);
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if (cs8409_i2c_wait_complete(codec) < 0) {
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codec_err(codec, "%s() Paged Transaction Failed 0x%02x : 0x%04x\n",
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__func__, i2c_address, i2c_reg);
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@ -143,7 +143,7 @@ static int cs8409_i2c_read(struct hda_codec *codec, unsigned int i2c_address, un
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}
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i2c_reg_data = (i2c_reg << 8) & 0x0ffff;
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cs8409_vendor_coef_set(codec, CIR_I2C_QREAD, i2c_reg_data);
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cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
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if (cs8409_i2c_wait_complete(codec) < 0) {
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codec_err(codec, "%s() Transaction Failed 0x%02x : 0x%04x\n",
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__func__, i2c_address, i2c_reg);
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@ -151,7 +151,7 @@ static int cs8409_i2c_read(struct hda_codec *codec, unsigned int i2c_address, un
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}
|
||||
|
||||
/* Register in bits 15-8 and the data in 7-0 */
|
||||
read_data = cs8409_vendor_coef_get(codec, CIR_I2C_QREAD);
|
||||
read_data = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD);
|
||||
|
||||
cs8409_enable_i2c_clock(codec, 0);
|
||||
|
||||
|
|
@ -175,10 +175,10 @@ static int cs8409_i2c_write(struct hda_codec *codec, unsigned int i2c_address, u
|
|||
unsigned int i2c_reg_data;
|
||||
|
||||
cs8409_enable_i2c_clock(codec, 1);
|
||||
cs8409_vendor_coef_set(codec, CIR_I2C_ADDR, i2c_address);
|
||||
cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, i2c_address);
|
||||
|
||||
if (paged) {
|
||||
cs8409_vendor_coef_set(codec, CIR_I2C_QWRITE, i2c_reg >> 8);
|
||||
cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8);
|
||||
if (cs8409_i2c_wait_complete(codec) < 0) {
|
||||
codec_err(codec, "%s() Paged Transaction Failed 0x%02x : 0x%04x\n",
|
||||
__func__, i2c_address, i2c_reg);
|
||||
|
|
@ -187,7 +187,7 @@ static int cs8409_i2c_write(struct hda_codec *codec, unsigned int i2c_address, u
|
|||
}
|
||||
|
||||
i2c_reg_data = ((i2c_reg << 8) & 0x0ff00) | (i2c_data & 0x0ff);
|
||||
cs8409_vendor_coef_set(codec, CIR_I2C_QWRITE, i2c_reg_data);
|
||||
cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
|
||||
|
||||
if (cs8409_i2c_wait_complete(codec) < 0) {
|
||||
codec_err(codec, "%s() Transaction Failed 0x%02x : 0x%04x\n",
|
||||
|
|
@ -363,11 +363,11 @@ static void cs8409_cs42l42_reset(struct hda_codec *codec)
|
|||
struct cs8409_spec *spec = codec->spec;
|
||||
|
||||
/* Assert RTS# line */
|
||||
snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_SET_GPIO_DATA, 0);
|
||||
snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, 0);
|
||||
/* wait ~10ms */
|
||||
usleep_range(10000, 15000);
|
||||
/* Release RTS# line */
|
||||
snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_SET_GPIO_DATA, GPIO5_INT);
|
||||
snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, CS8409_CS42L42_RESET);
|
||||
/* wait ~10ms */
|
||||
usleep_range(10000, 15000);
|
||||
|
||||
|
|
@ -471,7 +471,7 @@ static void cs8409_jack_unsol_event(struct hda_codec *codec, unsigned int res)
|
|||
* registers in previous cs8409_jack_unsol_event() call.
|
||||
* We don't need to handle this event, ignoring...
|
||||
*/
|
||||
if ((res & (1 << 4)))
|
||||
if (res & CS8409_CS42L42_INT)
|
||||
return;
|
||||
|
||||
mutex_lock(&spec->cs8409_i2c_mux);
|
||||
|
|
@ -568,7 +568,7 @@ static int cs8409_suspend(struct hda_codec *codec)
|
|||
cs8409_i2c_write(codec, CS42L42_I2C_ADDR, 0x1101, 0xfe, 1);
|
||||
mutex_unlock(&spec->cs8409_i2c_mux);
|
||||
/* Assert CS42L42 RTS# line */
|
||||
snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_SET_GPIO_DATA, 0);
|
||||
snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, 0);
|
||||
|
||||
snd_hda_shutup_pins(codec);
|
||||
|
||||
|
|
@ -580,10 +580,10 @@ static int cs8409_suspend(struct hda_codec *codec)
|
|||
static void cs8409_enable_ur(struct hda_codec *codec, int flag)
|
||||
{
|
||||
/* GPIO4 INT# and GPIO3 WAKE# */
|
||||
snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK,
|
||||
flag ? (GPIO3_INT | GPIO4_INT) : 0);
|
||||
snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK,
|
||||
flag ? CS8409_CS42L42_INT : 0);
|
||||
|
||||
snd_hda_codec_write(codec, codec->core.afg, 0, AC_VERB_SET_UNSOLICITED_ENABLE,
|
||||
snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_UNSOLICITED_ENABLE,
|
||||
flag ? AC_UNSOL_ENABLED : 0);
|
||||
|
||||
}
|
||||
|
|
@ -598,9 +598,12 @@ static void cs8409_cs42l42_hw_init(struct hda_codec *codec)
|
|||
struct cs8409_spec *spec = codec->spec;
|
||||
|
||||
if (spec->gpio_mask) {
|
||||
snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_MASK, spec->gpio_mask);
|
||||
snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DIRECTION, spec->gpio_dir);
|
||||
snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data);
|
||||
snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
|
||||
spec->gpio_mask);
|
||||
snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
|
||||
spec->gpio_dir);
|
||||
snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
|
||||
spec->gpio_data);
|
||||
}
|
||||
|
||||
for (; seq->nid; seq++)
|
||||
|
|
@ -738,7 +741,7 @@ void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix,
|
|||
spec->gen.suppress_vmaster = 1;
|
||||
|
||||
/* GPIO 5 out, 3,4 in */
|
||||
spec->gpio_dir = GPIO5_INT;
|
||||
spec->gpio_dir = CS8409_CS42L42_RESET;
|
||||
spec->gpio_data = 0;
|
||||
spec->gpio_mask = 0x03f;
|
||||
|
||||
|
|
|
|||
|
|
@ -17,39 +17,207 @@
|
|||
#include "hda_jack.h"
|
||||
#include "hda_generic.h"
|
||||
|
||||
/* Cirrus Logic CS8409 HDA bridge with
|
||||
* companion codec CS42L42
|
||||
*/
|
||||
/* CS8409 Specific Definitions */
|
||||
|
||||
enum cs8409_pins {
|
||||
CS8409_PIN_ROOT,
|
||||
CS8409_PIN_AFG,
|
||||
CS8409_PIN_ASP1_OUT_A,
|
||||
CS8409_PIN_ASP1_OUT_B,
|
||||
CS8409_PIN_ASP1_OUT_C,
|
||||
CS8409_PIN_ASP1_OUT_D,
|
||||
CS8409_PIN_ASP1_OUT_E,
|
||||
CS8409_PIN_ASP1_OUT_F,
|
||||
CS8409_PIN_ASP1_OUT_G,
|
||||
CS8409_PIN_ASP1_OUT_H,
|
||||
CS8409_PIN_ASP2_OUT_A,
|
||||
CS8409_PIN_ASP2_OUT_B,
|
||||
CS8409_PIN_ASP2_OUT_C,
|
||||
CS8409_PIN_ASP2_OUT_D,
|
||||
CS8409_PIN_ASP2_OUT_E,
|
||||
CS8409_PIN_ASP2_OUT_F,
|
||||
CS8409_PIN_ASP2_OUT_G,
|
||||
CS8409_PIN_ASP2_OUT_H,
|
||||
CS8409_PIN_ASP1_IN_A,
|
||||
CS8409_PIN_ASP1_IN_B,
|
||||
CS8409_PIN_ASP1_IN_C,
|
||||
CS8409_PIN_ASP1_IN_D,
|
||||
CS8409_PIN_ASP1_IN_E,
|
||||
CS8409_PIN_ASP1_IN_F,
|
||||
CS8409_PIN_ASP1_IN_G,
|
||||
CS8409_PIN_ASP1_IN_H,
|
||||
CS8409_PIN_ASP2_IN_A,
|
||||
CS8409_PIN_ASP2_IN_B,
|
||||
CS8409_PIN_ASP2_IN_C,
|
||||
CS8409_PIN_ASP2_IN_D,
|
||||
CS8409_PIN_ASP2_IN_E,
|
||||
CS8409_PIN_ASP2_IN_F,
|
||||
CS8409_PIN_ASP2_IN_G,
|
||||
CS8409_PIN_ASP2_IN_H,
|
||||
CS8409_PIN_DMIC1,
|
||||
CS8409_PIN_DMIC2,
|
||||
CS8409_PIN_ASP1_TRANSMITTER_A,
|
||||
CS8409_PIN_ASP1_TRANSMITTER_B,
|
||||
CS8409_PIN_ASP1_TRANSMITTER_C,
|
||||
CS8409_PIN_ASP1_TRANSMITTER_D,
|
||||
CS8409_PIN_ASP1_TRANSMITTER_E,
|
||||
CS8409_PIN_ASP1_TRANSMITTER_F,
|
||||
CS8409_PIN_ASP1_TRANSMITTER_G,
|
||||
CS8409_PIN_ASP1_TRANSMITTER_H,
|
||||
CS8409_PIN_ASP2_TRANSMITTER_A,
|
||||
CS8409_PIN_ASP2_TRANSMITTER_B,
|
||||
CS8409_PIN_ASP2_TRANSMITTER_C,
|
||||
CS8409_PIN_ASP2_TRANSMITTER_D,
|
||||
CS8409_PIN_ASP2_TRANSMITTER_E,
|
||||
CS8409_PIN_ASP2_TRANSMITTER_F,
|
||||
CS8409_PIN_ASP2_TRANSMITTER_G,
|
||||
CS8409_PIN_ASP2_TRANSMITTER_H,
|
||||
CS8409_PIN_ASP1_RECEIVER_A,
|
||||
CS8409_PIN_ASP1_RECEIVER_B,
|
||||
CS8409_PIN_ASP1_RECEIVER_C,
|
||||
CS8409_PIN_ASP1_RECEIVER_D,
|
||||
CS8409_PIN_ASP1_RECEIVER_E,
|
||||
CS8409_PIN_ASP1_RECEIVER_F,
|
||||
CS8409_PIN_ASP1_RECEIVER_G,
|
||||
CS8409_PIN_ASP1_RECEIVER_H,
|
||||
CS8409_PIN_ASP2_RECEIVER_A,
|
||||
CS8409_PIN_ASP2_RECEIVER_B,
|
||||
CS8409_PIN_ASP2_RECEIVER_C,
|
||||
CS8409_PIN_ASP2_RECEIVER_D,
|
||||
CS8409_PIN_ASP2_RECEIVER_E,
|
||||
CS8409_PIN_ASP2_RECEIVER_F,
|
||||
CS8409_PIN_ASP2_RECEIVER_G,
|
||||
CS8409_PIN_ASP2_RECEIVER_H,
|
||||
CS8409_PIN_DMIC1_IN,
|
||||
CS8409_PIN_DMIC2_IN,
|
||||
CS8409_PIN_BEEP_GEN,
|
||||
CS8409_PIN_VENDOR_WIDGET
|
||||
};
|
||||
|
||||
enum cs8409_coefficient_index_registers {
|
||||
CS8409_DEV_CFG1,
|
||||
CS8409_DEV_CFG2,
|
||||
CS8409_DEV_CFG3,
|
||||
CS8409_ASP1_CLK_CTRL1,
|
||||
CS8409_ASP1_CLK_CTRL2,
|
||||
CS8409_ASP1_CLK_CTRL3,
|
||||
CS8409_ASP2_CLK_CTRL1,
|
||||
CS8409_ASP2_CLK_CTRL2,
|
||||
CS8409_ASP2_CLK_CTRL3,
|
||||
CS8409_DMIC_CFG,
|
||||
CS8409_BEEP_CFG,
|
||||
ASP1_RX_NULL_INS_RMV,
|
||||
ASP1_Rx_RATE1,
|
||||
ASP1_Rx_RATE2,
|
||||
ASP1_Tx_NULL_INS_RMV,
|
||||
ASP1_Tx_RATE1,
|
||||
ASP1_Tx_RATE2,
|
||||
ASP2_Rx_NULL_INS_RMV,
|
||||
ASP2_Rx_RATE1,
|
||||
ASP2_Rx_RATE2,
|
||||
ASP2_Tx_NULL_INS_RMV,
|
||||
ASP2_Tx_RATE1,
|
||||
ASP2_Tx_RATE2,
|
||||
ASP1_SYNC_CTRL,
|
||||
ASP2_SYNC_CTRL,
|
||||
ASP1_A_TX_CTRL1,
|
||||
ASP1_A_TX_CTRL2,
|
||||
ASP1_B_TX_CTRL1,
|
||||
ASP1_B_TX_CTRL2,
|
||||
ASP1_C_TX_CTRL1,
|
||||
ASP1_C_TX_CTRL2,
|
||||
ASP1_D_TX_CTRL1,
|
||||
ASP1_D_TX_CTRL2,
|
||||
ASP1_E_TX_CTRL1,
|
||||
ASP1_E_TX_CTRL2,
|
||||
ASP1_F_TX_CTRL1,
|
||||
ASP1_F_TX_CTRL2,
|
||||
ASP1_G_TX_CTRL1,
|
||||
ASP1_G_TX_CTRL2,
|
||||
ASP1_H_TX_CTRL1,
|
||||
ASP1_H_TX_CTRL2,
|
||||
ASP2_A_TX_CTRL1,
|
||||
ASP2_A_TX_CTRL2,
|
||||
ASP2_B_TX_CTRL1,
|
||||
ASP2_B_TX_CTRL2,
|
||||
ASP2_C_TX_CTRL1,
|
||||
ASP2_C_TX_CTRL2,
|
||||
ASP2_D_TX_CTRL1,
|
||||
ASP2_D_TX_CTRL2,
|
||||
ASP2_E_TX_CTRL1,
|
||||
ASP2_E_TX_CTRL2,
|
||||
ASP2_F_TX_CTRL1,
|
||||
ASP2_F_TX_CTRL2,
|
||||
ASP2_G_TX_CTRL1,
|
||||
ASP2_G_TX_CTRL2,
|
||||
ASP2_H_TX_CTRL1,
|
||||
ASP2_H_TX_CTRL2,
|
||||
ASP1_A_RX_CTRL1,
|
||||
ASP1_A_RX_CTRL2,
|
||||
ASP1_B_RX_CTRL1,
|
||||
ASP1_B_RX_CTRL2,
|
||||
ASP1_C_RX_CTRL1,
|
||||
ASP1_C_RX_CTRL2,
|
||||
ASP1_D_RX_CTRL1,
|
||||
ASP1_D_RX_CTRL2,
|
||||
ASP1_E_RX_CTRL1,
|
||||
ASP1_E_RX_CTRL2,
|
||||
ASP1_F_RX_CTRL1,
|
||||
ASP1_F_RX_CTRL2,
|
||||
ASP1_G_RX_CTRL1,
|
||||
ASP1_G_RX_CTRL2,
|
||||
ASP1_H_RX_CTRL1,
|
||||
ASP1_H_RX_CTRL2,
|
||||
ASP2_A_RX_CTRL1,
|
||||
ASP2_A_RX_CTRL2,
|
||||
ASP2_B_RX_CTRL1,
|
||||
ASP2_B_RX_CTRL2,
|
||||
ASP2_C_RX_CTRL1,
|
||||
ASP2_C_RX_CTRL2,
|
||||
ASP2_D_RX_CTRL1,
|
||||
ASP2_D_RX_CTRL2,
|
||||
ASP2_E_RX_CTRL1,
|
||||
ASP2_E_RX_CTRL2,
|
||||
ASP2_F_RX_CTRL1,
|
||||
ASP2_F_RX_CTRL2,
|
||||
ASP2_G_RX_CTRL1,
|
||||
ASP2_G_RX_CTRL2,
|
||||
ASP2_H_RX_CTRL1,
|
||||
ASP2_H_RX_CTRL2,
|
||||
CS8409_I2C_ADDR,
|
||||
CS8409_I2C_DATA,
|
||||
CS8409_I2C_CTRL,
|
||||
CS8409_I2C_STS,
|
||||
CS8409_I2C_QWRITE,
|
||||
CS8409_I2C_QREAD,
|
||||
CS8409_SPI_CTRL,
|
||||
CS8409_SPI_TX_DATA,
|
||||
CS8409_SPI_RX_DATA,
|
||||
CS8409_SPI_STS,
|
||||
CS8409_PFE_COEF_W1, /* Parametric filter engine coefficient write 1*/
|
||||
CS8409_PFE_COEF_W2,
|
||||
CS8409_PFE_CTRL1,
|
||||
CS8409_PFE_CTRL2,
|
||||
CS8409_PRE_SCALE_ATTN1,
|
||||
CS8409_PRE_SCALE_ATTN2,
|
||||
CS8409_PFE_COEF_MON1, /* Parametric filter engine coefficient monitor 1*/
|
||||
CS8409_PFE_COEF_MON2,
|
||||
CS8409_ASP1_INTRN_STS,
|
||||
CS8409_ASP2_INTRN_STS,
|
||||
CS8409_ASP1_RX_SCLK_COUNT,
|
||||
CS8409_ASP1_TX_SCLK_COUNT,
|
||||
CS8409_ASP2_RX_SCLK_COUNT,
|
||||
CS8409_ASP2_TX_SCLK_COUNT,
|
||||
CS8409_ASP_UNS_RESP_MASK,
|
||||
CS8409_LOOPBACK_CTRL = 0x80,
|
||||
CS8409_PAD_CFG_SLW_RATE_CTRL = 0x82, /* Pad Config and Slew Rate Control (CIR = 0x0082) */
|
||||
};
|
||||
|
||||
/* CS42L42 Specific Definitions */
|
||||
|
||||
#define CS42L42_HP_CH (2U)
|
||||
#define CS42L42_HS_MIC_CH (1U)
|
||||
|
||||
#define CS8409_VENDOR_NID 0x47
|
||||
|
||||
#define CS8409_CS42L42_HP_PIN_NID 0x24
|
||||
#define CS8409_CS42L42_SPK_PIN_NID 0x2c
|
||||
#define CS8409_CS42L42_AMIC_PIN_NID 0x34
|
||||
#define CS8409_CS42L42_DMIC_PIN_NID 0x44
|
||||
#define CS8409_CS42L42_DMIC_ADC_PIN_NID 0x22
|
||||
|
||||
#define CS42L42_HSDET_AUTO_DONE 0x02
|
||||
#define CS42L42_HSTYPE_MASK 0x03
|
||||
|
||||
#define CS42L42_JACK_INSERTED 0x0C
|
||||
#define CS42L42_JACK_REMOVED 0x00
|
||||
|
||||
#define GPIO3_INT (1 << 3)
|
||||
#define GPIO4_INT (1 << 4)
|
||||
#define GPIO5_INT (1 << 5)
|
||||
|
||||
#define CS42L42_I2C_ADDR (0x48 << 1)
|
||||
|
||||
#define CIR_I2C_ADDR 0x0059
|
||||
#define CIR_I2C_DATA 0x005A
|
||||
#define CIR_I2C_CTRL 0x005B
|
||||
#define CIR_I2C_STATUS 0x005C
|
||||
#define CIR_I2C_QWRITE 0x005D
|
||||
#define CIR_I2C_QREAD 0x005E
|
||||
|
||||
#define CS8409_CS42L42_HP_VOL_REAL_MIN (-63)
|
||||
#define CS8409_CS42L42_HP_VOL_REAL_MAX (0)
|
||||
#define CS8409_CS42L42_AMIC_VOL_REAL_MIN (-97)
|
||||
|
|
@ -57,6 +225,21 @@
|
|||
#define CS8409_CS42L42_REG_HS_VOLUME_CHA (0x2301)
|
||||
#define CS8409_CS42L42_REG_HS_VOLUME_CHB (0x2303)
|
||||
#define CS8409_CS42L42_REG_AMIC_VOLUME (0x1D03)
|
||||
#define CS42L42_HSDET_AUTO_DONE (0x02)
|
||||
#define CS42L42_HSTYPE_MASK (0x03)
|
||||
#define CS42L42_JACK_INSERTED (0x0C)
|
||||
#define CS42L42_JACK_REMOVED (0x00)
|
||||
|
||||
/* Dell BULLSEYE / WARLOCK / CYBORG Specific Definitions */
|
||||
|
||||
#define CS42L42_I2C_ADDR (0x48 << 1)
|
||||
#define CS8409_CS42L42_RESET GENMASK(5, 5) /* CS8409_GPIO5 */
|
||||
#define CS8409_CS42L42_INT GENMASK(4, 4) /* CS8409_GPIO4 */
|
||||
#define CS8409_CS42L42_HP_PIN_NID CS8409_PIN_ASP1_TRANSMITTER_A
|
||||
#define CS8409_CS42L42_SPK_PIN_NID CS8409_PIN_ASP2_TRANSMITTER_A
|
||||
#define CS8409_CS42L42_AMIC_PIN_NID CS8409_PIN_ASP1_RECEIVER_A
|
||||
#define CS8409_CS42L42_DMIC_PIN_NID CS8409_PIN_DMIC1_IN
|
||||
#define CS8409_CS42L42_DMIC_ADC_PIN_NID CS8409_PIN_DMIC1
|
||||
|
||||
enum {
|
||||
CS8409_BULLSEYE,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user