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igb/e1000e: update PSSR_MDIX value to reflect correct bit

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The phy port status register has the MDI-X status bit on bit 11, not bit 3
as is currently setup in the define.  This patch corrects that so the
correct bit is checked on igp PHY types.

Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Acked-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alexander Duyck 2009-05-26 13:51:05 +00:00 committed by David S. Miller
parent 3ea73afafb
commit cbe7a81a73
2 changed files with 2 additions and 2 deletions
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2
drivers/net/e1000e/hw.h
View File

@ -253,7 +253,7 @@ enum e1e_registers {
#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
#define IGP01E1000_PSSR_MDIX 0x0008
#define IGP01E1000_PSSR_MDIX 0x0800
#define IGP01E1000_PSSR_SPEED_MASK 0xC000
#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000

2
drivers/net/igb/e1000_phy.h
View File

@ -80,7 +80,7 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
#define IGP01E1000_PSSR_MDIX 0x0008
#define IGP01E1000_PSSR_MDIX 0x0800
#define IGP01E1000_PSSR_SPEED_MASK 0xC000
#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
#define IGP02E1000_PHY_CHANNEL_NUM 4