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drm/msm: add msm8998 hdmi phy/pll support
Add support for the HDMI PHY as present on the Qualcomm MSM8998 SoC. This code is mostly copy & paste of the vendor code from msm-4.4 kernel.lnx.4.4.r38-rel. Signed-off-by: Arnaud Vrac <avrac@freebox.fr> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> Patchwork: https://patchwork.freedesktop.org/patch/605631/ Link: https://lore.kernel.org/r/20240724-hdmi-tx-v7-4-e44a20553464@freebox.fr [DB: replaced division with do_div64 to fix build issues on ARM32] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Arnaud Vrac
Dmitry Baryshkov
parent
a61eb17f40
commit
caedbf17c4
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@ -37,6 +37,7 @@ msm-display-$(CONFIG_DRM_MSM_HDMI) += \
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hdmi/hdmi_phy.o \
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hdmi/hdmi_phy_8960.o \
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hdmi/hdmi_phy_8996.o \
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hdmi/hdmi_phy_8998.o \
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hdmi/hdmi_phy_8x60.o \
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hdmi/hdmi_phy_8x74.o \
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hdmi/hdmi_pll_8960.o \
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@ -137,6 +137,7 @@ enum hdmi_phy_type {
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MSM_HDMI_PHY_8960,
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MSM_HDMI_PHY_8x74,
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MSM_HDMI_PHY_8996,
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MSM_HDMI_PHY_8998,
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MSM_HDMI_PHY_MAX,
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};
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@ -154,6 +155,7 @@ extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
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extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
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extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
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extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
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extern const struct hdmi_phy_cfg msm_hdmi_phy_8998_cfg;
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struct hdmi_phy {
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struct platform_device *pdev;
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@ -184,6 +186,7 @@ void __exit msm_hdmi_phy_driver_unregister(void);
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#ifdef CONFIG_COMMON_CLK
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int msm_hdmi_pll_8960_init(struct platform_device *pdev);
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int msm_hdmi_pll_8996_init(struct platform_device *pdev);
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int msm_hdmi_pll_8998_init(struct platform_device *pdev);
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#else
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static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
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{
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@ -194,6 +197,11 @@ static inline int msm_hdmi_pll_8996_init(struct platform_device *pdev)
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{
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return -ENODEV;
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}
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static inline int msm_hdmi_pll_8998_init(struct platform_device *pdev)
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{
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return -ENODEV;
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}
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#endif
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/*
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@ -118,6 +118,9 @@ static int msm_hdmi_phy_pll_init(struct platform_device *pdev,
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case MSM_HDMI_PHY_8996:
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ret = msm_hdmi_pll_8996_init(pdev);
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break;
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case MSM_HDMI_PHY_8998:
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ret = msm_hdmi_pll_8998_init(pdev);
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break;
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/*
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* we don't have PLL support for these, don't report an error for now
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*/
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@ -193,6 +196,8 @@ static const struct of_device_id msm_hdmi_phy_dt_match[] = {
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.data = &msm_hdmi_phy_8x74_cfg },
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{ .compatible = "qcom,hdmi-phy-8996",
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.data = &msm_hdmi_phy_8996_cfg },
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{ .compatible = "qcom,hdmi-phy-8998",
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.data = &msm_hdmi_phy_8998_cfg },
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{}
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};
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779
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
Normal file
779
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c
Normal file
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@ -0,0 +1,779 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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* Copyright (c) 2024 Freebox SAS
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include "hdmi.h"
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#define HDMI_VCO_MAX_FREQ 12000000000UL
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#define HDMI_VCO_MIN_FREQ 8000000000UL
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#define HDMI_PCLK_MAX_FREQ 600000000
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#define HDMI_PCLK_MIN_FREQ 25000000
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#define HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD 3400000000UL
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#define HDMI_DIG_FREQ_BIT_CLK_THRESHOLD 1500000000UL
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#define HDMI_MID_FREQ_BIT_CLK_THRESHOLD 750000000UL
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#define HDMI_CORECLK_DIV 5
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#define HDMI_DEFAULT_REF_CLOCK 19200000
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#define HDMI_PLL_CMP_CNT 1024
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#define HDMI_PLL_POLL_MAX_READS 100
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#define HDMI_PLL_POLL_TIMEOUT_US 150
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#define HDMI_NUM_TX_CHANNEL 4
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struct hdmi_pll_8998 {
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struct platform_device *pdev;
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struct clk_hw clk_hw;
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unsigned long rate;
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/* pll mmio base */
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void __iomem *mmio_qserdes_com;
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/* tx channel base */
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void __iomem *mmio_qserdes_tx[HDMI_NUM_TX_CHANNEL];
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};
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#define hw_clk_to_pll(x) container_of(x, struct hdmi_pll_8998, clk_hw)
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struct hdmi_8998_phy_pll_reg_cfg {
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u32 com_svs_mode_clk_sel;
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u32 com_hsclk_sel;
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u32 com_pll_cctrl_mode0;
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u32 com_pll_rctrl_mode0;
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u32 com_cp_ctrl_mode0;
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u32 com_dec_start_mode0;
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u32 com_div_frac_start1_mode0;
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u32 com_div_frac_start2_mode0;
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u32 com_div_frac_start3_mode0;
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u32 com_integloop_gain0_mode0;
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u32 com_integloop_gain1_mode0;
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u32 com_lock_cmp_en;
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u32 com_lock_cmp1_mode0;
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u32 com_lock_cmp2_mode0;
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u32 com_lock_cmp3_mode0;
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u32 com_core_clk_en;
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u32 com_coreclk_div_mode0;
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u32 tx_lx_tx_band[HDMI_NUM_TX_CHANNEL];
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u32 tx_lx_tx_drv_lvl[HDMI_NUM_TX_CHANNEL];
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u32 tx_lx_tx_emp_post1_lvl[HDMI_NUM_TX_CHANNEL];
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u32 tx_lx_pre_driver_1[HDMI_NUM_TX_CHANNEL];
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u32 tx_lx_pre_driver_2[HDMI_NUM_TX_CHANNEL];
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u32 tx_lx_res_code_offset[HDMI_NUM_TX_CHANNEL];
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u32 phy_mode;
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};
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struct hdmi_8998_post_divider {
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u64 vco_freq;
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int hsclk_divsel;
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int vco_ratio;
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int tx_band_sel;
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int half_rate_mode;
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};
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static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8998 *pll)
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{
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return platform_get_drvdata(pll->pdev);
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}
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static inline void hdmi_pll_write(struct hdmi_pll_8998 *pll, int offset,
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u32 data)
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{
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writel(data, pll->mmio_qserdes_com + offset);
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}
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static inline u32 hdmi_pll_read(struct hdmi_pll_8998 *pll, int offset)
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{
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return readl(pll->mmio_qserdes_com + offset);
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}
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static inline void hdmi_tx_chan_write(struct hdmi_pll_8998 *pll, int channel,
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int offset, int data)
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{
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writel(data, pll->mmio_qserdes_tx[channel] + offset);
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}
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static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,
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bool gen_ssc)
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{
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if ((frac_start != 0) || gen_ssc)
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return 0x8;
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return 0x30;
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}
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static inline u32 pll_get_rctrl(u64 frac_start, bool gen_ssc)
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{
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if ((frac_start != 0) || gen_ssc)
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return 0x16;
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return 0x18;
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}
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static inline u32 pll_get_cctrl(u64 frac_start, bool gen_ssc)
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{
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if ((frac_start != 0) || gen_ssc)
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return 0x34;
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return 0x2;
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}
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static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk,
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bool gen_ssc)
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{
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int digclk_divsel = bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2;
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u64 base;
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if ((frac_start != 0) || gen_ssc)
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base = 0x3F;
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else
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base = 0xC4;
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base <<= (digclk_divsel == 2 ? 1 : 0);
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return (base <= 2046 ? base : 2046);
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}
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static inline u32 pll_get_pll_cmp(u64 fdata, unsigned long ref_clk)
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{
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u64 dividend = HDMI_PLL_CMP_CNT * fdata;
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u32 divisor = ref_clk * 10;
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u32 rem;
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rem = do_div(dividend, divisor);
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if (rem > (divisor >> 1))
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dividend++;
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return dividend - 1;
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}
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static inline u64 pll_cmp_to_fdata(u32 pll_cmp, unsigned long ref_clk)
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{
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u64 fdata = ((u64)pll_cmp) * ref_clk * 10;
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do_div(fdata, HDMI_PLL_CMP_CNT);
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return fdata;
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}
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#define HDMI_REF_CLOCK_HZ ((u64)19200000)
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#define HDMI_MHZ_TO_HZ ((u64)1000000)
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static int pll_get_post_div(struct hdmi_8998_post_divider *pd, u64 bclk)
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{
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u32 const ratio_list[] = {1, 2, 3, 4, 5, 6,
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9, 10, 12, 15, 25};
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u32 const band_list[] = {0, 1, 2, 3};
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u32 const sz_ratio = ARRAY_SIZE(ratio_list);
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u32 const sz_band = ARRAY_SIZE(band_list);
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u32 const cmp_cnt = 1024;
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u32 const th_min = 500, th_max = 1000;
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u32 half_rate_mode = 0;
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u32 list_elements;
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int optimal_index;
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u32 i, j, k;
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u32 found_hsclk_divsel = 0, found_vco_ratio;
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u32 found_tx_band_sel;
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u64 const min_freq = HDMI_VCO_MIN_FREQ, max_freq = HDMI_VCO_MAX_FREQ;
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u64 freq_list[ARRAY_SIZE(ratio_list) * ARRAY_SIZE(band_list)];
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u64 found_vco_freq;
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u64 freq_optimal;
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find_optimal_index:
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freq_optimal = max_freq;
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optimal_index = -1;
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list_elements = 0;
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for (i = 0; i < sz_ratio; i++) {
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for (j = 0; j < sz_band; j++) {
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u64 freq = div_u64(bclk, (1 << half_rate_mode));
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freq *= (ratio_list[i] * (1 << band_list[j]));
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freq_list[list_elements++] = freq;
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}
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}
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for (k = 0; k < ARRAY_SIZE(freq_list); k++) {
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u32 const clks_pll_div = 2, core_clk_div = 5;
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u32 const rng1 = 16, rng2 = 8;
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u32 th1, th2;
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u64 core_clk, rvar1, rem;
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core_clk = div_u64(freq_list[k],
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ratio_list[k / sz_band] * clks_pll_div *
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core_clk_div);
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rvar1 = HDMI_REF_CLOCK_HZ * rng1 * HDMI_MHZ_TO_HZ;
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rvar1 = div64_u64_rem(rvar1, (cmp_cnt * core_clk), &rem);
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if (rem > ((cmp_cnt * core_clk) >> 1))
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rvar1++;
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th1 = rvar1;
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rvar1 = HDMI_REF_CLOCK_HZ * rng2 * HDMI_MHZ_TO_HZ;
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rvar1 = div64_u64_rem(rvar1, (cmp_cnt * core_clk), &rem);
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if (rem > ((cmp_cnt * core_clk) >> 1))
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rvar1++;
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th2 = rvar1;
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if (freq_list[k] >= min_freq &&
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freq_list[k] <= max_freq) {
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if ((th1 >= th_min && th1 <= th_max) ||
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(th2 >= th_min && th2 <= th_max)) {
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if (freq_list[k] <= freq_optimal) {
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freq_optimal = freq_list[k];
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optimal_index = k;
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}
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}
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}
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}
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if (optimal_index == -1) {
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if (!half_rate_mode) {
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half_rate_mode = 1;
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goto find_optimal_index;
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} else {
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return -EINVAL;
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}
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} else {
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found_vco_ratio = ratio_list[optimal_index / sz_band];
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found_tx_band_sel = band_list[optimal_index % sz_band];
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found_vco_freq = freq_optimal;
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}
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switch (found_vco_ratio) {
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case 1:
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found_hsclk_divsel = 15;
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break;
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case 2:
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found_hsclk_divsel = 0;
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break;
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case 3:
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found_hsclk_divsel = 4;
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break;
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case 4:
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found_hsclk_divsel = 8;
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break;
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case 5:
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found_hsclk_divsel = 12;
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break;
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case 6:
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found_hsclk_divsel = 1;
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break;
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case 9:
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found_hsclk_divsel = 5;
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break;
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case 10:
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found_hsclk_divsel = 2;
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break;
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case 12:
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found_hsclk_divsel = 9;
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break;
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case 15:
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found_hsclk_divsel = 13;
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break;
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case 25:
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found_hsclk_divsel = 14;
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break;
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};
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pd->vco_freq = found_vco_freq;
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pd->tx_band_sel = found_tx_band_sel;
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pd->vco_ratio = found_vco_ratio;
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pd->hsclk_divsel = found_hsclk_divsel;
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return 0;
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}
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static int pll_calculate(unsigned long pix_clk, unsigned long ref_clk,
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struct hdmi_8998_phy_pll_reg_cfg *cfg)
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{
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struct hdmi_8998_post_divider pd;
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u64 bclk;
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u64 dec_start;
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u64 frac_start;
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u64 fdata;
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u32 pll_divisor;
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u32 rem;
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u32 cpctrl;
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u32 rctrl;
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u32 cctrl;
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u32 integloop_gain;
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u32 pll_cmp;
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int i, ret;
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/* bit clk = 10 * pix_clk */
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bclk = ((u64)pix_clk) * 10;
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ret = pll_get_post_div(&pd, bclk);
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if (ret)
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return ret;
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dec_start = pd.vco_freq;
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pll_divisor = 4 * ref_clk;
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do_div(dec_start, pll_divisor);
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frac_start = pd.vco_freq * (1 << 20);
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rem = do_div(frac_start, pll_divisor);
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frac_start -= dec_start * (1 << 20);
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if (rem > (pll_divisor >> 1))
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frac_start++;
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cpctrl = pll_get_cpctrl(frac_start, ref_clk, false);
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rctrl = pll_get_rctrl(frac_start, false);
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cctrl = pll_get_cctrl(frac_start, false);
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integloop_gain = pll_get_integloop_gain(frac_start, bclk,
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ref_clk, false);
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fdata = pd.vco_freq;
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do_div(fdata, pd.vco_ratio);
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pll_cmp = pll_get_pll_cmp(fdata, ref_clk);
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/* Convert these values to register specific values */
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if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD)
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cfg->com_svs_mode_clk_sel = 1;
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else
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cfg->com_svs_mode_clk_sel = 2;
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cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel);
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cfg->com_pll_cctrl_mode0 = cctrl;
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cfg->com_pll_rctrl_mode0 = rctrl;
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cfg->com_cp_ctrl_mode0 = cpctrl;
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cfg->com_dec_start_mode0 = dec_start;
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cfg->com_div_frac_start1_mode0 = (frac_start & 0xff);
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cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8);
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cfg->com_div_frac_start3_mode0 = ((frac_start & 0xf0000) >> 16);
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cfg->com_integloop_gain0_mode0 = (integloop_gain & 0xff);
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cfg->com_integloop_gain1_mode0 = ((integloop_gain & 0xf00) >> 8);
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cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xff);
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cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xff00) >> 8);
|
||||
cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16);
|
||||
cfg->com_lock_cmp_en = 0x0;
|
||||
cfg->com_core_clk_en = 0x2c;
|
||||
cfg->com_coreclk_div_mode0 = HDMI_CORECLK_DIV;
|
||||
cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x5 : 0x4;
|
||||
|
||||
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++)
|
||||
cfg->tx_lx_tx_band[i] = pd.tx_band_sel;
|
||||
|
||||
if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) {
|
||||
cfg->tx_lx_tx_drv_lvl[0] = 0x0f;
|
||||
cfg->tx_lx_tx_drv_lvl[1] = 0x0f;
|
||||
cfg->tx_lx_tx_drv_lvl[2] = 0x0f;
|
||||
cfg->tx_lx_tx_drv_lvl[3] = 0x0f;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[0] = 0x03;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[1] = 0x02;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[2] = 0x03;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[0] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[1] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[2] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[3] = 0x00;
|
||||
cfg->tx_lx_pre_driver_2[0] = 0x1C;
|
||||
cfg->tx_lx_pre_driver_2[1] = 0x1C;
|
||||
cfg->tx_lx_pre_driver_2[2] = 0x1C;
|
||||
cfg->tx_lx_pre_driver_2[3] = 0x00;
|
||||
cfg->tx_lx_res_code_offset[0] = 0x03;
|
||||
cfg->tx_lx_res_code_offset[1] = 0x00;
|
||||
cfg->tx_lx_res_code_offset[2] = 0x00;
|
||||
cfg->tx_lx_res_code_offset[3] = 0x03;
|
||||
} else if (bclk > HDMI_DIG_FREQ_BIT_CLK_THRESHOLD) {
|
||||
cfg->tx_lx_tx_drv_lvl[0] = 0x0f;
|
||||
cfg->tx_lx_tx_drv_lvl[1] = 0x0f;
|
||||
cfg->tx_lx_tx_drv_lvl[2] = 0x0f;
|
||||
cfg->tx_lx_tx_drv_lvl[3] = 0x0f;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[0] = 0x03;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[1] = 0x03;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[2] = 0x03;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[0] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[1] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[2] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[3] = 0x00;
|
||||
cfg->tx_lx_pre_driver_2[0] = 0x16;
|
||||
cfg->tx_lx_pre_driver_2[1] = 0x16;
|
||||
cfg->tx_lx_pre_driver_2[2] = 0x16;
|
||||
cfg->tx_lx_pre_driver_2[3] = 0x18;
|
||||
cfg->tx_lx_res_code_offset[0] = 0x03;
|
||||
cfg->tx_lx_res_code_offset[1] = 0x00;
|
||||
cfg->tx_lx_res_code_offset[2] = 0x00;
|
||||
cfg->tx_lx_res_code_offset[3] = 0x00;
|
||||
} else if (bclk > HDMI_MID_FREQ_BIT_CLK_THRESHOLD) {
|
||||
cfg->tx_lx_tx_drv_lvl[0] = 0x0f;
|
||||
cfg->tx_lx_tx_drv_lvl[1] = 0x0f;
|
||||
cfg->tx_lx_tx_drv_lvl[2] = 0x0f;
|
||||
cfg->tx_lx_tx_drv_lvl[3] = 0x0f;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[0] = 0x05;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[1] = 0x05;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[2] = 0x05;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[0] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[1] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[2] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[3] = 0x00;
|
||||
cfg->tx_lx_pre_driver_2[0] = 0x0E;
|
||||
cfg->tx_lx_pre_driver_2[1] = 0x0E;
|
||||
cfg->tx_lx_pre_driver_2[2] = 0x0E;
|
||||
cfg->tx_lx_pre_driver_2[3] = 0x0E;
|
||||
cfg->tx_lx_res_code_offset[0] = 0x00;
|
||||
cfg->tx_lx_res_code_offset[1] = 0x00;
|
||||
cfg->tx_lx_res_code_offset[2] = 0x00;
|
||||
cfg->tx_lx_res_code_offset[3] = 0x00;
|
||||
} else {
|
||||
cfg->tx_lx_tx_drv_lvl[0] = 0x01;
|
||||
cfg->tx_lx_tx_drv_lvl[1] = 0x01;
|
||||
cfg->tx_lx_tx_drv_lvl[2] = 0x01;
|
||||
cfg->tx_lx_tx_drv_lvl[3] = 0x00;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[0] = 0x00;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[1] = 0x00;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[2] = 0x00;
|
||||
cfg->tx_lx_tx_emp_post1_lvl[3] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[0] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[1] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[2] = 0x00;
|
||||
cfg->tx_lx_pre_driver_1[3] = 0x00;
|
||||
cfg->tx_lx_pre_driver_2[0] = 0x16;
|
||||
cfg->tx_lx_pre_driver_2[1] = 0x16;
|
||||
cfg->tx_lx_pre_driver_2[2] = 0x16;
|
||||
cfg->tx_lx_pre_driver_2[3] = 0x18;
|
||||
cfg->tx_lx_res_code_offset[0] = 0x00;
|
||||
cfg->tx_lx_res_code_offset[1] = 0x00;
|
||||
cfg->tx_lx_res_code_offset[2] = 0x00;
|
||||
cfg->tx_lx_res_code_offset[3] = 0x00;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmi_8998_pll_set_clk_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
|
||||
struct hdmi_phy *phy = pll_get_phy(pll);
|
||||
struct hdmi_8998_phy_pll_reg_cfg cfg = {};
|
||||
int i, ret;
|
||||
|
||||
ret = pll_calculate(rate, parent_rate, &cfg);
|
||||
if (ret) {
|
||||
DRM_ERROR("PLL calculation failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Initially shut down PHY */
|
||||
hdmi_phy_write(phy, REG_HDMI_8998_PHY_PD_CTL, 0x0);
|
||||
udelay(500);
|
||||
|
||||
/* Power up sequence */
|
||||
hdmi_phy_write(phy, REG_HDMI_8998_PHY_PD_CTL, 0x1);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_RESETSM_CNTRL, 0x20);
|
||||
hdmi_phy_write(phy, REG_HDMI_8998_PHY_CMN_CTRL, 0x6);
|
||||
|
||||
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
|
||||
hdmi_tx_chan_write(pll, i,
|
||||
REG_HDMI_8998_PHY_TXn_INTERFACE_SELECT_TX_BAND,
|
||||
cfg.tx_lx_tx_band[i]);
|
||||
hdmi_tx_chan_write(pll, i,
|
||||
REG_HDMI_8998_PHY_TXn_CLKBUF_TERM_ENABLE,
|
||||
0x1);
|
||||
hdmi_tx_chan_write(pll, i,
|
||||
REG_HDMI_8998_PHY_TXn_LANE_MODE,
|
||||
0x20);
|
||||
}
|
||||
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE, 0x02);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x0B);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SYSCLK_EN_SEL, 0x37);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SYS_CLK_CTRL, 0x02);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CLK_ENABLE1, 0x0E);
|
||||
|
||||
/* Bypass VCO calibration */
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_SVS_MODE_CLK_SEL,
|
||||
cfg.com_svs_mode_clk_sel);
|
||||
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_IVCO, 0x07);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_VCO_TUNE_CTRL, 0x00);
|
||||
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CLK_SEL, 0x30);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_HSCLK_SEL,
|
||||
cfg.com_hsclk_sel);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP_EN,
|
||||
cfg.com_lock_cmp_en);
|
||||
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_CCTRL_MODE0,
|
||||
cfg.com_pll_cctrl_mode0);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_PLL_RCTRL_MODE0,
|
||||
cfg.com_pll_rctrl_mode0);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CP_CTRL_MODE0,
|
||||
cfg.com_cp_ctrl_mode0);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DEC_START_MODE0,
|
||||
cfg.com_dec_start_mode0);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0,
|
||||
cfg.com_div_frac_start1_mode0);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0,
|
||||
cfg.com_div_frac_start2_mode0);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0,
|
||||
cfg.com_div_frac_start3_mode0);
|
||||
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0,
|
||||
cfg.com_integloop_gain0_mode0);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0,
|
||||
cfg.com_integloop_gain1_mode0);
|
||||
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP1_MODE0,
|
||||
cfg.com_lock_cmp1_mode0);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP2_MODE0,
|
||||
cfg.com_lock_cmp2_mode0);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_LOCK_CMP3_MODE0,
|
||||
cfg.com_lock_cmp3_mode0);
|
||||
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_VCO_TUNE_MAP, 0x00);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CORE_CLK_EN,
|
||||
cfg.com_core_clk_en);
|
||||
hdmi_pll_write(pll, REG_HDMI_8998_PHY_QSERDES_COM_CORECLK_DIV_MODE0,
|
||||
cfg.com_coreclk_div_mode0);
|
||||
|
||||
/* TX lanes setup (TX 0/1/2/3) */
|
||||
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
|
||||
hdmi_tx_chan_write(pll, i,
|
||||
REG_HDMI_8998_PHY_TXn_DRV_LVL,
|
||||
cfg.tx_lx_tx_drv_lvl[i]);
|
||||
hdmi_tx_chan_write(pll, i,
|
||||
REG_HDMI_8998_PHY_TXn_EMP_POST1_LVL,
|
||||
cfg.tx_lx_tx_emp_post1_lvl[i]);
|
||||
hdmi_tx_chan_write(pll, i,
|
||||
REG_HDMI_8998_PHY_TXn_PRE_DRIVER_1,
|
||||
cfg.tx_lx_pre_driver_1[i]);
|
||||
hdmi_tx_chan_write(pll, i,
|
||||
REG_HDMI_8998_PHY_TXn_PRE_DRIVER_2,
|
||||
cfg.tx_lx_pre_driver_2[i]);
|
||||
hdmi_tx_chan_write(pll, i,
|
||||
REG_HDMI_8998_PHY_TXn_DRV_LVL_RES_CODE_OFFSET,
|
||||
cfg.tx_lx_res_code_offset[i]);
|
||||
}
|
||||
|
||||
hdmi_phy_write(phy, REG_HDMI_8998_PHY_MODE, cfg.phy_mode);
|
||||
|
||||
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
|
||||
hdmi_tx_chan_write(pll, i,
|
||||
REG_HDMI_8998_PHY_TXn_LANE_CONFIG,
|
||||
0x10);
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure that vco configuration gets flushed to hardware before
|
||||
* enabling the PLL
|
||||
*/
|
||||
wmb();
|
||||
|
||||
pll->rate = rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hdmi_8998_phy_ready_status(struct hdmi_phy *phy)
|
||||
{
|
||||
u32 nb_tries = HDMI_PLL_POLL_MAX_READS;
|
||||
unsigned long timeout = HDMI_PLL_POLL_TIMEOUT_US;
|
||||
u32 status;
|
||||
int phy_ready = 0;
|
||||
|
||||
while (nb_tries--) {
|
||||
status = hdmi_phy_read(phy, REG_HDMI_8998_PHY_STATUS);
|
||||
phy_ready = status & BIT(0);
|
||||
|
||||
if (phy_ready)
|
||||
break;
|
||||
|
||||
udelay(timeout);
|
||||
}
|
||||
|
||||
return phy_ready;
|
||||
}
|
||||
|
||||
static int hdmi_8998_pll_lock_status(struct hdmi_pll_8998 *pll)
|
||||
{
|
||||
u32 status;
|
||||
int nb_tries = HDMI_PLL_POLL_MAX_READS;
|
||||
unsigned long timeout = HDMI_PLL_POLL_TIMEOUT_US;
|
||||
int pll_locked = 0;
|
||||
|
||||
while (nb_tries--) {
|
||||
status = hdmi_pll_read(pll,
|
||||
REG_HDMI_8998_PHY_QSERDES_COM_C_READY_STATUS);
|
||||
pll_locked = status & BIT(0);
|
||||
|
||||
if (pll_locked)
|
||||
break;
|
||||
|
||||
udelay(timeout);
|
||||
}
|
||||
|
||||
return pll_locked;
|
||||
}
|
||||
|
||||
static int hdmi_8998_pll_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
|
||||
struct hdmi_phy *phy = pll_get_phy(pll);
|
||||
int i, ret = 0;
|
||||
|
||||
hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x1);
|
||||
udelay(100);
|
||||
|
||||
hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x59);
|
||||
udelay(100);
|
||||
|
||||
ret = hdmi_8998_pll_lock_status(pll);
|
||||
if (!ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
|
||||
hdmi_tx_chan_write(pll, i,
|
||||
REG_HDMI_8998_PHY_TXn_LANE_CONFIG, 0x1F);
|
||||
}
|
||||
|
||||
/* Ensure all registers are flushed to hardware */
|
||||
wmb();
|
||||
|
||||
ret = hdmi_8998_phy_ready_status(phy);
|
||||
if (!ret)
|
||||
return ret;
|
||||
|
||||
/* Restart the retiming buffer */
|
||||
hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x58);
|
||||
udelay(1);
|
||||
hdmi_phy_write(phy, REG_HDMI_8998_PHY_CFG, 0x59);
|
||||
|
||||
/* Ensure all registers are flushed to hardware */
|
||||
wmb();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long hdmi_8998_pll_round_rate(struct clk_hw *hw,
|
||||
unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
if (rate < HDMI_PCLK_MIN_FREQ)
|
||||
return HDMI_PCLK_MIN_FREQ;
|
||||
else if (rate > HDMI_PCLK_MAX_FREQ)
|
||||
return HDMI_PCLK_MAX_FREQ;
|
||||
else
|
||||
return rate;
|
||||
}
|
||||
|
||||
static unsigned long hdmi_8998_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
|
||||
return pll->rate;
|
||||
}
|
||||
|
||||
static void hdmi_8998_pll_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
|
||||
struct hdmi_phy *phy = pll_get_phy(pll);
|
||||
|
||||
hdmi_phy_write(phy, REG_HDMI_8998_PHY_PD_CTL, 0);
|
||||
usleep_range(100, 150);
|
||||
}
|
||||
|
||||
static int hdmi_8998_pll_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct hdmi_pll_8998 *pll = hw_clk_to_pll(hw);
|
||||
u32 status;
|
||||
int pll_locked;
|
||||
|
||||
status = hdmi_pll_read(pll, REG_HDMI_8998_PHY_QSERDES_COM_C_READY_STATUS);
|
||||
pll_locked = status & BIT(0);
|
||||
|
||||
return pll_locked;
|
||||
}
|
||||
|
||||
static const struct clk_ops hdmi_8998_pll_ops = {
|
||||
.set_rate = hdmi_8998_pll_set_clk_rate,
|
||||
.round_rate = hdmi_8998_pll_round_rate,
|
||||
.recalc_rate = hdmi_8998_pll_recalc_rate,
|
||||
.prepare = hdmi_8998_pll_prepare,
|
||||
.unprepare = hdmi_8998_pll_unprepare,
|
||||
.is_enabled = hdmi_8998_pll_is_enabled,
|
||||
};
|
||||
|
||||
static const struct clk_init_data pll_init = {
|
||||
.name = "hdmipll",
|
||||
.ops = &hdmi_8998_pll_ops,
|
||||
.parent_data = (const struct clk_parent_data[]){
|
||||
{ .fw_name = "xo", .name = "xo_board" },
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_IGNORE_UNUSED,
|
||||
};
|
||||
|
||||
int msm_hdmi_pll_8998_init(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct hdmi_pll_8998 *pll;
|
||||
int ret, i;
|
||||
|
||||
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll)
|
||||
return -ENOMEM;
|
||||
|
||||
pll->pdev = pdev;
|
||||
|
||||
pll->mmio_qserdes_com = msm_ioremap(pdev, "hdmi_pll");
|
||||
if (IS_ERR(pll->mmio_qserdes_com)) {
|
||||
DRM_DEV_ERROR(dev, "failed to map pll base\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
|
||||
char name[32];
|
||||
|
||||
snprintf(name, sizeof(name), "hdmi_tx_l%d", i);
|
||||
|
||||
pll->mmio_qserdes_tx[i] = msm_ioremap(pdev, name);
|
||||
if (IS_ERR(pll->mmio_qserdes_tx[i])) {
|
||||
DRM_DEV_ERROR(dev, "failed to map pll base\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
}
|
||||
pll->clk_hw.init = &pll_init;
|
||||
|
||||
ret = devm_clk_hw_register(dev, &pll->clk_hw);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(dev, "failed to register pll clock\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &pll->clk_hw);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(dev, "failed to register clk provider: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char * const hdmi_phy_8998_reg_names[] = {
|
||||
"vddio",
|
||||
"vcca",
|
||||
};
|
||||
|
||||
static const char * const hdmi_phy_8998_clk_names[] = {
|
||||
"iface", "ref", "xo",
|
||||
};
|
||||
|
||||
const struct hdmi_phy_cfg msm_hdmi_phy_8998_cfg = {
|
||||
.type = MSM_HDMI_PHY_8998,
|
||||
.reg_names = hdmi_phy_8998_reg_names,
|
||||
.num_regs = ARRAY_SIZE(hdmi_phy_8998_reg_names),
|
||||
.clk_names = hdmi_phy_8998_clk_names,
|
||||
.num_clks = ARRAY_SIZE(hdmi_phy_8998_clk_names),
|
||||
};
|
||||
|
|
@ -1012,4 +1012,93 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
|
|||
<reg32 offset="0x00110" name="TX_ALOG_INTF_OBSV"/>
|
||||
</domain>
|
||||
|
||||
<domain name="HDMI_8998_PHY" width="32">
|
||||
<reg32 offset="0x00000" name="CFG"/>
|
||||
<reg32 offset="0x00004" name="PD_CTL"/>
|
||||
<reg32 offset="0x00010" name="MODE"/>
|
||||
<reg32 offset="0x0005C" name="CLOCK"/>
|
||||
<reg32 offset="0x00068" name="CMN_CTRL"/>
|
||||
<reg32 offset="0x000B4" name="STATUS"/>
|
||||
</domain>
|
||||
|
||||
<domain name="HDMI_8998_PHY_QSERDES_COM" width="32">
|
||||
<reg32 offset="0x0000" name="ATB_SEL1"/>
|
||||
<reg32 offset="0x0004" name="ATB_SEL2"/>
|
||||
<reg32 offset="0x0008" name="FREQ_UPDATE"/>
|
||||
<reg32 offset="0x000C" name="BG_TIMER"/>
|
||||
<reg32 offset="0x0010" name="SSC_EN_CENTER"/>
|
||||
<reg32 offset="0x0014" name="SSC_ADJ_PER1"/>
|
||||
<reg32 offset="0x0018" name="SSC_ADJ_PER2"/>
|
||||
<reg32 offset="0x001C" name="SSC_PER1"/>
|
||||
<reg32 offset="0x0020" name="SSC_PER2"/>
|
||||
<reg32 offset="0x0024" name="SSC_STEP_SIZE1"/>
|
||||
<reg32 offset="0x0028" name="SSC_STEP_SIZE2"/>
|
||||
<reg32 offset="0x002C" name="POST_DIV"/>
|
||||
<reg32 offset="0x0030" name="POST_DIV_MUX"/>
|
||||
<reg32 offset="0x0034" name="BIAS_EN_CLKBUFLR_EN"/>
|
||||
<reg32 offset="0x0038" name="CLK_ENABLE1"/>
|
||||
<reg32 offset="0x003C" name="SYS_CLK_CTRL"/>
|
||||
<reg32 offset="0x0040" name="SYSCLK_BUF_ENABLE"/>
|
||||
<reg32 offset="0x0044" name="PLL_EN"/>
|
||||
<reg32 offset="0x0048" name="PLL_IVCO"/>
|
||||
<reg32 offset="0x004C" name="CMN_IETRIM"/>
|
||||
<reg32 offset="0x0050" name="CMN_IPTRIM"/>
|
||||
<reg32 offset="0x0060" name="CP_CTRL_MODE0"/>
|
||||
<reg32 offset="0x0064" name="CP_CTRL_MODE1"/>
|
||||
<reg32 offset="0x0068" name="PLL_RCTRL_MODE0"/>
|
||||
<reg32 offset="0x006C" name="PLL_RCTRL_MODE1"/>
|
||||
<reg32 offset="0x0070" name="PLL_CCTRL_MODE0"/>
|
||||
<reg32 offset="0x0074" name="PLL_CCTRL_MODE1"/>
|
||||
<reg32 offset="0x0078" name="PLL_CNTRL"/>
|
||||
<reg32 offset="0x007C" name="BIAS_EN_CTRL_BY_PSM"/>
|
||||
<reg32 offset="0x0080" name="SYSCLK_EN_SEL"/>
|
||||
<reg32 offset="0x0084" name="CML_SYSCLK_SEL"/>
|
||||
<reg32 offset="0x0088" name="RESETSM_CNTRL"/>
|
||||
<reg32 offset="0x008C" name="RESETSM_CNTRL2"/>
|
||||
<reg32 offset="0x0090" name="LOCK_CMP_EN"/>
|
||||
<reg32 offset="0x0094" name="LOCK_CMP_CFG"/>
|
||||
<reg32 offset="0x0098" name="LOCK_CMP1_MODE0"/>
|
||||
<reg32 offset="0x009C" name="LOCK_CMP2_MODE0"/>
|
||||
<reg32 offset="0x00A0" name="LOCK_CMP3_MODE0"/>
|
||||
<reg32 offset="0x00B0" name="DEC_START_MODE0"/>
|
||||
<reg32 offset="0x00B4" name="DEC_START_MODE1"/>
|
||||
<reg32 offset="0x00B8" name="DIV_FRAC_START1_MODE0"/>
|
||||
<reg32 offset="0x00BC" name="DIV_FRAC_START2_MODE0"/>
|
||||
<reg32 offset="0x00C0" name="DIV_FRAC_START3_MODE0"/>
|
||||
<reg32 offset="0x00C4" name="DIV_FRAC_START1_MODE1"/>
|
||||
<reg32 offset="0x00C8" name="DIV_FRAC_START2_MODE1"/>
|
||||
<reg32 offset="0x00CC" name="DIV_FRAC_START3_MODE1"/>
|
||||
<reg32 offset="0x00D0" name="INTEGLOOP_INITVAL"/>
|
||||
<reg32 offset="0x00D4" name="INTEGLOOP_EN"/>
|
||||
<reg32 offset="0x00D8" name="INTEGLOOP_GAIN0_MODE0"/>
|
||||
<reg32 offset="0x00DC" name="INTEGLOOP_GAIN1_MODE0"/>
|
||||
<reg32 offset="0x00E0" name="INTEGLOOP_GAIN0_MODE1"/>
|
||||
<reg32 offset="0x00E4" name="INTEGLOOP_GAIN1_MODE1"/>
|
||||
<reg32 offset="0x00E8" name="VCOCAL_DEADMAN_CTRL"/>
|
||||
<reg32 offset="0x00EC" name="VCO_TUNE_CTRL"/>
|
||||
<reg32 offset="0x00F0" name="VCO_TUNE_MAP"/>
|
||||
<reg32 offset="0x0124" name="CMN_STATUS"/>
|
||||
<reg32 offset="0x0128" name="RESET_SM_STATUS"/>
|
||||
<reg32 offset="0x0138" name="CLK_SEL"/>
|
||||
<reg32 offset="0x013C" name="HSCLK_SEL"/>
|
||||
<reg32 offset="0x0148" name="CORECLK_DIV_MODE0"/>
|
||||
<reg32 offset="0x0150" name="SW_RESET"/>
|
||||
<reg32 offset="0x0154" name="CORE_CLK_EN"/>
|
||||
<reg32 offset="0x0158" name="C_READY_STATUS"/>
|
||||
<reg32 offset="0x015C" name="CMN_CONFIG"/>
|
||||
<reg32 offset="0x0164" name="SVS_MODE_CLK_SEL"/>
|
||||
</domain>
|
||||
|
||||
<domain name="HDMI_8998_PHY_TXn" width="32">
|
||||
<reg32 offset="0x0000" name="EMP_POST1_LVL"/>
|
||||
<reg32 offset="0x0008" name="INTERFACE_SELECT_TX_BAND"/>
|
||||
<reg32 offset="0x000C" name="CLKBUF_TERM_ENABLE"/>
|
||||
<reg32 offset="0x0014" name="DRV_LVL_RES_CODE_OFFSET"/>
|
||||
<reg32 offset="0x0018" name="DRV_LVL"/>
|
||||
<reg32 offset="0x001C" name="LANE_CONFIG"/>
|
||||
<reg32 offset="0x0024" name="PRE_DRIVER_1"/>
|
||||
<reg32 offset="0x0028" name="PRE_DRIVER_2"/>
|
||||
<reg32 offset="0x002C" name="LANE_MODE"/>
|
||||
</domain>
|
||||
|
||||
</database>
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user