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x86/ioperm: Fix io bitmap invalidation on Xen PV
tss_invalidate_io_bitmap() wasn't wired up properly through the pvop
machinery, so the TSS and Xen's io bitmap would get out of sync
whenever disabling a valid io bitmap.
Add a new pvop for tss_invalidate_io_bitmap() to fix it.
This is XSA-329.
Fixes: 22fe5b0439
("x86/ioperm: Move TSS bitmap update to exit to user work")
Signed-off-by: Andy Lutomirski <luto@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/d53075590e1f91c19f8af705059d3ff99424c020.1595030016.git.luto@kernel.org
This commit is contained in:
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@ -19,12 +19,28 @@ struct task_struct;
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void io_bitmap_share(struct task_struct *tsk);
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void io_bitmap_exit(struct task_struct *tsk);
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static inline void native_tss_invalidate_io_bitmap(void)
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{
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/*
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* Invalidate the I/O bitmap by moving io_bitmap_base outside the
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* TSS limit so any subsequent I/O access from user space will
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* trigger a #GP.
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*
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* This is correct even when VMEXIT rewrites the TSS limit
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* to 0x67 as the only requirement is that the base points
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* outside the limit.
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*/
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this_cpu_write(cpu_tss_rw.x86_tss.io_bitmap_base,
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IO_BITMAP_OFFSET_INVALID);
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}
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void native_tss_update_io_bitmap(void);
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#ifdef CONFIG_PARAVIRT_XXL
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#include <asm/paravirt.h>
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#else
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#define tss_update_io_bitmap native_tss_update_io_bitmap
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#define tss_invalidate_io_bitmap native_tss_invalidate_io_bitmap
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#endif
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#else
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@ -302,6 +302,11 @@ static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
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}
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#ifdef CONFIG_X86_IOPL_IOPERM
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static inline void tss_invalidate_io_bitmap(void)
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{
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PVOP_VCALL0(cpu.invalidate_io_bitmap);
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}
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static inline void tss_update_io_bitmap(void)
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{
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PVOP_VCALL0(cpu.update_io_bitmap);
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@ -141,6 +141,7 @@ struct pv_cpu_ops {
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void (*load_sp0)(unsigned long sp0);
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#ifdef CONFIG_X86_IOPL_IOPERM
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void (*invalidate_io_bitmap)(void);
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void (*update_io_bitmap)(void);
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#endif
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@ -324,7 +324,8 @@ struct paravirt_patch_template pv_ops = {
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.cpu.swapgs = native_swapgs,
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#ifdef CONFIG_X86_IOPL_IOPERM
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.cpu.update_io_bitmap = native_tss_update_io_bitmap,
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.cpu.invalidate_io_bitmap = native_tss_invalidate_io_bitmap,
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.cpu.update_io_bitmap = native_tss_update_io_bitmap,
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#endif
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.cpu.start_context_switch = paravirt_nop,
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@ -322,20 +322,6 @@ void arch_setup_new_exec(void)
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}
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#ifdef CONFIG_X86_IOPL_IOPERM
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static inline void tss_invalidate_io_bitmap(struct tss_struct *tss)
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{
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/*
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* Invalidate the I/O bitmap by moving io_bitmap_base outside the
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* TSS limit so any subsequent I/O access from user space will
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* trigger a #GP.
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*
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* This is correct even when VMEXIT rewrites the TSS limit
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* to 0x67 as the only requirement is that the base points
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* outside the limit.
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*/
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tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
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}
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static inline void switch_to_bitmap(unsigned long tifp)
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{
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/*
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@ -346,7 +332,7 @@ static inline void switch_to_bitmap(unsigned long tifp)
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* user mode.
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*/
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if (tifp & _TIF_IO_BITMAP)
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tss_invalidate_io_bitmap(this_cpu_ptr(&cpu_tss_rw));
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tss_invalidate_io_bitmap();
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}
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static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
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@ -380,7 +366,7 @@ void native_tss_update_io_bitmap(void)
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u16 *base = &tss->x86_tss.io_bitmap_base;
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if (!test_thread_flag(TIF_IO_BITMAP)) {
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tss_invalidate_io_bitmap(tss);
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native_tss_invalidate_io_bitmap();
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return;
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}
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@ -870,6 +870,17 @@ static void xen_load_sp0(unsigned long sp0)
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}
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#ifdef CONFIG_X86_IOPL_IOPERM
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static void xen_invalidate_io_bitmap(void)
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{
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struct physdev_set_iobitmap iobitmap = {
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.bitmap = 0,
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.nr_ports = 0,
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};
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native_tss_invalidate_io_bitmap();
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HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap);
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}
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static void xen_update_io_bitmap(void)
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{
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struct physdev_set_iobitmap iobitmap;
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@ -1099,6 +1110,7 @@ static const struct pv_cpu_ops xen_cpu_ops __initconst = {
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.load_sp0 = xen_load_sp0,
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#ifdef CONFIG_X86_IOPL_IOPERM
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.invalidate_io_bitmap = xen_invalidate_io_bitmap,
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.update_io_bitmap = xen_update_io_bitmap,
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#endif
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.io_delay = xen_io_delay,
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