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EDAC/i10nm: Add support for high bandwidth memory
A future Xeon processor will include in-package HBM (high bandwidth memory). The in-package HBM memory controller shares the same architecture with the regular DDR memory controller. Add the HBM memory controller devices for EDAC support. Tested-by: Hongyu Ning <hongyu.ning@linux.intel.com> Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20210611170123.1057025-4-tony.luck@intel.com
This commit is contained in:
Qiuxu Zhuo
Tony Luck
parent
4bd4d32e9a
commit
c945088384
@ -13,7 +13,7 @@
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#include "edac_module.h"
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#include "skx_common.h"
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#define I10NM_REVISION "v0.0.4"
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#define I10NM_REVISION "v0.0.5"
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#define EDAC_MOD_STR "i10nm_edac"
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/* Debug macros */
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@ -26,19 +26,33 @@
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pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))
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#define I10NM_GET_SAD(d, offset, i, reg)\
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pci_read_config_dword((d)->sad_all, (offset) + (i) * 8, &(reg))
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#define I10NM_GET_HBM_IMC_BAR(d, reg) \
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pci_read_config_dword((d)->uracu, 0xd4, &(reg))
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#define I10NM_GET_CAPID3_CFG(d, reg) \
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pci_read_config_dword((d)->pcu_cr3, 0x90, &(reg))
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#define I10NM_GET_DIMMMTR(m, i, j) \
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readl((m)->mbase + 0x2080c + (i) * (m)->chan_mmio_sz + (j) * 4)
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readl((m)->mbase + ((m)->hbm_mc ? 0x80c : 0x2080c) + \
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(i) * (m)->chan_mmio_sz + (j) * 4)
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#define I10NM_GET_MCDDRTCFG(m, i, j) \
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readl((m)->mbase + 0x20970 + (i) * (m)->chan_mmio_sz + (j) * 4)
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readl((m)->mbase + ((m)->hbm_mc ? 0x970 : 0x20970) + \
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(i) * (m)->chan_mmio_sz + (j) * 4)
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#define I10NM_GET_MCMTR(m, i) \
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readl((m)->mbase + 0x20ef8 + (i) * (m)->chan_mmio_sz)
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readl((m)->mbase + ((m)->hbm_mc ? 0xef8 : 0x20ef8) + \
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(i) * (m)->chan_mmio_sz)
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#define I10NM_GET_AMAP(m, i) \
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readl((m)->mbase + 0x20814 + (i) * (m)->chan_mmio_sz)
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readl((m)->mbase + ((m)->hbm_mc ? 0x814 : 0x20814) + \
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(i) * (m)->chan_mmio_sz)
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#define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23)
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#define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12)
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#define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \
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GET_BITFIELD(reg, 0, 10) + 1) << 12)
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#define I10NM_GET_HBM_IMC_MMIO_OFFSET(reg) \
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((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000)
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#define I10NM_HBM_IMC_MMIO_SIZE 0x9000
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#define I10NM_IS_HBM_PRESENT(reg) GET_BITFIELD(reg, 27, 30)
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#define I10NM_IS_HBM_IMC(reg) GET_BITFIELD(reg, 29, 29)
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#define I10NM_MAX_SAD 16
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#define I10NM_SAD_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
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@ -94,7 +108,7 @@ static bool i10nm_check_2lm(struct res_config *cfg)
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return false;
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}
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static int i10nm_get_all_munits(void)
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static int i10nm_get_ddr_munits(void)
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{
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struct pci_dev *mdev;
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void __iomem *mbase;
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@ -122,7 +136,7 @@ static int i10nm_get_all_munits(void)
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edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n",
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j++, base, reg);
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for (i = 0; i < I10NM_NUM_IMC; i++) {
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for (i = 0; i < I10NM_NUM_DDR_IMC; i++) {
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mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
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12 + i, 0);
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if (i == 0 && !mdev) {
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@ -158,6 +172,90 @@ static int i10nm_get_all_munits(void)
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return 0;
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}
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static bool i10nm_check_hbm_imc(struct skx_dev *d)
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{
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u32 reg;
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if (I10NM_GET_CAPID3_CFG(d, reg)) {
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i10nm_printk(KERN_ERR, "Failed to get capid3_cfg\n");
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return false;
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}
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return I10NM_IS_HBM_PRESENT(reg) != 0;
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}
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static int i10nm_get_hbm_munits(void)
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{
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struct pci_dev *mdev;
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void __iomem *mbase;
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u32 reg, off, mcmtr;
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struct skx_dev *d;
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int i, lmc;
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u64 base;
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list_for_each_entry(d, i10nm_edac_list, list) {
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d->pcu_cr3 = pci_get_dev_wrapper(d->seg, d->bus[1], 30, 3);
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if (!d->pcu_cr3)
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return -ENODEV;
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if (!i10nm_check_hbm_imc(d)) {
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i10nm_printk(KERN_DEBUG, "No hbm memory\n");
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return -ENODEV;
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}
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if (I10NM_GET_SCK_BAR(d, reg)) {
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i10nm_printk(KERN_ERR, "Failed to get socket bar\n");
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return -ENODEV;
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}
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base = I10NM_GET_SCK_MMIO_BASE(reg);
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if (I10NM_GET_HBM_IMC_BAR(d, reg)) {
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i10nm_printk(KERN_ERR, "Failed to get hbm mc bar\n");
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return -ENODEV;
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}
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base += I10NM_GET_HBM_IMC_MMIO_OFFSET(reg);
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lmc = I10NM_NUM_DDR_IMC;
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for (i = 0; i < I10NM_NUM_HBM_IMC; i++) {
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mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
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12 + i / 4, 1 + i % 4);
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if (i == 0 && !mdev) {
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i10nm_printk(KERN_ERR, "No hbm mc found\n");
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return -ENODEV;
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}
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if (!mdev)
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continue;
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d->imc[lmc].mdev = mdev;
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off = i * I10NM_HBM_IMC_MMIO_SIZE;
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edac_dbg(2, "hbm mc%d mmio base 0x%llx size 0x%x\n",
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lmc, base + off, I10NM_HBM_IMC_MMIO_SIZE);
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mbase = ioremap(base + off, I10NM_HBM_IMC_MMIO_SIZE);
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if (!mbase) {
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i10nm_printk(KERN_ERR, "Failed to ioremap for hbm mc 0x%llx\n",
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base + off);
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return -ENOMEM;
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}
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d->imc[lmc].mbase = mbase;
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d->imc[lmc].hbm_mc = true;
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mcmtr = I10NM_GET_MCMTR(&d->imc[lmc], 0);
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if (!I10NM_IS_HBM_IMC(mcmtr)) {
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i10nm_printk(KERN_ERR, "This isn't an hbm mc!\n");
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return -ENODEV;
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}
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lmc++;
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}
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}
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return 0;
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}
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static struct res_config i10nm_cfg0 = {
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.type = I10NM,
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.decs_did = 0x3452,
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@ -181,6 +279,7 @@ static struct res_config spr_cfg = {
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.decs_did = 0x3252,
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.busno_cfg_offset = 0xd0,
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.ddr_chan_mmio_sz = 0x8000,
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.hbm_chan_mmio_sz = 0x4000,
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.support_ddr5 = true,
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.sad_all_devfn = PCI_DEVFN(10, 0),
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.sad_all_offset = 0x300,
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@ -216,13 +315,13 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
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struct dimm_info *dimm;
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int i, j, ndimms;
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for (i = 0; i < I10NM_NUM_CHANNELS; i++) {
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for (i = 0; i < imc->num_channels; i++) {
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if (!imc->mbase)
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continue;
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ndimms = 0;
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amap = I10NM_GET_AMAP(imc, i);
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for (j = 0; j < I10NM_NUM_DIMMS; j++) {
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for (j = 0; j < imc->num_dimms; j++) {
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dimm = edac_get_dimm(mci, i, j, 0);
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mtr = I10NM_GET_DIMMMTR(imc, i, j);
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mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i, j);
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@ -335,8 +434,9 @@ static int __init i10nm_init(void)
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skx_set_mem_cfg(i10nm_check_2lm(cfg));
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rc = i10nm_get_all_munits();
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if (rc < 0)
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rc = i10nm_get_ddr_munits();
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if (i10nm_get_hbm_munits() && rc)
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goto fail;
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list_for_each_entry(d, i10nm_edac_list, list) {
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@ -357,7 +457,15 @@ static int __init i10nm_init(void)
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d->imc[i].lmc = i;
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d->imc[i].src_id = src_id;
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d->imc[i].node_id = node_id;
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d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz;
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if (d->imc[i].hbm_mc) {
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d->imc[i].chan_mmio_sz = cfg->hbm_chan_mmio_sz;
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d->imc[i].num_channels = I10NM_NUM_HBM_CHANNELS;
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d->imc[i].num_dimms = I10NM_NUM_HBM_DIMMS;
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} else {
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d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz;
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d->imc[i].num_channels = I10NM_NUM_DDR_CHANNELS;
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d->imc[i].num_dimms = I10NM_NUM_DDR_DIMMS;
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}
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rc = skx_register_mci(&d->imc[i], d->imc[i].mdev,
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"Intel_10nm Socket", EDAC_MOD_STR,
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@ -343,9 +343,9 @@ int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
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ranks = numrank(mtr);
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rows = numrow(mtr);
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cols = numcol(mtr);
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cols = imc->hbm_mc ? 6 : numcol(mtr);
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if (cfg->support_ddr5 && (amap & 0x8)) {
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if (cfg->support_ddr5 && ((amap & 0x8) || imc->hbm_mc)) {
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banks = 32;
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mtype = MEM_DDR5;
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} else {
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@ -374,8 +374,13 @@ int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
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dimm->dtype = get_width(mtr);
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dimm->mtype = mtype;
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dimm->edac_mode = EDAC_SECDED; /* likely better than this */
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snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
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imc->src_id, imc->lmc, chan, dimmno);
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if (imc->hbm_mc)
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snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_HBMC#%u_Chan#%u",
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imc->src_id, imc->lmc, chan);
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else
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snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
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imc->src_id, imc->lmc, chan, dimmno);
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return 1;
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}
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@ -703,6 +708,8 @@ void skx_remove(void)
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}
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if (d->util_all)
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pci_dev_put(d->util_all);
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if (d->pcu_cr3)
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pci_dev_put(d->pcu_cr3);
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if (d->sad_all)
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pci_dev_put(d->sad_all);
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if (d->uracu)
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@ -32,9 +32,17 @@
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#define SKX_NUM_CHANNELS 3 /* Channels per memory controller */
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#define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */
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#define I10NM_NUM_IMC 4
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#define I10NM_NUM_CHANNELS 2
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#define I10NM_NUM_DIMMS 2
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#define I10NM_NUM_DDR_IMC 4
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#define I10NM_NUM_DDR_CHANNELS 2
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#define I10NM_NUM_DDR_DIMMS 2
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#define I10NM_NUM_HBM_IMC 16
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#define I10NM_NUM_HBM_CHANNELS 2
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#define I10NM_NUM_HBM_DIMMS 1
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#define I10NM_NUM_IMC (I10NM_NUM_DDR_IMC + I10NM_NUM_HBM_IMC)
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#define I10NM_NUM_CHANNELS MAX(I10NM_NUM_DDR_CHANNELS, I10NM_NUM_HBM_CHANNELS)
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#define I10NM_NUM_DIMMS MAX(I10NM_NUM_DDR_DIMMS, I10NM_NUM_HBM_DIMMS)
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#define MAX(a, b) ((a) > (b) ? (a) : (b))
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#define NUM_IMC MAX(SKX_NUM_IMC, I10NM_NUM_IMC)
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@ -56,12 +64,16 @@ struct skx_dev {
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struct pci_dev *sad_all;
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struct pci_dev *util_all;
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struct pci_dev *uracu; /* for i10nm CPU */
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struct pci_dev *pcu_cr3; /* for HBM memory detection */
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u32 mcroute;
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struct skx_imc {
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struct mem_ctl_info *mci;
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struct pci_dev *mdev; /* for i10nm CPU */
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void __iomem *mbase; /* for i10nm CPU */
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int chan_mmio_sz; /* for i10nm CPU */
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int num_channels; /* channels per memory controller */
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int num_dimms; /* dimms per channel */
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bool hbm_mc;
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u8 mc; /* system wide mc# */
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u8 lmc; /* socket relative mc# */
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u8 src_id, node_id;
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@ -132,6 +144,8 @@ struct res_config {
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int busno_cfg_offset;
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/* Per DDR channel memory-mapped I/O size */
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int ddr_chan_mmio_sz;
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/* Per HBM channel memory-mapped I/O size */
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int hbm_chan_mmio_sz;
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bool support_ddr5;
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/* SAD device number and function number */
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unsigned int sad_all_devfn;
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