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ASoC: nau8825: Add FLL configuration
snd_soc_codec_driver.set_pll is implemented to configure the FLL. The codec internal SYSCLK can be from either the MCLK pin directly, or the FLL. This is configured by snd_soc_codec_driver.set_pll. Signed-off-by: Ben Zhang <benzh@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Ben Zhang
Mark Brown
parent
b3681308cc
commit
c86ba612bd
@ -17,6 +17,7 @@
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/acpi.h>
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#include <linux/math64.h>
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#include <sound/initval.h>
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#include <sound/tlv.h>
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@ -29,6 +30,58 @@
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#include "nau8825.h"
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#define NAU_FREF_MAX 13500000
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#define NAU_FVCO_MAX 100000000
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#define NAU_FVCO_MIN 90000000
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struct nau8825_fll {
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int mclk_src;
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int ratio;
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int fll_frac;
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int fll_int;
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int clk_ref_div;
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};
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struct nau8825_fll_attr {
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unsigned int param;
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unsigned int val;
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};
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/* scaling for mclk from sysclk_src output */
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static const struct nau8825_fll_attr mclk_src_scaling[] = {
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{ 1, 0x0 },
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{ 2, 0x2 },
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{ 4, 0x3 },
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{ 8, 0x4 },
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{ 16, 0x5 },
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{ 32, 0x6 },
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{ 3, 0x7 },
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{ 6, 0xa },
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{ 12, 0xb },
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{ 24, 0xc },
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{ 48, 0xd },
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{ 96, 0xe },
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{ 5, 0xf },
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};
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/* ratio for input clk freq */
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static const struct nau8825_fll_attr fll_ratio[] = {
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{ 512000, 0x01 },
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{ 256000, 0x02 },
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{ 128000, 0x04 },
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{ 64000, 0x08 },
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{ 32000, 0x10 },
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{ 8000, 0x20 },
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{ 4000, 0x40 },
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};
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static const struct nau8825_fll_attr fll_pre_scalar[] = {
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{ 1, 0x0 },
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{ 2, 0x1 },
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{ 4, 0x2 },
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{ 8, 0x3 },
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};
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static const struct reg_default nau8825_reg_defaults[] = {
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{ NAU8825_REG_ENA_CTRL, 0x00ff },
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{ NAU8825_REG_CLK_DIVIDER, 0x0050 },
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@ -808,6 +861,115 @@ static int nau8825_codec_probe(struct snd_soc_codec *codec)
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return 0;
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}
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/**
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* nau8825_calc_fll_param - Calculate FLL parameters.
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* @fll_in: external clock provided to codec.
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* @fs: sampling rate.
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* @fll_param: Pointer to structure of FLL parameters.
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*
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* Calculate FLL parameters to configure codec.
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*
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* Returns 0 for success or negative error code.
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*/
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static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
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struct nau8825_fll *fll_param)
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{
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u64 fvco;
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unsigned int fref, i;
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/* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
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* freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
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* FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
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*/
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for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
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fref = fll_in / fll_pre_scalar[i].param;
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if (fref <= NAU_FREF_MAX)
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break;
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}
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if (i == ARRAY_SIZE(fll_pre_scalar))
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return -EINVAL;
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fll_param->clk_ref_div = fll_pre_scalar[i].val;
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/* Choose the FLL ratio based on FREF */
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for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
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if (fref >= fll_ratio[i].param)
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break;
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}
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if (i == ARRAY_SIZE(fll_ratio))
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return -EINVAL;
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fll_param->ratio = fll_ratio[i].val;
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/* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
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* FDCO must be within the 90MHz - 100MHz or the FFL cannot be
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* guaranteed across the full range of operation.
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* FDCO = freq_out * 2 * mclk_src_scaling
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*/
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for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
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fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
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if (NAU_FVCO_MIN < fvco && fvco < NAU_FVCO_MAX)
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break;
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}
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if (i == ARRAY_SIZE(mclk_src_scaling))
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return -EINVAL;
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fll_param->mclk_src = mclk_src_scaling[i].val;
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/* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
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* input based on FDCO, FREF and FLL ratio.
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*/
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fvco = div_u64(fvco << 16, fref * fll_param->ratio);
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fll_param->fll_int = (fvco >> 16) & 0x3FF;
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fll_param->fll_frac = fvco & 0xFFFF;
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return 0;
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}
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static void nau8825_fll_apply(struct nau8825 *nau8825,
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struct nau8825_fll *fll_param)
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{
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regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
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NAU8825_CLK_MCLK_SRC_MASK, fll_param->mclk_src);
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regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
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NAU8825_FLL_RATIO_MASK, fll_param->ratio);
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/* FLL 16-bit fractional input */
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regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
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/* FLL 10-bit integer input */
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regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
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NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
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/* FLL pre-scaler */
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regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
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NAU8825_FLL_REF_DIV_MASK, fll_param->clk_ref_div);
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/* select divided VCO input */
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regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
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NAU8825_FLL_FILTER_SW_MASK, 0x0000);
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/* FLL sigma delta modulator enable */
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regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
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NAU8825_SDM_EN_MASK, NAU8825_SDM_EN);
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}
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/* freq_out must be 256*Fs in order to achieve the best performance */
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static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
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unsigned int freq_in, unsigned int freq_out)
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{
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struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
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struct nau8825_fll fll_param;
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int ret, fs;
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fs = freq_out / 256;
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ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
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if (ret < 0) {
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dev_err(codec->dev, "Unsupported input clock %d\n", freq_in);
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return ret;
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}
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dev_dbg(codec->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
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fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
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fll_param.fll_int, fll_param.clk_ref_div);
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nau8825_fll_apply(nau8825, &fll_param);
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mdelay(2);
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regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
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NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
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return 0;
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}
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static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
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unsigned int freq)
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{
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@ -920,6 +1082,7 @@ static int nau8825_set_bias_level(struct snd_soc_codec *codec,
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static struct snd_soc_codec_driver nau8825_codec_driver = {
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.probe = nau8825_codec_probe,
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.set_sysclk = nau8825_set_sysclk,
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.set_pll = nau8825_set_pll,
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.set_bias_level = nau8825_set_bias_level,
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.suspend_bias_off = true,
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@ -101,13 +101,31 @@
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#define NAU8825_ENABLE_SAR_SFT 1
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/* CLK_DIVIDER (0x3) */
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#define NAU8825_CLK_SRC_SFT 15
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#define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT)
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#define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT)
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#define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT)
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#define NAU8825_CLK_SRC_SFT 15
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#define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT)
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#define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT)
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#define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT)
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#define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0)
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/* FLL1 (0x04) */
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#define NAU8825_FLL_RATIO_MASK (0x7f << 0)
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/* FLL3 (0x06) */
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#define NAU8825_FLL_INTEGER_MASK (0x3ff << 0)
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/* FLL4 (0x07) */
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#define NAU8825_FLL_REF_DIV_MASK (0x3 << 10)
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/* FLL5 (0x08) */
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#define NAU8825_FLL_FILTER_SW_MASK (0x1 << 14)
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/* FLL6 (0x9) */
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#define NAU8825_DCO_EN (1 << 15)
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#define NAU8825_DCO_EN_MASK (0x1 << 15)
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#define NAU8825_DCO_EN (0x1 << 15)
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#define NAU8825_DCO_DIS (0x0 << 15)
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#define NAU8825_SDM_EN_MASK (0x1 << 14)
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#define NAU8825_SDM_EN (0x1 << 14)
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#define NAU8825_SDM_DIS (0x0 << 14)
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/* HSD_CTRL (0xc) */
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#define NAU8825_HSD_AUTO_MODE (1 << 6)
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