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remoteproc: mss: q6v5-mss: Add modem support on SC7280
Add out of reset sequence support for modem sub-system on SC7280 SoCs. It requires access to an additional set of qaccept registers, external power/clk control registers and halt vq6 register to put the modem back into reset. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1631886935-14691-6-git-send-email-sibis@codeaurora.org
This commit is contained in:
Sibi Sankar
Bjorn Andersson
parent
c42c0a5e97
commit
c842379d00
@ -77,6 +77,14 @@
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#define HALT_ACK_TIMEOUT_US 100000
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/* QACCEPT Register Offsets */
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#define QACCEPT_ACCEPT_REG 0x0
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#define QACCEPT_ACTIVE_REG 0x4
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#define QACCEPT_DENY_REG 0x8
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#define QACCEPT_REQ_REG 0xC
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#define QACCEPT_TIMEOUT_US 50
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/* QDSP6SS_RESET */
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#define Q6SS_STOP_CORE BIT(0)
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#define Q6SS_CORE_ARES BIT(1)
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@ -143,6 +151,9 @@ struct rproc_hexagon_res {
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bool has_alt_reset;
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bool has_mba_logs;
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bool has_spare_reg;
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bool has_qaccept_regs;
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bool has_ext_cntl_regs;
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bool has_vq6;
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};
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struct q6v5 {
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@ -158,8 +169,18 @@ struct q6v5 {
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u32 halt_q6;
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u32 halt_modem;
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u32 halt_nc;
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u32 halt_vq6;
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u32 conn_box;
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u32 qaccept_mdm;
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u32 qaccept_cx;
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u32 qaccept_axi;
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u32 axim1_clk_off;
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u32 crypto_clk_off;
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u32 force_clk_on;
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u32 rscc_disable;
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struct reset_control *mss_restart;
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struct reset_control *pdc_reset;
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@ -201,6 +222,9 @@ struct q6v5 {
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bool has_alt_reset;
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bool has_mba_logs;
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bool has_spare_reg;
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bool has_qaccept_regs;
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bool has_ext_cntl_regs;
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bool has_vq6;
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int mpss_perm;
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int mba_perm;
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const char *hexagon_mdt_image;
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@ -213,6 +237,7 @@ enum {
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MSS_MSM8996,
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MSS_MSM8998,
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MSS_SC7180,
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MSS_SC7280,
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MSS_SDM845,
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};
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@ -473,6 +498,12 @@ static int q6v5_reset_assert(struct q6v5 *qproc)
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regmap_update_bits(qproc->conn_map, qproc->conn_box,
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AXI_GATING_VALID_OVERRIDE, 0);
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ret = reset_control_deassert(qproc->mss_restart);
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} else if (qproc->has_ext_cntl_regs) {
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regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
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reset_control_assert(qproc->pdc_reset);
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reset_control_assert(qproc->mss_restart);
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reset_control_deassert(qproc->pdc_reset);
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ret = reset_control_deassert(qproc->mss_restart);
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} else {
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ret = reset_control_assert(qproc->mss_restart);
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}
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@ -490,7 +521,7 @@ static int q6v5_reset_deassert(struct q6v5 *qproc)
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ret = reset_control_reset(qproc->mss_restart);
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writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
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reset_control_deassert(qproc->pdc_reset);
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} else if (qproc->has_spare_reg) {
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} else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
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ret = reset_control_reset(qproc->mss_restart);
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} else {
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ret = reset_control_deassert(qproc->mss_restart);
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@ -604,7 +635,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
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}
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goto pbl_wait;
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} else if (qproc->version == MSS_SC7180) {
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} else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) {
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val = readl(qproc->reg_base + QDSP6SS_SLEEP);
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val |= Q6SS_CBCR_CLKEN;
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writel(val, qproc->reg_base + QDSP6SS_SLEEP);
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@ -787,6 +818,89 @@ pbl_wait:
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return ret;
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}
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static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
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{
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unsigned int val;
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int ret;
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if (!qproc->has_qaccept_regs)
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return 0;
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if (qproc->has_ext_cntl_regs) {
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regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
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regmap_write(qproc->conn_map, qproc->force_clk_on, 1);
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ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
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!val, 1, Q6SS_CBCR_TIMEOUT_US);
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if (ret) {
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dev_err(qproc->dev, "failed to enable axim1 clock\n");
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return -ETIMEDOUT;
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}
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}
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regmap_write(map, offset + QACCEPT_REQ_REG, 1);
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/* Wait for accept */
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ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5,
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QACCEPT_TIMEOUT_US);
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if (ret) {
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dev_err(qproc->dev, "qchannel enable failed\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
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{
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int ret;
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unsigned int val, retry;
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unsigned int nretry = 10;
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bool takedown_complete = false;
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if (!qproc->has_qaccept_regs)
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return;
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while (!takedown_complete && nretry) {
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nretry--;
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/* Wait for active transactions to complete */
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regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5,
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QACCEPT_TIMEOUT_US);
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/* Request Q-channel transaction takedown */
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regmap_write(map, offset + QACCEPT_REQ_REG, 0);
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/*
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* If the request is denied, reset the Q-channel takedown request,
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* wait for active transactions to complete and retry takedown.
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*/
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retry = 10;
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while (retry) {
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usleep_range(5, 10);
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retry--;
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ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val);
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if (!ret && val) {
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regmap_write(map, offset + QACCEPT_REQ_REG, 1);
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break;
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}
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ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val);
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if (!ret && !val) {
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takedown_complete = true;
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break;
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}
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}
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if (!retry)
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break;
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}
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/* Rely on mss_restart to clear out pending transactions on takedown failure */
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if (!takedown_complete)
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dev_err(qproc->dev, "qchannel takedown failed\n");
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}
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static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
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struct regmap *halt_map,
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u32 offset)
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@ -950,6 +1064,12 @@ static int q6v5_mba_load(struct q6v5 *qproc)
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goto assert_reset;
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}
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ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
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if (ret) {
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dev_err(qproc->dev, "failed to enable axi bridge\n");
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goto disable_active_clks;
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}
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/*
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* Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
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* the Q6 access to this region.
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@ -996,8 +1116,13 @@ static int q6v5_mba_load(struct q6v5 *qproc)
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halt_axi_ports:
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
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if (qproc->has_vq6)
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
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q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
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q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
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q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
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mba_load_err = true;
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reclaim_mba:
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xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
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@ -1047,6 +1172,8 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
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qproc->dp_size = 0;
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
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if (qproc->has_vq6)
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
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if (qproc->version == MSS_MSM8996) {
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@ -1059,6 +1186,24 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
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writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
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}
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if (qproc->has_ext_cntl_regs) {
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regmap_write(qproc->conn_map, qproc->rscc_disable, 1);
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ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
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!val, 1, Q6SS_CBCR_TIMEOUT_US);
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if (ret)
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dev_err(qproc->dev, "failed to enable axim1 clock\n");
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ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val,
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!val, 1, Q6SS_CBCR_TIMEOUT_US);
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if (ret)
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dev_err(qproc->dev, "failed to enable crypto clock\n");
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}
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q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
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q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
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q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
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q6v5_reset_assert(qproc);
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q6v5_clk_disable(qproc->dev, qproc->reset_clks,
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@ -1471,6 +1616,7 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
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{
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struct of_phandle_args args;
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struct resource *res;
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int halt_cell_cnt = 3;
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int ret;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
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@ -1483,8 +1629,11 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
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if (IS_ERR(qproc->rmb_base))
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return PTR_ERR(qproc->rmb_base);
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if (qproc->has_vq6)
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halt_cell_cnt++;
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ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
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"qcom,halt-regs", 3, 0, &args);
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"qcom,halt-regs", halt_cell_cnt, 0, &args);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
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return -EINVAL;
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@ -1499,6 +1648,52 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
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qproc->halt_modem = args.args[1];
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qproc->halt_nc = args.args[2];
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if (qproc->has_vq6)
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qproc->halt_vq6 = args.args[3];
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if (qproc->has_qaccept_regs) {
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ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
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"qcom,qaccept-regs",
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3, 0, &args);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to parse qaccept-regs\n");
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return -EINVAL;
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}
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qproc->qaccept_mdm = args.args[0];
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qproc->qaccept_cx = args.args[1];
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qproc->qaccept_axi = args.args[2];
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}
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if (qproc->has_ext_cntl_regs) {
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ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
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"qcom,ext-regs",
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2, 0, &args);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to parse ext-regs index 0\n");
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return -EINVAL;
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}
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qproc->conn_map = syscon_node_to_regmap(args.np);
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of_node_put(args.np);
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if (IS_ERR(qproc->conn_map))
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return PTR_ERR(qproc->conn_map);
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qproc->force_clk_on = args.args[0];
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qproc->rscc_disable = args.args[1];
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ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
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"qcom,ext-regs",
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2, 1, &args);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to parse ext-regs index 1\n");
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return -EINVAL;
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}
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qproc->axim1_clk_off = args.args[0];
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qproc->crypto_clk_off = args.args[1];
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}
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if (qproc->has_spare_reg) {
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ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
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"qcom,spare-regs",
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@ -1590,7 +1785,7 @@ static int q6v5_init_reset(struct q6v5 *qproc)
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return PTR_ERR(qproc->mss_restart);
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}
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if (qproc->has_alt_reset || qproc->has_spare_reg) {
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if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
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qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
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"pdc_reset");
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if (IS_ERR(qproc->pdc_reset)) {
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@ -1697,6 +1892,9 @@ static int q6v5_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, qproc);
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qproc->has_qaccept_regs = desc->has_qaccept_regs;
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qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs;
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qproc->has_vq6 = desc->has_vq6;
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qproc->has_spare_reg = desc->has_spare_reg;
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ret = q6v5_init_mem(qproc, pdev);
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if (ret)
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@ -1857,9 +2055,40 @@ static const struct rproc_hexagon_res sc7180_mss = {
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.has_alt_reset = false,
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.has_mba_logs = true,
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.has_spare_reg = true,
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.has_qaccept_regs = false,
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.has_ext_cntl_regs = false,
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.has_vq6 = false,
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.version = MSS_SC7180,
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};
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static const struct rproc_hexagon_res sc7280_mss = {
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.hexagon_mba_image = "mba.mbn",
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.proxy_clk_names = (char*[]){
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"xo",
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"pka",
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NULL
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},
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.active_clk_names = (char*[]){
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"iface",
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"offline",
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"snoc_axi",
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NULL
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},
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.proxy_pd_names = (char*[]){
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"cx",
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"mss",
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NULL
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},
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.need_mem_protection = true,
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.has_alt_reset = false,
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.has_mba_logs = true,
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.has_spare_reg = false,
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.has_qaccept_regs = true,
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.has_ext_cntl_regs = true,
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.has_vq6 = true,
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.version = MSS_SC7280,
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};
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static const struct rproc_hexagon_res sdm845_mss = {
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.hexagon_mba_image = "mba.mbn",
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.proxy_clk_names = (char*[]){
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@ -1889,6 +2118,9 @@ static const struct rproc_hexagon_res sdm845_mss = {
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.has_alt_reset = true,
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.has_mba_logs = false,
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.has_spare_reg = false,
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.has_qaccept_regs = false,
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.has_ext_cntl_regs = false,
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.has_vq6 = false,
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.version = MSS_SDM845,
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};
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@ -1917,6 +2149,9 @@ static const struct rproc_hexagon_res msm8998_mss = {
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.has_alt_reset = false,
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.has_mba_logs = false,
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.has_spare_reg = false,
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.has_qaccept_regs = false,
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.has_ext_cntl_regs = false,
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.has_vq6 = false,
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.version = MSS_MSM8998,
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};
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@ -1948,6 +2183,9 @@ static const struct rproc_hexagon_res msm8996_mss = {
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.has_alt_reset = false,
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.has_mba_logs = false,
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.has_spare_reg = false,
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.has_qaccept_regs = false,
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||||
.has_ext_cntl_regs = false,
|
||||
.has_vq6 = false,
|
||||
.version = MSS_MSM8996,
|
||||
};
|
||||
|
||||
@ -1990,6 +2228,9 @@ static const struct rproc_hexagon_res msm8916_mss = {
|
||||
.has_alt_reset = false,
|
||||
.has_mba_logs = false,
|
||||
.has_spare_reg = false,
|
||||
.has_qaccept_regs = false,
|
||||
.has_ext_cntl_regs = false,
|
||||
.has_vq6 = false,
|
||||
.version = MSS_MSM8916,
|
||||
};
|
||||
|
||||
@ -2040,6 +2281,9 @@ static const struct rproc_hexagon_res msm8974_mss = {
|
||||
.has_alt_reset = false,
|
||||
.has_mba_logs = false,
|
||||
.has_spare_reg = false,
|
||||
.has_qaccept_regs = false,
|
||||
.has_ext_cntl_regs = false,
|
||||
.has_vq6 = false,
|
||||
.version = MSS_MSM8974,
|
||||
};
|
||||
|
||||
@ -2050,6 +2294,7 @@ static const struct of_device_id q6v5_of_match[] = {
|
||||
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
|
||||
{ .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
|
||||
{ .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
|
||||
{ .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
|
||||
{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
|
||||
{ },
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user