i2c: stm32f7: add SMBus-Alert support

Add support for the SMBus-Alert protocol to the STM32F7 that has
dedicated control and status logic.

If SMBus-Alert is used, the SMBALERT# pin must be configured as alternate
function for I2C Alert.

Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Reviewed-by: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Alain Volmat 2021-05-05 15:14:39 +02:00 committed by Wolfram Sang
parent 168290fb26
commit c8062d11e2

View File

@ -51,6 +51,7 @@
/* STM32F7 I2C control 1 */ /* STM32F7 I2C control 1 */
#define STM32F7_I2C_CR1_PECEN BIT(23) #define STM32F7_I2C_CR1_PECEN BIT(23)
#define STM32F7_I2C_CR1_ALERTEN BIT(22)
#define STM32F7_I2C_CR1_SMBHEN BIT(20) #define STM32F7_I2C_CR1_SMBHEN BIT(20)
#define STM32F7_I2C_CR1_WUPEN BIT(18) #define STM32F7_I2C_CR1_WUPEN BIT(18)
#define STM32F7_I2C_CR1_SBC BIT(16) #define STM32F7_I2C_CR1_SBC BIT(16)
@ -125,6 +126,7 @@
(((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17) (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
#define STM32F7_I2C_ISR_DIR BIT(16) #define STM32F7_I2C_ISR_DIR BIT(16)
#define STM32F7_I2C_ISR_BUSY BIT(15) #define STM32F7_I2C_ISR_BUSY BIT(15)
#define STM32F7_I2C_ISR_ALERT BIT(13)
#define STM32F7_I2C_ISR_PECERR BIT(11) #define STM32F7_I2C_ISR_PECERR BIT(11)
#define STM32F7_I2C_ISR_ARLO BIT(9) #define STM32F7_I2C_ISR_ARLO BIT(9)
#define STM32F7_I2C_ISR_BERR BIT(8) #define STM32F7_I2C_ISR_BERR BIT(8)
@ -138,6 +140,7 @@
#define STM32F7_I2C_ISR_TXE BIT(0) #define STM32F7_I2C_ISR_TXE BIT(0)
/* STM32F7 I2C Interrupt Clear */ /* STM32F7 I2C Interrupt Clear */
#define STM32F7_I2C_ICR_ALERTCF BIT(13)
#define STM32F7_I2C_ICR_PECCF BIT(11) #define STM32F7_I2C_ICR_PECCF BIT(11)
#define STM32F7_I2C_ICR_ARLOCF BIT(9) #define STM32F7_I2C_ICR_ARLOCF BIT(9)
#define STM32F7_I2C_ICR_BERRCF BIT(8) #define STM32F7_I2C_ICR_BERRCF BIT(8)
@ -278,6 +281,17 @@ struct stm32f7_i2c_msg {
u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4); u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
}; };
/**
* struct stm32f7_i2c_alert - SMBus alert specific data
* @setup: platform data for the smbus_alert i2c client
* @ara: I2C slave device used to respond to the SMBus Alert with Alert
* Response Address
*/
struct stm32f7_i2c_alert {
struct i2c_smbus_alert_setup setup;
struct i2c_client *ara;
};
/** /**
* struct stm32f7_i2c_dev - private data of the controller * struct stm32f7_i2c_dev - private data of the controller
* @adap: I2C adapter for this controller * @adap: I2C adapter for this controller
@ -310,6 +324,7 @@ struct stm32f7_i2c_msg {
* @analog_filter: boolean to indicate enabling of the analog filter * @analog_filter: boolean to indicate enabling of the analog filter
* @dnf_dt: value of digital filter requested via dt * @dnf_dt: value of digital filter requested via dt
* @dnf: value of digital filter to apply * @dnf: value of digital filter to apply
* @alert: SMBus alert specific data
*/ */
struct stm32f7_i2c_dev { struct stm32f7_i2c_dev {
struct i2c_adapter adap; struct i2c_adapter adap;
@ -341,6 +356,7 @@ struct stm32f7_i2c_dev {
bool analog_filter; bool analog_filter;
u32 dnf_dt; u32 dnf_dt;
u32 dnf; u32 dnf;
struct stm32f7_i2c_alert *alert;
}; };
/* /*
@ -1624,6 +1640,13 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
f7_msg->result = -EINVAL; f7_msg->result = -EINVAL;
} }
if (status & STM32F7_I2C_ISR_ALERT) {
dev_dbg(dev, "<%s>: SMBus alert received\n", __func__);
writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
i2c_handle_smbus_alert(i2c_dev->alert->ara);
return IRQ_HANDLED;
}
if (!i2c_dev->slave_running) { if (!i2c_dev->slave_running) {
u32 mask; u32 mask;
/* Disable interrupts */ /* Disable interrupts */
@ -1990,6 +2013,42 @@ static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
} }
} }
static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
{
struct stm32f7_i2c_alert *alert;
struct i2c_adapter *adap = &i2c_dev->adap;
struct device *dev = i2c_dev->dev;
void __iomem *base = i2c_dev->base;
alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
if (!alert)
return -ENOMEM;
alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup);
if (IS_ERR(alert->ara))
return PTR_ERR(alert->ara);
i2c_dev->alert = alert;
/* Enable SMBus Alert */
stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
return 0;
}
static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
{
struct stm32f7_i2c_alert *alert = i2c_dev->alert;
void __iomem *base = i2c_dev->base;
if (alert) {
/* Disable SMBus Alert */
stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
STM32F7_I2C_CR1_ALERTEN);
i2c_unregister_device(alert->ara);
}
}
static u32 stm32f7_i2c_func(struct i2c_adapter *adap) static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
{ {
struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap); struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
@ -2173,6 +2232,16 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)
} }
} }
if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) {
ret = stm32f7_i2c_enable_smbus_alert(i2c_dev);
if (ret) {
dev_err(i2c_dev->dev,
"failed to enable SMBus alert protocol (%d)\n",
ret);
goto i2c_disable_smbus_host;
}
}
dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
pm_runtime_mark_last_busy(i2c_dev->dev); pm_runtime_mark_last_busy(i2c_dev->dev);
@ -2180,6 +2249,9 @@ static int stm32f7_i2c_probe(struct platform_device *pdev)
return 0; return 0;
i2c_disable_smbus_host:
stm32f7_i2c_disable_smbus_host(i2c_dev);
i2c_adapter_remove: i2c_adapter_remove:
i2c_del_adapter(adap); i2c_del_adapter(adap);
@ -2214,6 +2286,7 @@ static int stm32f7_i2c_remove(struct platform_device *pdev)
{ {
struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
stm32f7_i2c_disable_smbus_alert(i2c_dev);
stm32f7_i2c_disable_smbus_host(i2c_dev); stm32f7_i2c_disable_smbus_host(i2c_dev);
i2c_del_adapter(&i2c_dev->adap); i2c_del_adapter(&i2c_dev->adap);