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clk: meson: meson8b: fix the naming of the APB clocks

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Fix a typo in the APB clock names by renaming them from "abp" to "apb".
No functional changes.

Fixes: a7d19b05ce ("clk: meson: meson8b: add the CPU clock post divider clocks")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190210222603.6404-2-martin.blumenstingl@googlemail.com
This commit is contained in:
Martin Blumenstingl 2019-02-10 23:26:03 +01:00 committed by Neil Armstrong
parent 40d08f774c
commit c5f09e6bd8
2 changed files with 14 additions and 14 deletions
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26
drivers/clk/meson/meson8b.c
View File

@ -804,16 +804,16 @@ static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
},
};
static u32 mux_table_abp[] = { 1, 2, 3, 4, 5, 6, 7 };
static struct clk_regmap meson8b_abp_clk_sel = {
static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
static struct clk_regmap meson8b_apb_clk_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.mask = 0x7,
.shift = 3,
.table = mux_table_abp,
.table = mux_table_apb,
},
.hw.init = &(struct clk_init_data){
.name = "abp_clk_sel",
.name = "apb_clk_sel",
.ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "cpu_clk_div2",
"cpu_clk_div3",
@ -826,16 +826,16 @@ static struct clk_regmap meson8b_abp_clk_sel = {
},
};
static struct clk_regmap meson8b_abp_clk_gate = {
static struct clk_regmap meson8b_apb_clk_gate = {
.data = &(struct clk_regmap_gate_data){
.offset = HHI_SYS_CPU_CLK_CNTL1,
.bit_idx = 16,
.flags = CLK_GATE_SET_TO_DISABLE,
},
.hw.init = &(struct clk_init_data){
.name = "abp_clk_dis",
.name = "apb_clk_dis",
.ops = &clk_regmap_gate_ro_ops,
.parent_names = (const char *[]){ "abp_clk_sel" },
.parent_names = (const char *[]){ "apb_clk_sel" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
@ -1911,8 +1911,8 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
[CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
[CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
[CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
[CLKID_ABP_SEL] = &meson8b_abp_clk_sel.hw,
[CLKID_ABP] = &meson8b_abp_clk_gate.hw,
[CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
[CLKID_APB] = &meson8b_apb_clk_gate.hw,
[CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
[CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
[CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
@ -2093,8 +2093,8 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
[CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
[CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
[CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
[CLKID_ABP_SEL] = &meson8b_abp_clk_sel.hw,
[CLKID_ABP] = &meson8b_abp_clk_gate.hw,
[CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
[CLKID_APB] = &meson8b_apb_clk_gate.hw,
[CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
[CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
[CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
@ -2262,8 +2262,8 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
&meson8b_fixed_pll_dco,
&meson8b_hdmi_pll_dco,
&meson8b_sys_pll_dco,
&meson8b_abp_clk_sel,
&meson8b_abp_clk_gate,
&meson8b_apb_clk_sel,
&meson8b_apb_clk_gate,
&meson8b_periph_clk_sel,
&meson8b_periph_clk_gate,
&meson8b_axi_clk_sel,

2
drivers/clk/meson/meson8b.h
View File

@ -92,7 +92,7 @@
#define CLKID_CPU_CLK_DIV6 120
#define CLKID_CPU_CLK_DIV7 121
#define CLKID_CPU_CLK_DIV8 122
#define CLKID_ABP_SEL 123
#define CLKID_APB_SEL 123
#define CLKID_PERIPH_SEL 125
#define CLKID_AXI_SEL 127
#define CLKID_L2_DRAM_SEL 129