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bus: ti-sysc: Add parsing of module capabilities
We need to configure the interconnect target module based on the device three configuration. Let's also add a new quirk for SYSC_QUIRK_RESET_STATUS to indicate that the SYSCONFIG reset bit changes after the reset is done. Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -39,6 +39,9 @@ enum sysc_clocks {
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static const char * const clock_names[] = { "fck", "ick", };
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#define SYSC_IDLEMODE_MASK 3
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#define SYSC_CLOCKACTIVITY_MASK 3
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/**
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* struct sysc - TI sysc interconnect target module registers and capabilities
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* @dev: struct device pointer
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@ -517,6 +520,91 @@ static int sysc_init_module(struct sysc *ddata)
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return 0;
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}
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static int sysc_init_sysc_mask(struct sysc *ddata)
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{
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struct device_node *np = ddata->dev->of_node;
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int error;
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u32 val;
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error = of_property_read_u32(np, "ti,sysc-mask", &val);
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if (error)
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return 0;
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if (val)
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ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
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else
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ddata->cfg.sysc_val = ddata->cap->sysc_mask;
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return 0;
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}
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static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
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const char *name)
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{
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struct device_node *np = ddata->dev->of_node;
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struct property *prop;
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const __be32 *p;
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u32 val;
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of_property_for_each_u32(np, name, prop, p, val) {
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if (val >= SYSC_NR_IDLEMODES) {
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dev_err(ddata->dev, "invalid idlemode: %i\n", val);
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return -EINVAL;
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}
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*idlemodes |= (1 << val);
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}
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return 0;
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}
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static int sysc_init_idlemodes(struct sysc *ddata)
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{
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int error;
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error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
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"ti,sysc-midle");
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if (error)
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return error;
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error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
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"ti,sysc-sidle");
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if (error)
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return error;
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return 0;
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}
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/*
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* Only some devices on omap4 and later have SYSCONFIG reset done
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* bit. We can detect this if there is no SYSSTATUS at all, or the
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* SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
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* have multiple bits for the child devices like OHCI and EHCI.
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* Depends on SYSC being parsed first.
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*/
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static int sysc_init_syss_mask(struct sysc *ddata)
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{
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struct device_node *np = ddata->dev->of_node;
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int error;
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u32 val;
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error = of_property_read_u32(np, "ti,syss-mask", &val);
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if (error) {
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if ((ddata->cap->type == TI_SYSC_OMAP4 ||
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ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
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(ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
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ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
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return 0;
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}
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if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
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ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
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ddata->cfg.syss_mask = val;
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return 0;
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}
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/* Device tree configured quirks */
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struct sysc_dts_quirk {
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const char *name;
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@ -820,6 +908,18 @@ static int sysc_probe(struct platform_device *pdev)
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if (error)
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goto unprepare;
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error = sysc_init_sysc_mask(ddata);
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if (error)
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goto unprepare;
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error = sysc_init_idlemodes(ddata);
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if (error)
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goto unprepare;
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error = sysc_init_syss_mask(ddata);
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if (error)
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goto unprepare;
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pm_runtime_enable(ddata->dev);
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error = sysc_init_module(ddata);
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@ -41,6 +41,7 @@ struct sysc_regbits {
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s8 emufree_shift;
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};
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#define SYSC_QUIRK_RESET_STATUS BIT(7)
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#define SYSC_QUIRK_NO_IDLE_ON_INIT BIT(6)
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#define SYSC_QUIRK_NO_RESET_ON_INIT BIT(5)
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#define SYSC_QUIRK_OPT_CLKS_NEEDED BIT(4)
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@ -49,6 +50,8 @@ struct sysc_regbits {
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#define SYSC_QUIRK_UNCACHED BIT(1)
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#define SYSC_QUIRK_USE_CLOCKACT BIT(0)
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#define SYSC_NR_IDLEMODES 4
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/**
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* struct sysc_capabilities - capabilities for an interconnect target module
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*
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@ -65,10 +68,17 @@ struct sysc_capabilities {
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/**
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* struct sysc_config - configuration for an interconnect target module
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* @sysc_val: configured value for sysc register
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* @midlemodes: bitmask of supported master idle modes
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* @sidlemodes: bitmask of supported master idle modes
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* @srst_udelay: optional delay needed after OCP soft reset
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* @quirks: bitmask of enabled quirks
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*/
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struct sysc_config {
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u32 sysc_val;
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u32 syss_mask;
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u8 midlemodes;
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u8 sidlemodes;
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u8 srst_udelay;
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u32 quirks;
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};
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