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habanalabs: use EQ MSI/X ID per chip
The Event Queue MSI/X ID is different per ASIC. This patch renames the current define to have the GOYA_ prefix to mark it only for Goya. It also moves it from the common armcp_if.h file to the ASIC specific goya_fw_if.h file. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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3110c60fdc
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c535bfdd0f
@ -2204,10 +2204,10 @@ static int goya_enable_msix(struct hl_device *hdev)
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}
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}
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}
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}
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irq = pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX);
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irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
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rc = request_irq(irq, hl_irq_handler_eq, 0,
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rc = request_irq(irq, hl_irq_handler_eq, 0,
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goya_irq_name[EVENT_QUEUE_MSIX_IDX],
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goya_irq_name[GOYA_EVENT_QUEUE_MSIX_IDX],
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&hdev->event_queue);
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&hdev->event_queue);
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if (rc) {
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if (rc) {
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dev_err(hdev->dev, "Failed to request IRQ %d", irq);
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dev_err(hdev->dev, "Failed to request IRQ %d", irq);
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@ -2238,7 +2238,7 @@ static void goya_sync_irqs(struct hl_device *hdev)
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for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
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for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
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synchronize_irq(pci_irq_vector(hdev->pdev, i));
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synchronize_irq(pci_irq_vector(hdev->pdev, i));
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synchronize_irq(pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX));
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synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX));
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}
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}
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static void goya_disable_msix(struct hl_device *hdev)
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static void goya_disable_msix(struct hl_device *hdev)
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@ -2251,7 +2251,7 @@ static void goya_disable_msix(struct hl_device *hdev)
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goya_sync_irqs(hdev);
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goya_sync_irqs(hdev);
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irq = pci_irq_vector(hdev->pdev, EVENT_QUEUE_MSIX_IDX);
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irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
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free_irq(irq, &hdev->event_queue);
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free_irq(irq, &hdev->event_queue);
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for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
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for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
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@ -32,8 +32,6 @@ struct hl_eq_entry {
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#define EQ_CTL_EVENT_TYPE_SHIFT 16
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#define EQ_CTL_EVENT_TYPE_SHIFT 16
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#define EQ_CTL_EVENT_TYPE_MASK 0x03FF0000
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#define EQ_CTL_EVENT_TYPE_MASK 0x03FF0000
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#define EVENT_QUEUE_MSIX_IDX 5
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enum pq_init_status {
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enum pq_init_status {
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PQ_INIT_STATUS_NA = 0,
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PQ_INIT_STATUS_NA = 0,
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PQ_INIT_STATUS_READY_FOR_CP,
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PQ_INIT_STATUS_READY_FOR_CP,
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@ -8,6 +8,8 @@
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#ifndef GOYA_FW_IF_H
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#ifndef GOYA_FW_IF_H
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#define GOYA_FW_IF_H
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#define GOYA_FW_IF_H
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#define GOYA_EVENT_QUEUE_MSIX_IDX 5
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#define CPU_BOOT_ADDR 0x7FF8040000ull
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#define CPU_BOOT_ADDR 0x7FF8040000ull
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#define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */
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#define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */
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