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Maxim/driver: Add driver for maxim ds26522
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Zhao Qiang
David S. Miller
parent
8a79813c14
commit
c37d4a0085
@ -291,6 +291,17 @@ config FSL_UCC_HDLC
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To compile this driver as a module, choose M here: the
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module will be called fsl_ucc_hdlc.
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config SLIC_DS26522
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tristate "Slic Maxim ds26522 card support"
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depends on SPI
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depends on FSL_SOC || ARCH_MXC || ARCH_LAYERSCAPE
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help
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This module initializes and configures the slic maxim card
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in T1 or E1 mode.
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To compile this driver as a module, choose M here: the
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module will be called slic_ds26522.
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config DSCC4_PCISYNC
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bool "Etinc PCISYNC features"
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depends on DSCC4
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@ -33,6 +33,7 @@ obj-$(CONFIG_PCI200SYN) += pci200syn.o
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obj-$(CONFIG_PC300TOO) += pc300too.o
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obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
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obj-$(CONFIG_FSL_UCC_HDLC) += fsl_ucc_hdlc.o
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obj-$(CONFIG_SLIC_DS26522) += slic_ds26522.o
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clean-files := wanxlfw.inc
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$(obj)/wanxl.o: $(obj)/wanxlfw.inc
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255
drivers/net/wan/slic_ds26522.c
Normal file
255
drivers/net/wan/slic_ds26522.c
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@ -0,0 +1,255 @@
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/*
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* drivers/net/wan/slic_ds26522.c
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*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* Author:Zhao Qiang<qiang.zhao@nxp.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/bitrev.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/kthread.h>
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#include <linux/spi/spi.h>
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#include <linux/wait.h>
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#include <linux/param.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include "slic_ds26522.h"
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#define DRV_NAME "ds26522"
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#define SLIC_TRANS_LEN 1
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#define SLIC_TWO_LEN 2
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#define SLIC_THREE_LEN 3
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static struct spi_device *g_spi;
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Zhao Qiang<B45475@freescale.com>");
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/* the read/write format of address is
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* w/r|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|A3|A2|A1|A0|x
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*/
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static void slic_write(struct spi_device *spi, u16 addr,
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u8 data)
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{
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u8 temp[3];
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addr = bitrev16(addr) >> 1;
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data = bitrev8(data);
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temp[0] = (u8)((addr >> 8) & 0x7f);
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temp[1] = (u8)(addr & 0xfe);
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temp[2] = data;
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/* write spi addr and value */
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spi_write(spi, &temp[0], SLIC_THREE_LEN);
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}
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static u8 slic_read(struct spi_device *spi, u16 addr)
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{
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u8 temp[2];
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u8 data;
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addr = bitrev16(addr) >> 1;
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temp[0] = (u8)(((addr >> 8) & 0x7f) | 0x80);
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temp[1] = (u8)(addr & 0xfe);
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spi_write_then_read(spi, &temp[0], SLIC_TWO_LEN, &data,
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SLIC_TRANS_LEN);
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data = bitrev8(data);
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return data;
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}
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static bool get_slic_product_code(struct spi_device *spi)
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{
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u8 device_id;
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device_id = slic_read(spi, DS26522_IDR_ADDR);
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if ((device_id & 0xf8) == 0x68)
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return true;
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else
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return false;
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}
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static void ds26522_e1_spec_config(struct spi_device *spi)
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{
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/* Receive E1 Mode, Framer Disabled */
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slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_E1);
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/* Transmit E1 Mode, Framer Disable */
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slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_E1);
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/* Receive E1 Mode Framer Enable */
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slic_write(spi, DS26522_RMMR_ADDR,
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slic_read(spi, DS26522_RMMR_ADDR) | DS26522_RMMR_FRM_EN);
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/* Transmit E1 Mode Framer Enable */
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slic_write(spi, DS26522_TMMR_ADDR,
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slic_read(spi, DS26522_TMMR_ADDR) | DS26522_TMMR_FRM_EN);
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/* RCR1, receive E1 B8zs & ESF */
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slic_write(spi, DS26522_RCR1_ADDR,
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DS26522_RCR1_E1_HDB3 | DS26522_RCR1_E1_CCS);
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/* RSYSCLK=2.048MHz, RSYNC-Output */
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slic_write(spi, DS26522_RIOCR_ADDR,
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DS26522_RIOCR_2048KHZ | DS26522_RIOCR_RSIO_OUT);
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/* TCR1 Transmit E1 b8zs */
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slic_write(spi, DS26522_TCR1_ADDR, DS26522_TCR1_TB8ZS);
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/* TSYSCLK=2.048MHz, TSYNC-Output */
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slic_write(spi, DS26522_TIOCR_ADDR,
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DS26522_TIOCR_2048KHZ | DS26522_TIOCR_TSIO_OUT);
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/* Set E1TAF */
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slic_write(spi, DS26522_E1TAF_ADDR, DS26522_E1TAF_DEFAULT);
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/* Set E1TNAF register */
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slic_write(spi, DS26522_E1TNAF_ADDR, DS26522_E1TNAF_DEFAULT);
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/* Receive E1 Mode Framer Enable & init Done */
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slic_write(spi, DS26522_RMMR_ADDR, slic_read(spi, DS26522_RMMR_ADDR) |
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DS26522_RMMR_INIT_DONE);
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/* Transmit E1 Mode Framer Enable & init Done */
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slic_write(spi, DS26522_TMMR_ADDR, slic_read(spi, DS26522_TMMR_ADDR) |
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DS26522_TMMR_INIT_DONE);
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/* Configure LIU E1 mode */
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slic_write(spi, DS26522_LTRCR_ADDR, DS26522_LTRCR_E1);
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/* E1 Mode default 75 ohm w/Transmit Impedance Matlinking */
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slic_write(spi, DS26522_LTITSR_ADDR,
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DS26522_LTITSR_TLIS_75OHM | DS26522_LTITSR_LBOS_75OHM);
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/* E1 Mode default 75 ohm Long Haul w/Receive Impedance Matlinking */
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slic_write(spi, DS26522_LRISMR_ADDR,
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DS26522_LRISMR_75OHM | DS26522_LRISMR_MAX);
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/* Enable Transmit output */
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slic_write(spi, DS26522_LMCR_ADDR, DS26522_LMCR_TE);
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}
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static int slic_ds26522_init_configure(struct spi_device *spi)
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{
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u16 addr;
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/* set clock */
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slic_write(spi, DS26522_GTCCR_ADDR, DS26522_GTCCR_BPREFSEL_REFCLKIN |
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DS26522_GTCCR_BFREQSEL_2048KHZ |
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DS26522_GTCCR_FREQSEL_2048KHZ);
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slic_write(spi, DS26522_GTCR2_ADDR, DS26522_GTCR2_TSSYNCOUT);
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slic_write(spi, DS26522_GFCR_ADDR, DS26522_GFCR_BPCLK_2048KHZ);
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/* set gtcr */
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slic_write(spi, DS26522_GTCR1_ADDR, DS26522_GTCR1);
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/* Global LIU Software Reset Register */
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slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_RESET);
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/* Global Framer and BERT Software Reset Register */
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slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_RESET);
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usleep_range(100, 120);
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slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_NORMAL);
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slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_NORMAL);
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/* Perform RX/TX SRESET,Reset receiver */
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slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_SFTRST);
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/* Reset tranceiver */
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slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_SFTRST);
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usleep_range(100, 120);
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/* Zero all Framer Registers */
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for (addr = DS26522_RF_ADDR_START; addr <= DS26522_RF_ADDR_END;
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addr++)
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slic_write(spi, addr, 0);
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for (addr = DS26522_TF_ADDR_START; addr <= DS26522_TF_ADDR_END;
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addr++)
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slic_write(spi, addr, 0);
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for (addr = DS26522_LIU_ADDR_START; addr <= DS26522_LIU_ADDR_END;
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addr++)
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slic_write(spi, addr, 0);
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for (addr = DS26522_BERT_ADDR_START; addr <= DS26522_BERT_ADDR_END;
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addr++)
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slic_write(spi, addr, 0);
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/* setup ds26522 for E1 specification */
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ds26522_e1_spec_config(spi);
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slic_write(spi, DS26522_GTCR1_ADDR, 0x00);
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return 0;
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}
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static int slic_ds26522_remove(struct spi_device *spi)
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{
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pr_info("DS26522 module uninstalled\n");
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return 0;
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}
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static int slic_ds26522_probe(struct spi_device *spi)
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{
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int ret = 0;
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g_spi = spi;
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spi->bits_per_word = 8;
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if (!get_slic_product_code(spi))
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return ret;
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ret = slic_ds26522_init_configure(spi);
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if (ret == 0)
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pr_info("DS26522 cs%d configurated\n", spi->chip_select);
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return ret;
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}
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static const struct of_device_id slic_ds26522_match[] = {
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{
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.compatible = "maxim,ds26522",
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},
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{},
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};
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static struct spi_driver slic_ds26522_driver = {
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.driver = {
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.name = "ds26522",
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.bus = &spi_bus_type,
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.owner = THIS_MODULE,
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.of_match_table = slic_ds26522_match,
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},
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.probe = slic_ds26522_probe,
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.remove = slic_ds26522_remove,
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};
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static int __init slic_ds26522_init(void)
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{
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return spi_register_driver(&slic_ds26522_driver);
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}
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static void __exit slic_ds26522_exit(void)
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{
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spi_unregister_driver(&slic_ds26522_driver);
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}
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module_init(slic_ds26522_init);
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module_exit(slic_ds26522_exit);
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134
drivers/net/wan/slic_ds26522.h
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134
drivers/net/wan/slic_ds26522.h
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@ -0,0 +1,134 @@
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/*
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* drivers/tdm/line_ctrl/slic_ds26522.h
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*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* Author: Zhao Qiang <B45475@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#define DS26522_RF_ADDR_START 0x00
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#define DS26522_RF_ADDR_END 0xef
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#define DS26522_GLB_ADDR_START 0xf0
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#define DS26522_GLB_ADDR_END 0xff
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#define DS26522_TF_ADDR_START 0x100
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#define DS26522_TF_ADDR_END 0x1ef
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#define DS26522_LIU_ADDR_START 0x1000
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#define DS26522_LIU_ADDR_END 0x101f
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#define DS26522_TEST_ADDR_START 0x1008
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#define DS26522_TEST_ADDR_END 0x101f
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#define DS26522_BERT_ADDR_START 0x1100
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#define DS26522_BERT_ADDR_END 0x110f
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#define DS26522_RMMR_ADDR 0x80
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#define DS26522_RCR1_ADDR 0x81
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#define DS26522_RCR3_ADDR 0x83
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#define DS26522_RIOCR_ADDR 0x84
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#define DS26522_GTCR1_ADDR 0xf0
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#define DS26522_GFCR_ADDR 0xf1
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#define DS26522_GTCR2_ADDR 0xf2
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#define DS26522_GTCCR_ADDR 0xf3
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#define DS26522_GLSRR_ADDR 0xf5
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#define DS26522_GFSRR_ADDR 0xf6
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#define DS26522_IDR_ADDR 0xf8
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#define DS26522_E1TAF_ADDR 0x164
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#define DS26522_E1TNAF_ADDR 0x165
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#define DS26522_TMMR_ADDR 0x180
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#define DS26522_TCR1_ADDR 0x181
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#define DS26522_TIOCR_ADDR 0x184
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#define DS26522_LTRCR_ADDR 0x1000
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#define DS26522_LTITSR_ADDR 0x1001
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#define DS26522_LMCR_ADDR 0x1002
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#define DS26522_LRISMR_ADDR 0x1007
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#define MAX_NUM_OF_CHANNELS 8
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#define PQ_MDS_8E1T1_BRD_REV 0x00
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#define PQ_MDS_8E1T1_PLD_REV 0x00
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#define DS26522_GTCCR_BPREFSEL_REFCLKIN 0xa0
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#define DS26522_GTCCR_BFREQSEL_1544KHZ 0x08
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#define DS26522_GTCCR_FREQSEL_1544KHZ 0x04
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#define DS26522_GTCCR_BFREQSEL_2048KHZ 0x00
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#define DS26522_GTCCR_FREQSEL_2048KHZ 0x00
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#define DS26522_GFCR_BPCLK_2048KHZ 0x00
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#define DS26522_GTCR2_TSSYNCOUT 0x02
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#define DS26522_GTCR1 0x00
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#define DS26522_GFSRR_RESET 0x01
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#define DS26522_GFSRR_NORMAL 0x00
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#define DS26522_GLSRR_RESET 0x01
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#define DS26522_GLSRR_NORMAL 0x00
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#define DS26522_RMMR_SFTRST 0x02
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#define DS26522_RMMR_FRM_EN 0x80
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#define DS26522_RMMR_INIT_DONE 0x40
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#define DS26522_RMMR_T1 0x00
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#define DS26522_RMMR_E1 0x01
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#define DS26522_E1TAF_DEFAULT 0x1b
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#define DS26522_E1TNAF_DEFAULT 0x40
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#define DS26522_TMMR_SFTRST 0x02
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#define DS26522_TMMR_FRM_EN 0x80
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#define DS26522_TMMR_INIT_DONE 0x40
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#define DS26522_TMMR_T1 0x00
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#define DS26522_TMMR_E1 0x01
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#define DS26522_RCR1_T1_SYNCT 0x80
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#define DS26522_RCR1_T1_RB8ZS 0x40
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#define DS26522_RCR1_T1_SYNCC 0x08
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#define DS26522_RCR1_E1_HDB3 0x40
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#define DS26522_RCR1_E1_CCS 0x20
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#define DS26522_RIOCR_1544KHZ 0x00
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#define DS26522_RIOCR_2048KHZ 0x10
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#define DS26522_RIOCR_RSIO_OUT 0x00
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#define DS26522_RCR3_FLB 0x01
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#define DS26522_TIOCR_1544KHZ 0x00
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#define DS26522_TIOCR_2048KHZ 0x10
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#define DS26522_TIOCR_TSIO_OUT 0x04
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#define DS26522_TCR1_TB8ZS 0x04
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#define DS26522_LTRCR_T1 0x02
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#define DS26522_LTRCR_E1 0x00
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#define DS26522_LTITSR_TLIS_75OHM 0x00
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#define DS26522_LTITSR_LBOS_75OHM 0x00
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#define DS26522_LTITSR_TLIS_100OHM 0x10
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#define DS26522_LTITSR_TLIS_0DB_CSU 0x00
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#define DS26522_LRISMR_75OHM 0x00
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#define DS26522_LRISMR_100OHM 0x10
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#define DS26522_LRISMR_MAX 0x03
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#define DS26522_LMCR_TE 0x01
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enum line_rate {
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LINE_RATE_T1, /* T1 line rate (1.544 Mbps) */
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LINE_RATE_E1 /* E1 line rate (2.048 Mbps) */
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};
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enum tdm_trans_mode {
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NORMAL = 0,
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FRAMER_LB
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};
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enum card_support_type {
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LM_CARD = 0,
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DS26522_CARD,
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NO_CARD
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};
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