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ASoC: amd: acp: add ZSC control register programming sequence

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Add ZSC Control register programming sequence for ACP D0 and D3 state
transitions for ACP7.0 onwards. This will allow ACP to enter low power
state when ACP enters D3 state. When ACP enters D0 State, ZSC control
should be disabled.

Tested-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://patch.msgid.link/20240807085154.1987681-1-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vijendar Mukunda 2024-08-07 14:21:48 +05:30 committed by Mark Brown
parent 20288905e1
commit c35fad6f7e
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GPG Key ID: 24D68B725D5487D0
2 changed files with 7 additions and 0 deletions
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5
sound/soc/amd/acp/acp-legacy-common.c
View File

@ -321,6 +321,8 @@ int acp_init(struct acp_chip_info *chip)
pr_err("ACP reset failed\n");
return ret;
}
if (chip->acp_rev >= ACP70_DEV)
writel(0, chip->base + ACP_ZSC_DSP_CTRL);
return 0;
}
EXPORT_SYMBOL_NS_GPL(acp_init, SND_SOC_ACP_COMMON);
@ -336,6 +338,9 @@ int acp_deinit(struct acp_chip_info *chip)
if (chip->acp_rev != ACP70_DEV)
writel(0, chip->base + ACP_CONTROL);
if (chip->acp_rev >= ACP70_DEV)
writel(0x01, chip->base + ACP_ZSC_DSP_CTRL);
return 0;
}
EXPORT_SYMBOL_NS_GPL(acp_deinit, SND_SOC_ACP_COMMON);

2
sound/soc/amd/acp/amd.h
View File

@ -103,6 +103,8 @@
#define ACP70_PGFSM_CONTROL ACP6X_PGFSM_CONTROL
#define ACP70_PGFSM_STATUS ACP6X_PGFSM_STATUS
#define ACP_ZSC_DSP_CTRL 0x0001014
#define ACP_ZSC_STS 0x0001018
#define ACP_SOFT_RST_DONE_MASK 0x00010001
#define ACP_PGFSM_CNTL_POWER_ON_MASK 0xffffffff