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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Malta: Enable tickless and highres timers. [MIPS] Bigsur: Enable tickless and and highres timers. qemu: do not enable IP7 blindly [MIPS] Alchemy: Fix Au1x SD controller IRQ [MIPS] Don't byteswap writes to display when running bigendian
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commit
c34c15b02e
@ -76,9 +76,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
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CONFIG_GENERIC_FIND_NEXT_BIT=y
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CONFIG_GENERIC_HWEIGHT=y
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CONFIG_GENERIC_CALIBRATE_DELAY=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_TIME=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
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# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
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CONFIG_CEVT_BCM1480=y
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CONFIG_CSRC_BCM1480=y
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CONFIG_DMA_COHERENT=y
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CONFIG_CPU_BIG_ENDIAN=y
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# CONFIG_CPU_LITTLE_ENDIAN is not set
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@ -91,6 +95,11 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
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#
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# CPU selection
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#
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CONFIG_TICK_ONESHOT=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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# CONFIG_CPU_LOONGSON2 is not set
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# CONFIG_CPU_MIPS32_R1 is not set
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# CONFIG_CPU_MIPS32_R2 is not set
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# CONFIG_CPU_MIPS64_R1 is not set
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@ -49,10 +49,13 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
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CONFIG_GENERIC_FIND_NEXT_BIT=y
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CONFIG_GENERIC_HWEIGHT=y
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CONFIG_GENERIC_CALIBRATE_DELAY=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_TIME=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
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# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
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CONFIG_ARCH_MAY_HAVE_PC_FDC=y
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CONFIG_CEVT_R4K=y
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CONFIG_DMA_NONCOHERENT=y
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CONFIG_DMA_NEED_PCI_MAP_STATE=y
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CONFIG_EARLY_PRINTK=y
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@ -76,6 +79,10 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
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#
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# CPU selection
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#
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CONFIG_TICK_ONESHOT=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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# CONFIG_CPU_LOONGSON2 is not set
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# CONFIG_CPU_MIPS32_R1 is not set
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CONFIG_CPU_MIPS32_R2=y
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@ -253,6 +260,7 @@ CONFIG_HW_HAS_PCI=y
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CONFIG_PCI=y
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# CONFIG_ARCH_SUPPORTS_MSI is not set
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CONFIG_MMU=y
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CONFIG_I8253=y
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#
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# PCCARD (PCMCIA/CardBus) support
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@ -37,9 +37,9 @@ void mips_display_message(const char *str)
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for (i = 0; i <= 14; i=i+2) {
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if (*str)
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writel(*str++, display + i);
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__raw_writel(*str++, display + i);
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else
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writel(' ', display + i);
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__raw_writel(' ', display + i);
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}
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}
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@ -33,5 +33,5 @@ void __init arch_init_irq(void)
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mips_cpu_irq_init();
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init_i8259_irqs();
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set_c0_status(0x8400);
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set_c0_status(0x400);
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}
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@ -41,8 +41,11 @@
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#define NUM_AU1100_MMC_CONTROLLERS 2
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#define AU1100_SD_IRQ 2
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#if defined(CONFIG_SOC_AU1100)
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#define AU1100_SD_IRQ AU1100_SD_INT
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#elif defined(CONFIG_SOC_AU1200)
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#define AU1100_SD_IRQ AU1200_SD_INT
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#endif
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#define SD0_BASE 0xB0600000
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