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ASoC: amd: acp: Add generic support for PDM controller on ACP
Add driver module for PDM controller on ACP IP block. Expose dai ops to configure ACP_WOV_PDM_BLOCK registers on ACP. Such dai ops will be used by platform specific driver module to register dmic related dai with ASoC. Signed-off-by: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> Link: https://lore.kernel.org/r/20220117115854.455995-2-AjitKumar.Pandey@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Ajit Kumar Pandey
Mark Brown
parent
74cc53cf59
commit
c32bd332ce
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@ -15,6 +15,9 @@ config SND_SOC_AMD_ACP_COMMON
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if SND_SOC_AMD_ACP_COMMON
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config SND_SOC_AMD_ACP_PDM
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tristate
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config SND_SOC_AMD_ACP_I2S
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tristate
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@ -7,6 +7,7 @@
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#common acp driver
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snd-acp-pcm-objs := acp-platform.o
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snd-acp-i2s-objs := acp-i2s.o
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snd-acp-pdm-objs := acp-pdm.o
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#platform specific driver
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snd-acp-renoir-objs := acp-renoir.o
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@ -18,6 +19,7 @@ snd-acp-sof-mach-objs := acp-sof-mach.o
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obj-$(CONFIG_SND_SOC_AMD_ACP_PCM) += snd-acp-pcm.o
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obj-$(CONFIG_SND_SOC_AMD_ACP_I2S) += snd-acp-i2s.o
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obj-$(CONFIG_SND_SOC_AMD_ACP_PDM) += snd-acp-pdm.o
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obj-$(CONFIG_SND_AMD_ASOC_RENOIR) += snd-acp-renoir.o
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193
sound/soc/amd/acp/acp-pdm.c
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193
sound/soc/amd/acp/acp-pdm.c
Normal file
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@ -0,0 +1,193 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2022 Advanced Micro Devices, Inc.
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//
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// Authors: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
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// Vijendar Mukunda <Vijendar.Mukunda@amd.com>
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//
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/*
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* Generic Hardware interface for ACP Audio PDM controller
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include "amd.h"
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#define DRV_NAME "acp-pdm"
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#define PDM_DMA_STAT 0x10
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#define PDM_DMA_INTR_MASK 0x10000
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#define PDM_DEC_64 0x2
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#define PDM_CLK_FREQ_MASK 0x07
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#define PDM_MISC_CTRL_MASK 0x10
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#define PDM_ENABLE 0x01
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#define PDM_DISABLE 0x00
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#define DMA_EN_MASK 0x02
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#define DELAY_US 5
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#define PDM_TIMEOUT 1000
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#define ACP_REGION2_OFFSET 0x02000000
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static int acp_dmic_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct acp_stream *stream = substream->runtime->private_data;
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struct device *dev = dai->component->dev;
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struct acp_dev_data *adata = dev_get_drvdata(dev);
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u32 physical_addr, size_dmic, period_bytes;
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unsigned int dmic_ctrl;
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/* Enable default DMIC clk */
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writel(PDM_CLK_FREQ_MASK, adata->acp_base + ACP_WOV_CLK_CTRL);
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dmic_ctrl = readl(adata->acp_base + ACP_WOV_MISC_CTRL);
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dmic_ctrl |= PDM_MISC_CTRL_MASK;
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writel(dmic_ctrl, adata->acp_base + ACP_WOV_MISC_CTRL);
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period_bytes = frames_to_bytes(substream->runtime,
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substream->runtime->period_size);
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size_dmic = frames_to_bytes(substream->runtime,
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substream->runtime->buffer_size);
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physical_addr = stream->reg_offset + MEM_WINDOW_START;
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/* Init DMIC Ring buffer */
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writel(physical_addr, adata->acp_base + ACP_WOV_RX_RINGBUFADDR);
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writel(size_dmic, adata->acp_base + ACP_WOV_RX_RINGBUFSIZE);
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writel(period_bytes, adata->acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);
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writel(0x01, adata->acp_base + ACPAXI2AXI_ATU_CTRL);
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return 0;
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}
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static int acp_dmic_dai_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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struct device *dev = dai->component->dev;
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struct acp_dev_data *adata = dev_get_drvdata(dev);
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unsigned int dma_enable;
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int ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
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if (!(dma_enable & DMA_EN_MASK)) {
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writel(PDM_ENABLE, adata->acp_base + ACP_WOV_PDM_ENABLE);
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writel(PDM_ENABLE, adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
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}
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ret = readl_poll_timeout_atomic(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE,
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dma_enable, (dma_enable & DMA_EN_MASK),
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DELAY_US, PDM_TIMEOUT);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
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if ((dma_enable & DMA_EN_MASK)) {
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writel(PDM_DISABLE, adata->acp_base + ACP_WOV_PDM_ENABLE);
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writel(PDM_DISABLE, adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);
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}
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ret = readl_poll_timeout_atomic(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE,
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dma_enable, !(dma_enable & DMA_EN_MASK),
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DELAY_US, PDM_TIMEOUT);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int acp_dmic_hwparams(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *hwparams, struct snd_soc_dai *dai)
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{
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struct device *dev = dai->component->dev;
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struct acp_dev_data *adata = dev_get_drvdata(dev);
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unsigned int channels, ch_mask;
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channels = params_channels(hwparams);
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switch (channels) {
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case 2:
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ch_mask = 0;
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break;
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case 4:
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ch_mask = 1;
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break;
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case 6:
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ch_mask = 2;
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break;
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default:
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dev_err(dev, "Invalid channels %d\n", channels);
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return -EINVAL;
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}
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if (params_format(hwparams) != SNDRV_PCM_FORMAT_S32_LE) {
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dev_err(dai->dev, "Invalid format:%d\n", params_format(hwparams));
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return -EINVAL;
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}
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writel(ch_mask, adata->acp_base + ACP_WOV_PDM_NO_OF_CHANNELS);
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writel(PDM_DEC_64, adata->acp_base + ACP_WOV_PDM_DECIMATION_FACTOR);
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return 0;
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}
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static int acp_dmic_dai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct acp_stream *stream = substream->runtime->private_data;
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struct device *dev = dai->component->dev;
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struct acp_dev_data *adata = dev_get_drvdata(dev);
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u32 ext_int_ctrl;
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stream->dai_id = DMIC_INSTANCE;
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stream->irq_bit = BIT(PDM_DMA_STAT);
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stream->pte_offset = ACP_SRAM_PDM_PTE_OFFSET;
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stream->reg_offset = ACP_REGION2_OFFSET;
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/* Enable DMIC Interrupts */
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ext_int_ctrl = readl(adata->acp_base + ACP_EXTERNAL_INTR_CNTL);
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ext_int_ctrl |= PDM_DMA_INTR_MASK;
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writel(ext_int_ctrl, adata->acp_base + ACP_EXTERNAL_INTR_CNTL);
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return 0;
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}
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static void acp_dmic_dai_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->component->dev;
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struct acp_dev_data *adata = dev_get_drvdata(dev);
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u32 ext_int_ctrl;
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/* Disable DMIC interrrupts */
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ext_int_ctrl = readl(adata->acp_base + ACP_EXTERNAL_INTR_CNTL);
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ext_int_ctrl |= ~PDM_DMA_INTR_MASK;
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writel(ext_int_ctrl, adata->acp_base + ACP_EXTERNAL_INTR_CNTL);
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}
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const struct snd_soc_dai_ops acp_dmic_dai_ops = {
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.prepare = acp_dmic_prepare,
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.hw_params = acp_dmic_hwparams,
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.trigger = acp_dmic_dai_trigger,
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.startup = acp_dmic_dai_startup,
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.shutdown = acp_dmic_dai_shutdown,
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};
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EXPORT_SYMBOL_NS_GPL(acp_dmic_dai_ops, SND_SOC_ACP_COMMON);
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_ALIAS(DRV_NAME);
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@ -17,8 +17,9 @@
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#define I2S_SP_INSTANCE 0x00
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#define I2S_BT_INSTANCE 0x01
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#define DMIC_INSTANCE 0x02
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#define MEM_WINDOW_START 0x4000000
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#define MEM_WINDOW_START 0x4080000
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#define ACP_I2S_REG_START 0x1242400
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#define ACP_I2S_REG_END 0x1242810
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@ -38,6 +39,7 @@
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#define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
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#define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
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#define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
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#define ACP_SRAM_PDM_PTE_OFFSET 0x400
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#define PAGE_SIZE_4K_ENABLE 0x2
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#define I2S_SP_TX_MEM_WINDOW_START 0x4000000
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@ -96,6 +98,7 @@ struct acp_dev_data {
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};
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extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
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extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
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int asoc_acp_i2s_probe(struct snd_soc_dai *dai);
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int acp_platform_register(struct device *dev);
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@ -131,6 +134,10 @@ static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int
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high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
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low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
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break;
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case DMIC_INSTANCE:
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high = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
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low = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
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break;
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default:
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dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
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return -EINVAL;
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@ -73,4 +73,24 @@
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#define ACP_BTTDM_ITER 0x280C
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#define ACP_BTTDM_TXFRMT 0x2810
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/* Registers from ACP_WOV_PDM block */
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#define ACP_WOV_PDM_ENABLE 0x2C04
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#define ACP_WOV_PDM_DMA_ENABLE 0x2C08
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#define ACP_WOV_RX_RINGBUFADDR 0x2C0C
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#define ACP_WOV_RX_RINGBUFSIZE 0x2C10
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#define ACP_WOV_RX_LINKPOSITIONCNTR 0x2C14
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#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x2C18
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#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x2C1C
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#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x2C20
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#define ACP_WOV_PDM_FIFO_FLUSH 0x2C24
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#define ACP_WOV_PDM_NO_OF_CHANNELS 0x2C28
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#define ACP_WOV_PDM_DECIMATION_FACTOR 0x2C2C
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#define ACP_WOV_PDM_VAD_CTRL 0x2C30
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#define ACP_WOV_BUFFER_STATUS 0x2C58
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#define ACP_WOV_MISC_CTRL 0x2C5C
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#define ACP_WOV_CLK_CTRL 0x2C60
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#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x2C64
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#define ACP_WOV_ERROR_STATUS_REGISTER 0x2C68
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#endif
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