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DeviceTree fixes for 4.5-rc5:

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- Fix irq msi-map calculation for nonzero rid-base.
 
 - Binding doc updates for GICv3, fsl-imx-uart, and S3C RTC.
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Merge tag 'devicetree-fixes-for-4.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull DeviceTree fixes from Rob Herring:

 - Fix irq msi-map calculation for nonzero rid-base.

 - Binding doc updates for GICv3, fsl-imx-uart, and S3C RTC.

* tag 'devicetree-fixes-for-4.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  rtc: s3c: Document required clocks in the DT binding
  serial: fsl-imx-uart: Fix typo in fsl,dte-mode description
  dt-bindings: arm, gic-v3: require that reserved cells are always 0
  of/irq: Fix msi-map calculation for nonzero rid-base
This commit is contained in:
Linus Torvalds 2016-02-17 11:50:53 -08:00
commit c28b947d04
4 changed files with 17 additions and 5 deletions
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5
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
View File

@ -24,9 +24,8 @@ Main node required properties:
1 = edge triggered
4 = level triggered
Cells 4 and beyond are reserved for future use. When the 1st cell
has a value of 0 or 1, cells 4 and beyond act as padding, and may be
ignored. It is recommended that padding cells have a value of 0.
Cells 4 and beyond are reserved for future use and must have a value
of 0 if present.
- reg : Specifies base physical address(s) and size of the GIC
registers, in the following order:

6
Documentation/devicetree/bindings/rtc/s3c-rtc.txt
View File

@ -14,6 +14,10 @@ Required properties:
interrupt number is the rtc alarm interrupt and second interrupt number
is the rtc tick interrupt. The number of cells representing a interrupt
depends on the parent interrupt controller.
- clocks: Must contain a list of phandle and clock specifier for the rtc
and source clocks.
- clock-names: Must contain "rtc" and "rtc_src" entries sorted in the
same order as the clocks property.
Example:
@ -21,4 +25,6 @@ Example:
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
interrupts = <44 0 45 0>;
clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
clock-names = "rtc", "rtc_src";
};

2
Documentation/devicetree/bindings/serial/fsl-imx-uart.txt
View File

@ -9,7 +9,7 @@ Optional properties:
- fsl,uart-has-rtscts : Indicate the uart has rts and cts
- fsl,irda-mode : Indicate the uart supports irda mode
- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
is DCE mode by default.
in DCE mode by default.
Note: Each uart controller should have an alias correctly numbered
in "aliases" node.

9
drivers/of/irq.c
View File

@ -635,6 +635,13 @@ static u32 __of_msi_map_rid(struct device *dev, struct device_node **np,
msi_base = be32_to_cpup(msi_map + 2);
rid_len = be32_to_cpup(msi_map + 3);
if (rid_base & ~map_mask) {
dev_err(parent_dev,
"Invalid msi-map translation - msi-map-mask (0x%x) ignores rid-base (0x%x)\n",
map_mask, rid_base);
return rid_out;
}
msi_controller_node = of_find_node_by_phandle(phandle);
matched = (masked_rid >= rid_base &&
@ -654,7 +661,7 @@ static u32 __of_msi_map_rid(struct device *dev, struct device_node **np,
if (!matched)
return rid_out;
rid_out = masked_rid + msi_base;
rid_out = masked_rid - rid_base + msi_base;
dev_dbg(dev,
"msi-map at: %s, using mask %08x, rid-base: %08x, msi-base: %08x, length: %08x, rid: %08x -> %08x\n",
dev_name(parent_dev), map_mask, rid_base, msi_base,