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arm64: dts: uniphier: add PXs3 SoC support
Initial support for PXs3 SoC and its reference development board. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
parent
555861fb48
commit
c28adcb536
@ -2,7 +2,8 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
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uniphier-ld11-global.dtb \
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uniphier-ld11-ref.dtb \
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uniphier-ld20-global.dtb \
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uniphier-ld20-ref.dtb
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uniphier-ld20-ref.dtb \
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uniphier-pxs3-ref.dtb
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always := $(dtb-y)
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clean-files := *.dtb
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62
arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
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62
arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
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@ -0,0 +1,62 @@
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/*
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* Device Tree Source for UniPhier PXs3 Reference Board
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*
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* Copyright (C) 2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/dts-v1/;
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#include "uniphier-pxs3.dtsi"
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#include "uniphier-support-card.dtsi"
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/ {
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model = "UniPhier PXs3 Reference Board";
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compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c6 = &i2c6;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0 0x80000000 0 0xa0000000>;
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};
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};
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ðsc {
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interrupts = <0 52 4>;
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};
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&serial0 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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};
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&i2c3 {
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status = "okay";
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};
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367
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
Normal file
367
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
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@ -0,0 +1,367 @@
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/*
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* Device Tree Source for UniPhier PXs3 SoC
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*
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* Copyright (C) 2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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/memreserve/ 0x80000000 0x02000000;
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/ {
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compatible = "socionext,uniphier-pxs3";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x000>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x001>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x002>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x003>;
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clocks = <&sys_clk 33>;
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enable-method = "psci";
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operating-points-v2 = <&cluster0_opp>;
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};
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};
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cluster0_opp: opp_table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-250000000 {
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opp-hz = /bits/ 64 <250000000>;
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clock-latency-ns = <300>;
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};
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opp-325000000 {
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opp-hz = /bits/ 64 <325000000>;
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clock-latency-ns = <300>;
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};
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opp-500000000 {
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opp-hz = /bits/ 64 <500000000>;
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clock-latency-ns = <300>;
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};
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opp-650000000 {
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opp-hz = /bits/ 64 <650000000>;
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clock-latency-ns = <300>;
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};
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opp-666667000 {
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opp-hz = /bits/ 64 <666667000>;
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clock-latency-ns = <300>;
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};
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opp-866667000 {
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opp-hz = /bits/ 64 <866667000>;
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clock-latency-ns = <300>;
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};
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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clock-latency-ns = <300>;
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};
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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clock-latency-ns = <300>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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clocks {
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refclk: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 4>,
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<1 14 4>,
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<1 11 4>,
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<1 10 4>;
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&peri_clk 0>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&peri_clk 1>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&peri_clk 2>;
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <0 177 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&peri_clk 3>;
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};
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58780000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&peri_clk 4>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58781000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58781000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&peri_clk 5>;
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clock-frequency = <100000>;
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};
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i2c2: i2c@58782000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58782000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clocks = <&peri_clk 6>;
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clock-frequency = <100000>;
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};
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i2c3: i2c@58783000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58783000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clocks = <&peri_clk 7>;
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clock-frequency = <100000>;
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};
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/* chip-internal connection for HDMI */
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i2c6: i2c@58786000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58786000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 26 4>;
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clocks = <&peri_clk 10>;
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clock-frequency = <400000>;
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};
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system_bus: system-bus@58c00000 {
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compatible = "socionext,uniphier-system-bus";
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status = "disabled";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_system_bus>;
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};
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smpctrl@59801000 {
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compatible = "socionext,uniphier-smpctrl";
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reg = <0x59801000 0x400>;
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};
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sdctrl@59810000 {
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compatible = "socionext,uniphier-pxs3-sdctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x400>;
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sd_clk: clock {
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compatible = "socionext,uniphier-pxs3-sd-clock";
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#clock-cells = <1>;
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};
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sd_rst: reset {
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compatible = "socionext,uniphier-pxs3-sd-reset";
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#reset-cells = <1>;
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};
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};
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perictrl@59820000 {
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compatible = "socionext,uniphier-pxs3-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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peri_clk: clock {
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compatible = "socionext,uniphier-pxs3-peri-clock";
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#clock-cells = <1>;
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};
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peri_rst: reset {
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compatible = "socionext,uniphier-pxs3-peri-reset";
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#reset-cells = <1>;
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};
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};
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emmc: sdhc@5a000000 {
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compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
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reg = <0x5a000000 0x400>;
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interrupts = <0 78 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_emmc>;
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clocks = <&sys_clk 4>;
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bus-width = <8>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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cdns,phy-input-delay-legacy = <4>;
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cdns,phy-input-delay-mmc-highspeed = <2>;
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cdns,phy-input-delay-mmc-ddr = <3>;
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cdns,phy-dll-delay-sdclk = <21>;
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cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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};
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soc-glue@5f800000 {
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compatible = "socionext,uniphier-pxs3-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-pxs3-pinctrl";
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};
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};
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aidet: aidet@5fc20000 {
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compatible = "socionext,uniphier-pxs3-aidet";
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reg = <0x5fc20000 0x200>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gic: interrupt-controller@5fe00000 {
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compatible = "arm,gic-v3";
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reg = <0x5fe00000 0x10000>, /* GICD */
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<0x5fe80000 0x80000>; /* GICR */
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <1 9 4>;
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};
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sysctrl@61840000 {
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compatible = "socionext,uniphier-pxs3-sysctrl",
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"simple-mfd", "syscon";
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reg = <0x61840000 0x10000>;
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sys_clk: clock {
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compatible = "socionext,uniphier-pxs3-clock";
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#clock-cells = <1>;
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};
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sys_rst: reset {
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compatible = "socionext,uniphier-pxs3-reset";
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#reset-cells = <1>;
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};
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watchdog {
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compatible = "socionext,uniphier-wdt";
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};
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};
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nand: nand@68000000 {
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compatible = "socionext,uniphier-denali-nand-v5b";
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status = "disabled";
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reg-names = "nand_data", "denali_reg";
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reg = <0x68000000 0x20>, <0x68100000 0x1000>;
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interrupts = <0 65 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand>;
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clocks = <&sys_clk 2>;
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};
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};
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};
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#include "uniphier-pinctrl.dtsi"
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