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ARM: at91: make watchdog drivers soc independent

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switch the watchdog drivers to resource and pass it via platform_device

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD 2011-11-02 01:43:31 +08:00
parent f22deee523
commit c1c30a29df
14 changed files with 88 additions and 18 deletions
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11
arch/arm/mach-at91/at91cap9_devices.c
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@ -694,10 +694,19 @@ static void __init at91_add_device_rtt(void)
* -------------------------------------------------------------------- */
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
static struct resource wdt_resources[] = {
{
.start = AT91CAP9_BASE_WDT,
.end = AT91CAP9_BASE_WDT + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device at91cap9_wdt_device = {
.name = "at91_wdt",
.id = -1,
.num_resources = 0,
.resource = wdt_resources,
.num_resources = ARRAY_SIZE(wdt_resources),
};
static void __init at91_add_device_watchdog(void)

11
arch/arm/mach-at91/at91sam9260_devices.c
View File

@ -738,10 +738,19 @@ static void __init at91_add_device_rtt(void)
* -------------------------------------------------------------------- */
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
static struct resource wdt_resources[] = {
{
.start = AT91SAM9260_BASE_WDT,
.end = AT91SAM9260_BASE_WDT + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device at91sam9260_wdt_device = {
.name = "at91_wdt",
.id = -1,
.num_resources = 0,
.resource = wdt_resources,
.num_resources = ARRAY_SIZE(wdt_resources),
};
static void __init at91_add_device_watchdog(void)

11
arch/arm/mach-at91/at91sam9261_devices.c
View File

@ -624,10 +624,19 @@ static void __init at91_add_device_rtt(void)
* -------------------------------------------------------------------- */
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
static struct resource wdt_resources[] = {
{
.start = AT91SAM9261_BASE_WDT,
.end = AT91SAM9261_BASE_WDT + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device at91sam9261_wdt_device = {
.name = "at91_wdt",
.id = -1,
.num_resources = 0,
.resource = wdt_resources,
.num_resources = ARRAY_SIZE(wdt_resources),
};
static void __init at91_add_device_watchdog(void)

11
arch/arm/mach-at91/at91sam9263_devices.c
View File

@ -996,10 +996,19 @@ static void __init at91_add_device_rtt(void)
* -------------------------------------------------------------------- */
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
static struct resource wdt_resources[] = {
{
.start = AT91SAM9263_BASE_WDT,
.end = AT91SAM9263_BASE_WDT + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device at91sam9263_wdt_device = {
.name = "at91_wdt",
.id = -1,
.num_resources = 0,
.resource = wdt_resources,
.num_resources = ARRAY_SIZE(wdt_resources),
};
static void __init at91_add_device_watchdog(void)

11
arch/arm/mach-at91/at91sam9g45_devices.c
View File

@ -1133,10 +1133,19 @@ static void __init at91_add_device_trng(void) {}
* -------------------------------------------------------------------- */
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
static struct resource wdt_resources[] = {
{
.start = AT91SAM9G45_BASE_WDT,
.end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device at91sam9g45_wdt_device = {
.name = "at91_wdt",
.id = -1,
.num_resources = 0,
.resource = wdt_resources,
.num_resources = ARRAY_SIZE(wdt_resources),
};
static void __init at91_add_device_watchdog(void)

11
arch/arm/mach-at91/at91sam9rl_devices.c
View File

@ -709,10 +709,19 @@ static void __init at91_add_device_rtt(void)
* -------------------------------------------------------------------- */
#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
static struct resource wdt_resources[] = {
{
.start = AT91SAM9RL_BASE_WDT,
.end = AT91SAM9RL_BASE_WDT + SZ_16 - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device at91sam9rl_wdt_device = {
.name = "at91_wdt",
.id = -1,
.num_resources = 0,
.resource = wdt_resources,
.num_resources = ARRAY_SIZE(wdt_resources),
};
static void __init at91_add_device_watchdog(void)

2
arch/arm/mach-at91/include/mach/at91cap9.h
View File

@ -86,7 +86,6 @@
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
(0xfffffd50 - AT91_BASE_SYS) : \
(0xfffffd60 - AT91_BASE_SYS))
@ -101,6 +100,7 @@
#define AT91CAP9_BASE_SHDWC 0xfffffd10
#define AT91CAP9_BASE_RTT 0xfffffd20
#define AT91CAP9_BASE_PIT 0xfffffd30
#define AT91CAP9_BASE_WDT 0xfffffd40
#define AT91_USART0 AT91CAP9_BASE_US0
#define AT91_USART1 AT91CAP9_BASE_US1

2
arch/arm/mach-at91/include/mach/at91sam9260.h
View File

@ -86,7 +86,6 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9260_BASE_ECC 0xffffe800
@ -97,6 +96,7 @@
#define AT91SAM9260_BASE_SHDWC 0xfffffd10
#define AT91SAM9260_BASE_RTT 0xfffffd20
#define AT91SAM9260_BASE_PIT 0xfffffd30
#define AT91SAM9260_BASE_WDT 0xfffffd40
#define AT91_USART0 AT91SAM9260_BASE_US0
#define AT91_USART1 AT91SAM9260_BASE_US1

2
arch/arm/mach-at91/include/mach/at91sam9261.h
View File

@ -71,7 +71,6 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9261_BASE_SMC 0xffffec00
@ -81,6 +80,7 @@
#define AT91SAM9261_BASE_SHDWC 0xfffffd10
#define AT91SAM9261_BASE_RTT 0xfffffd20
#define AT91SAM9261_BASE_PIT 0xfffffd30
#define AT91SAM9261_BASE_WDT 0xfffffd40
#define AT91_USART0 AT91SAM9261_BASE_US0
#define AT91_USART1 AT91SAM9261_BASE_US1

2
arch/arm/mach-at91/include/mach/at91sam9263.h
View File

@ -81,7 +81,6 @@
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91SAM9263_BASE_ECC0 0xffffe000
@ -96,6 +95,7 @@
#define AT91SAM9263_BASE_SHDWC 0xfffffd10
#define AT91SAM9263_BASE_RTT0 0xfffffd20
#define AT91SAM9263_BASE_PIT 0xfffffd30
#define AT91SAM9263_BASE_WDT 0xfffffd40
#define AT91SAM9263_BASE_RTT1 0xfffffd50
#define AT91_USART0 AT91SAM9263_BASE_US0

2
arch/arm/mach-at91/include/mach/at91sam9g45.h
View File

@ -93,7 +93,6 @@
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
@ -108,6 +107,7 @@
#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
#define AT91SAM9G45_BASE_RTT 0xfffffd20
#define AT91SAM9G45_BASE_PIT 0xfffffd30
#define AT91SAM9G45_BASE_WDT 0xfffffd40
#define AT91_USART0 AT91SAM9G45_BASE_US0
#define AT91_USART1 AT91SAM9G45_BASE_US1

2
arch/arm/mach-at91/include/mach/at91sam9rl.h
View File

@ -75,7 +75,6 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
@ -90,6 +89,7 @@
#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
#define AT91SAM9RL_BASE_RTT 0xfffffd20
#define AT91SAM9RL_BASE_PIT 0xfffffd30
#define AT91SAM9RL_BASE_WDT 0xfffffd40
#define AT91_USART0 AT91SAM9RL_BASE_US0
#define AT91_USART1 AT91SAM9RL_BASE_US1

22
drivers/watchdog/at91sam9_wdt.c
View File

@ -35,6 +35,11 @@
#define DRV_NAME "AT91SAM9 Watchdog"
#define wdt_read(field) \
__raw_readl(at91wdt_private.base + field)
#define wdt_write(field, val) \
__raw_writel((val), at91wdt_private.base + field)
/* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
* use this to convert a watchdog
* value from/to milliseconds.
@ -63,6 +68,7 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
static void at91_ping(unsigned long data);
static struct {
void __iomem *base;
unsigned long next_heartbeat; /* the next_heartbeat for the timer */
unsigned long open;
char expect_close;
@ -77,7 +83,7 @@ static struct {
*/
static inline void at91_wdt_reset(void)
{
at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
wdt_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
}
/*
@ -132,7 +138,7 @@ static int at91_wdt_settimeout(unsigned int timeout)
unsigned int mr;
/* Check if disabled */
mr = at91_sys_read(AT91_WDT_MR);
mr = wdt_read(AT91_WDT_MR);
if (mr & AT91_WDT_WDDIS) {
printk(KERN_ERR DRV_NAME": sorry, watchdog is disabled\n");
return -EIO;
@ -149,7 +155,7 @@ static int at91_wdt_settimeout(unsigned int timeout)
| AT91_WDT_WDDBGHLT /* disabled in debug mode */
| AT91_WDT_WDD /* restart at any time */
| (timeout & AT91_WDT_WDV); /* timer value */
at91_sys_write(AT91_WDT_MR, reg);
wdt_write(AT91_WDT_MR, reg);
return 0;
}
@ -248,12 +254,22 @@ static struct miscdevice at91wdt_miscdev = {
static int __init at91wdt_probe(struct platform_device *pdev)
{
struct resource *r;
int res;
if (at91wdt_miscdev.parent)
return -EBUSY;
at91wdt_miscdev.parent = &pdev->dev;
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r)
return -ENODEV;
at91wdt_private.base = ioremap(r->start, resource_size(r));
if (!at91wdt_private.base) {
dev_err(&pdev->dev, "failed to map registers, aborting.\n");
return -ENOMEM;
}
/* Set watchdog */
res = at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
if (res)

6
drivers/watchdog/at91sam9_wdt.h
View File

@ -16,11 +16,11 @@
#ifndef AT91_WDT_H
#define AT91_WDT_H
#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
#define AT91_WDT_CR 0x00 /* Watchdog Control Register */
#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */
#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
#define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
@ -30,7 +30,7 @@
#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
#define AT91_WDT_SR 0x08 /* Watchdog Status Register */
#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */