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pinctrl: rockchip: Use common interface for recalced iomux
The other Socs also need the feature of recalced iomux, so make it as a common interface like iomux route feature. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -76,7 +76,6 @@ enum rockchip_pinctrl_type {
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#define IOMUX_SOURCE_PMU BIT(2)
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#define IOMUX_UNROUTED BIT(3)
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#define IOMUX_WIDTH_3BIT BIT(4)
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#define IOMUX_RECALCED BIT(5)
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/**
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* @type: iomux variant using IOMUX_* constants
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@ -166,6 +165,7 @@ struct rockchip_pin_bank {
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struct pinctrl_gpio_range grange;
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raw_spinlock_t slock;
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u32 toggle_edge_mode;
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u32 recalced_mask;
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u32 route_mask;
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};
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@ -289,6 +289,22 @@ struct rockchip_pin_bank {
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.pull_type[3] = pull3, \
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}
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/**
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* struct rockchip_mux_recalced_data: represent a pin iomux data.
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* @num: bank number.
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* @pin: pin number.
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* @bit: index at register.
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* @reg: register offset.
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* @mask: mask bit
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*/
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struct rockchip_mux_recalced_data {
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u8 num;
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u8 pin;
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u8 reg;
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u8 bit;
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u8 mask;
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};
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/**
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* struct rockchip_mux_recalced_data: represent a pin iomux data.
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* @bank_num: bank number.
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@ -317,6 +333,8 @@ struct rockchip_pin_ctrl {
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int pmu_mux_offset;
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int grf_drv_offset;
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int pmu_drv_offset;
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struct rockchip_mux_recalced_data *iomux_recalced;
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u32 niomux_recalced;
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struct rockchip_mux_route_data *iomux_routes;
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u32 niomux_routes;
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@ -326,8 +344,6 @@ struct rockchip_pin_ctrl {
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void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit);
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void (*iomux_recalc)(u8 bank_num, int pin, int *reg,
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u8 *bit, int *mask);
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int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit);
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@ -382,22 +398,6 @@ struct rockchip_pinctrl {
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unsigned int nfunctions;
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};
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/**
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* struct rockchip_mux_recalced_data: represent a pin iomux data.
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* @num: bank number.
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* @pin: pin number.
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* @bit: index at register.
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* @reg: register offset.
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* @mask: mask bit
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*/
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struct rockchip_mux_recalced_data {
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u8 num;
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u8 pin;
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u8 reg;
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u8 bit;
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u8 mask;
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};
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static struct regmap_config rockchip_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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@ -557,7 +557,7 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
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* Hardware access
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*/
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static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
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static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
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{
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.num = 2,
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.pin = 12,
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@ -579,20 +579,22 @@ static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
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},
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};
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static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg,
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u8 *bit, int *mask)
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static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
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int *reg, u8 *bit, int *mask)
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{
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const struct rockchip_mux_recalced_data *data = NULL;
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struct rockchip_pinctrl *info = bank->drvdata;
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struct rockchip_pin_ctrl *ctrl = info->ctrl;
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struct rockchip_mux_recalced_data *data;
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int i;
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for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++)
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if (rk3328_mux_recalced_data[i].num == bank_num &&
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rk3328_mux_recalced_data[i].pin == pin) {
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data = &rk3328_mux_recalced_data[i];
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for (i = 0; i < ctrl->niomux_recalced; i++) {
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data = &ctrl->iomux_recalced[i];
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if (data->num == bank->bank_num &&
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data->pin == pin)
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break;
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}
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}
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if (!data)
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if (i >= ctrl->niomux_recalced)
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return;
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*reg = data->reg;
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@ -877,7 +879,6 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
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static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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struct rockchip_pin_ctrl *ctrl = info->ctrl;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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unsigned int val;
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@ -916,8 +917,8 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
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mask = 0x3;
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}
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if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
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ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask);
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if (bank->recalced_mask & BIT(pin))
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rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
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ret = regmap_read(regmap, reg, &val);
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if (ret)
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@ -967,7 +968,6 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
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static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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struct rockchip_pin_ctrl *ctrl = info->ctrl;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask, mux_type;
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@ -1005,8 +1005,8 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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mask = 0x3;
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}
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if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
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ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask);
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if (bank->recalced_mask & BIT(pin))
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rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
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if (bank->route_mask & BIT(pin)) {
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if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
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@ -2853,6 +2853,16 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
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bank_pins += 8;
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}
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/* calculate the per-bank recalced_mask */
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for (j = 0; j < ctrl->niomux_recalced; j++) {
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int pin = 0;
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if (ctrl->iomux_recalced[j].num == bank->bank_num) {
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pin = ctrl->iomux_recalced[j].pin;
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bank->recalced_mask |= BIT(pin);
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}
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}
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/* calculate the per-bank route_mask */
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for (j = 0; j < ctrl->niomux_routes; j++) {
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int pin = 0;
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@ -3165,12 +3175,12 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
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IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
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IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
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IOMUX_WIDTH_3BIT,
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IOMUX_WIDTH_3BIT,
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0),
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
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IOMUX_WIDTH_3BIT,
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IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
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IOMUX_WIDTH_3BIT,
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0,
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0),
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};
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@ -3181,11 +3191,12 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
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.label = "RK3328-GPIO",
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.type = RK3288,
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.grf_mux_offset = 0x0,
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.iomux_recalced = rk3328_mux_recalced_data,
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.niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
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.iomux_routes = rk3328_mux_route_data,
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.niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
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.pull_calc_reg = rk3228_calc_pull_reg_and_bit,
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.drv_calc_reg = rk3228_calc_drv_reg_and_bit,
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.iomux_recalc = rk3328_recalc_mux,
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.schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
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};
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