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xtensa: Tweak xuartps UART driver Rx watermark for Cadence CSP config.

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Add module parameter xilinx_uartps.rx_trigger_level=32 to command line
options for CSP to set Rx watermark for xuartps driver lower than the
default value, to avoid UART overruns at 115200 bps.

Signed-off-by: Scott Telford <stelford@cadence.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Scott Telford 2016-09-15 16:26:45 +01:00 committed by Max Filippov
parent bf15f86b34
commit bebbc4bcf3
1 changed files with 1 additions and 1 deletions
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2
arch/xtensa/boot/dts/csp.dts
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@ -7,7 +7,7 @@
interrupt-parent = <&pic>;
chosen {
bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk loglevel=8 nohz=off ignore_loglevel";
bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel";
};
memory@0 {