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[SCSI] mvumi: Add support for Marvell SAS/SATA RAID-on-Chip(ROC) 88RC9580
[jejb: fix up for spelling correction patch] Signed-off-by: Shun Fu <fushun@marvell.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Shun Fu
James Bottomley
parent
08bc166d0f
commit
bd756ddea1
1093
drivers/scsi/mvumi.c
1093
drivers/scsi/mvumi.c
File diff suppressed because it is too large
Load Diff
@ -34,51 +34,87 @@
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#define MV_DRIVER_NAME "mvumi"
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#define PCI_VENDOR_ID_MARVELL_2 0x1b4b
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#define PCI_DEVICE_ID_MARVELL_MV9143 0x9143
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#define PCI_DEVICE_ID_MARVELL_MV9580 0x9580
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#define MVUMI_INTERNAL_CMD_WAIT_TIME 45
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#define MVUMI_INQUIRY_LENGTH 44
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#define MVUMI_INQUIRY_UUID_OFF 36
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#define MVUMI_INQUIRY_UUID_LEN 8
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#define IS_DMA64 (sizeof(dma_addr_t) == 8)
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enum mvumi_qc_result {
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MV_QUEUE_COMMAND_RESULT_SENT = 0,
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MV_QUEUE_COMMAND_RESULT_SENT = 0,
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MV_QUEUE_COMMAND_RESULT_NO_RESOURCE,
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};
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struct mvumi_hw_regs {
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/* For CPU */
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void *main_int_cause_reg;
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void *enpointa_mask_reg;
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void *enpointb_mask_reg;
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void *rstoutn_en_reg;
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void *ctrl_sts_reg;
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void *rstoutn_mask_reg;
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void *sys_soft_rst_reg;
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/* For Doorbell */
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void *pciea_to_arm_drbl_reg;
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void *arm_to_pciea_drbl_reg;
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void *arm_to_pciea_mask_reg;
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void *pciea_to_arm_msg0;
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void *pciea_to_arm_msg1;
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void *arm_to_pciea_msg0;
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void *arm_to_pciea_msg1;
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/* reset register */
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void *reset_request;
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void *reset_enable;
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/* For Message Unit */
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void *inb_list_basel;
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void *inb_list_baseh;
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void *inb_aval_count_basel;
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void *inb_aval_count_baseh;
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void *inb_write_pointer;
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void *inb_read_pointer;
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void *outb_list_basel;
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void *outb_list_baseh;
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void *outb_copy_basel;
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void *outb_copy_baseh;
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void *outb_copy_pointer;
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void *outb_read_pointer;
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void *inb_isr_cause;
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void *outb_isr_cause;
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void *outb_coal_cfg;
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void *outb_coal_timeout;
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/* Bit setting for HW */
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u32 int_comaout;
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u32 int_comaerr;
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u32 int_dl_cpu2pciea;
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u32 int_mu;
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u32 int_drbl_int_mask;
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u32 int_main_int_mask;
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u32 cl_pointer_toggle;
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u32 cl_slot_num_mask;
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u32 clic_irq;
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u32 clic_in_err;
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u32 clic_out_err;
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};
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struct mvumi_dyn_list_entry {
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u32 src_low_addr;
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u32 src_high_addr;
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u32 if_length;
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u32 reserve;
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};
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#define SCSI_CMD_MARVELL_SPECIFIC 0xE1
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#define CDB_CORE_MODULE 0x1
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#define CDB_CORE_SHUTDOWN 0xB
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enum {
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/*******************************************/
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/* ARM Mbus Registers Map */
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/*******************************************/
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CPU_MAIN_INT_CAUSE_REG = 0x20200,
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CPU_MAIN_IRQ_MASK_REG = 0x20204,
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CPU_MAIN_FIQ_MASK_REG = 0x20208,
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CPU_ENPOINTA_MASK_REG = 0x2020C,
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CPU_ENPOINTB_MASK_REG = 0x20210,
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INT_MAP_COMAERR = 1 << 6,
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INT_MAP_COMAIN = 1 << 7,
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INT_MAP_COMAOUT = 1 << 8,
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INT_MAP_COMBERR = 1 << 9,
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INT_MAP_COMBIN = 1 << 10,
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INT_MAP_COMBOUT = 1 << 11,
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INT_MAP_COMAINT = (INT_MAP_COMAOUT | INT_MAP_COMAERR),
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INT_MAP_COMBINT = (INT_MAP_COMBOUT | INT_MAP_COMBIN | INT_MAP_COMBERR),
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INT_MAP_DL_PCIEA2CPU = 1 << 0,
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INT_MAP_DL_CPU2PCIEA = 1 << 1,
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/***************************************/
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/* ARM Doorbell Registers Map */
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/***************************************/
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CPU_PCIEA_TO_ARM_DRBL_REG = 0x20400,
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CPU_PCIEA_TO_ARM_MASK_REG = 0x20404,
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CPU_ARM_TO_PCIEA_DRBL_REG = 0x20408,
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CPU_ARM_TO_PCIEA_MASK_REG = 0x2040C,
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DRBL_HANDSHAKE = 1 << 0,
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DRBL_SOFT_RESET = 1 << 1,
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DRBL_BUS_CHANGE = 1 << 2,
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@ -86,46 +122,6 @@ enum {
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DRBL_MU_RESET = 1 << 4,
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DRBL_HANDSHAKE_ISR = DRBL_HANDSHAKE,
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CPU_PCIEA_TO_ARM_MSG0 = 0x20430,
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CPU_PCIEA_TO_ARM_MSG1 = 0x20434,
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CPU_ARM_TO_PCIEA_MSG0 = 0x20438,
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CPU_ARM_TO_PCIEA_MSG1 = 0x2043C,
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/*******************************************/
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/* ARM Communication List Registers Map */
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/*******************************************/
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CLA_INB_LIST_BASEL = 0x500,
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CLA_INB_LIST_BASEH = 0x504,
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CLA_INB_AVAL_COUNT_BASEL = 0x508,
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CLA_INB_AVAL_COUNT_BASEH = 0x50C,
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CLA_INB_DESTI_LIST_BASEL = 0x510,
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CLA_INB_DESTI_LIST_BASEH = 0x514,
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CLA_INB_WRITE_POINTER = 0x518,
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CLA_INB_READ_POINTER = 0x51C,
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CLA_OUTB_LIST_BASEL = 0x530,
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CLA_OUTB_LIST_BASEH = 0x534,
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CLA_OUTB_SOURCE_LIST_BASEL = 0x538,
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CLA_OUTB_SOURCE_LIST_BASEH = 0x53C,
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CLA_OUTB_COPY_POINTER = 0x544,
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CLA_OUTB_READ_POINTER = 0x548,
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CLA_ISR_CAUSE = 0x560,
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CLA_ISR_MASK = 0x564,
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INT_MAP_MU = (INT_MAP_DL_CPU2PCIEA | INT_MAP_COMAINT),
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CL_POINTER_TOGGLE = 1 << 12,
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CLIC_IN_IRQ = 1 << 0,
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CLIC_OUT_IRQ = 1 << 1,
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CLIC_IN_ERR_IRQ = 1 << 8,
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CLIC_OUT_ERR_IRQ = 1 << 12,
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CL_SLOT_NUM_MASK = 0xFFF,
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/*
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* Command flag is the flag for the CDB command itself
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*/
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@ -137,15 +133,23 @@ enum {
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CMD_FLAG_DATA_IN = 1 << 3,
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/* 1-host write data */
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CMD_FLAG_DATA_OUT = 1 << 4,
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SCSI_CMD_MARVELL_SPECIFIC = 0xE1,
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CDB_CORE_SHUTDOWN = 0xB,
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CMD_FLAG_PRDT_IN_HOST = 1 << 5,
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};
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#define APICDB0_EVENT 0xF4
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#define APICDB1_EVENT_GETEVENT 0
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#define APICDB1_HOST_GETEVENT 1
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#define MAX_EVENTS_RETURNED 6
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#define DEVICE_OFFLINE 0
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#define DEVICE_ONLINE 1
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struct mvumi_hotplug_event {
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u16 size;
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u8 dummy[2];
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u8 bitmap[0];
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};
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struct mvumi_driver_event {
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u32 time_stamp;
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u32 sequence_no;
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@ -172,8 +176,14 @@ struct mvumi_events_wq {
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void *param;
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};
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#define HS_CAPABILITY_SUPPORT_COMPACT_SG (1U << 4)
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#define HS_CAPABILITY_SUPPORT_PRD_HOST (1U << 5)
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#define HS_CAPABILITY_SUPPORT_DYN_SRC (1U << 6)
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#define HS_CAPABILITY_NEW_PAGE_IO_DEPTH_DEF (1U << 14)
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#define MVUMI_MAX_SG_ENTRY 32
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#define SGD_EOT (1L << 27)
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#define SGD_EOT_CP (1L << 22)
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struct mvumi_sgl {
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u32 baseaddr_l;
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@ -181,6 +191,39 @@ struct mvumi_sgl {
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u32 flags;
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u32 size;
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};
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struct mvumi_compact_sgl {
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u32 baseaddr_l;
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u32 baseaddr_h;
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u32 flags;
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};
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#define GET_COMPACT_SGD_SIZE(sgd) \
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((((struct mvumi_compact_sgl *)(sgd))->flags) & 0x3FFFFFL)
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#define SET_COMPACT_SGD_SIZE(sgd, sz) do { \
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(((struct mvumi_compact_sgl *)(sgd))->flags) &= ~0x3FFFFFL; \
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(((struct mvumi_compact_sgl *)(sgd))->flags) |= (sz); \
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} while (0)
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#define sgd_getsz(_mhba, sgd, sz) do { \
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if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
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(sz) = GET_COMPACT_SGD_SIZE(sgd); \
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else \
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(sz) = (sgd)->size; \
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} while (0)
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#define sgd_setsz(_mhba, sgd, sz) do { \
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if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
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SET_COMPACT_SGD_SIZE(sgd, sz); \
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else \
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(sgd)->size = (sz); \
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} while (0)
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#define sgd_inc(_mhba, sgd) do { \
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if (_mhba->hba_capability & HS_CAPABILITY_SUPPORT_COMPACT_SG) \
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sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 12); \
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else \
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sgd = (struct mvumi_sgl *)(((unsigned char *) (sgd)) + 16); \
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} while (0)
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struct mvumi_res {
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struct list_head entry;
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@ -197,7 +240,7 @@ enum resource_type {
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};
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struct mvumi_sense_data {
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u8 error_eode:7;
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u8 error_code:7;
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u8 valid:1;
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u8 segment_number;
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u8 sense_key:4;
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@ -220,6 +263,7 @@ struct mvumi_sense_data {
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struct mvumi_cmd {
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struct list_head queue_pointer;
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struct mvumi_msg_frame *frame;
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dma_addr_t frame_phys;
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struct scsi_cmnd *scmd;
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atomic_t sync_cmd;
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void *data_buf;
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@ -393,7 +437,8 @@ struct mvumi_hs_page2 {
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u16 frame_length;
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u8 host_type;
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u8 reserved[3];
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u8 host_cap;
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u8 reserved[2];
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struct version_info host_ver;
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u32 system_io_bus;
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u32 slot_number;
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@ -435,8 +480,17 @@ struct mvumi_tag {
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unsigned short size;
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};
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struct mvumi_device {
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struct list_head list;
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struct scsi_device *sdev;
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u64 wwid;
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u8 dev_type;
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int id;
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};
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struct mvumi_hba {
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void *base_addr[MAX_BASE_ADDRESS];
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u32 pci_base[MAX_BASE_ADDRESS];
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void *mmio;
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struct list_head cmd_pool;
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struct Scsi_Host *shost;
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@ -449,6 +503,9 @@ struct mvumi_hba {
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void *ib_list;
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dma_addr_t ib_list_phys;
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void *ib_frame;
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dma_addr_t ib_frame_phys;
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void *ob_list;
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dma_addr_t ob_list_phys;
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@ -477,12 +534,14 @@ struct mvumi_hba {
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unsigned char hba_total_pages;
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unsigned char fw_flag;
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unsigned char request_id_enabled;
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unsigned char eot_flag;
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unsigned short hba_capability;
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unsigned short io_seq;
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unsigned int ib_cur_slot;
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unsigned int ob_cur_slot;
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unsigned int fw_state;
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struct mutex sas_discovery_mutex;
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struct list_head ob_data_list;
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struct list_head free_ob_list;
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@ -491,14 +550,24 @@ struct mvumi_hba {
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struct mvumi_tag tag_pool;
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struct mvumi_cmd **tag_cmd;
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struct mvumi_hw_regs *regs;
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struct mutex device_lock;
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struct list_head mhba_dev_list;
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struct list_head shost_dev_list;
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struct task_struct *dm_thread;
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atomic_t pnp_count;
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};
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struct mvumi_instance_template {
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void (*fire_cmd)(struct mvumi_hba *, struct mvumi_cmd *);
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void (*enable_intr)(void *) ;
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void (*disable_intr)(void *);
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int (*clear_intr)(void *);
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unsigned int (*read_fw_status_reg)(void *);
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void (*fire_cmd) (struct mvumi_hba *, struct mvumi_cmd *);
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void (*enable_intr) (struct mvumi_hba *);
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void (*disable_intr) (struct mvumi_hba *);
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int (*clear_intr) (void *);
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unsigned int (*read_fw_status_reg) (struct mvumi_hba *);
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unsigned int (*check_ib_list) (struct mvumi_hba *);
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int (*check_ob_list) (struct mvumi_hba *, unsigned int *,
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unsigned int *);
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int (*reset_host) (struct mvumi_hba *);
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};
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extern struct timezone sys_tz;
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