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drm/amdgpu/gfx9.4.3: Enable bad opcode interrupt
For the bad opcode case, it will cause CP/ME hang. The firmware will prevent the ME side from hanging by raising a bad opcode interrupt. And the driver needs to perform a vmid reset when receiving the interrupt. Acked-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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238352b494
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@ -901,6 +901,13 @@ static int gfx_v9_4_3_sw_init(void *handle)
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if (r)
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if (r)
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return r;
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return r;
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/* Bad opcode Event */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
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GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR,
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&adev->gfx.bad_op_irq);
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if (r)
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return r;
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/* Privileged reg */
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/* Privileged reg */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
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&adev->gfx.priv_reg_irq);
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&adev->gfx.priv_reg_irq);
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@ -2162,6 +2169,7 @@ static int gfx_v9_4_3_hw_fini(void *handle)
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amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
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amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
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amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
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amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
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amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
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num_xcc = NUM_XCC(adev->gfx.xcc_mask);
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num_xcc = NUM_XCC(adev->gfx.xcc_mask);
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for (i = 0; i < num_xcc; i++) {
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for (i = 0; i < num_xcc; i++) {
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@ -2327,6 +2335,10 @@ static int gfx_v9_4_3_late_init(void *handle)
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if (r)
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if (r)
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return r;
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return r;
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r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
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if (r)
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return r;
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if (adev->gfx.ras &&
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if (adev->gfx.ras &&
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adev->gfx.ras->enable_watchdog_timer)
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adev->gfx.ras->enable_watchdog_timer)
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adev->gfx.ras->enable_watchdog_timer(adev);
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adev->gfx.ras->enable_watchdog_timer(adev);
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@ -2964,6 +2976,46 @@ static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,
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return 0;
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return 0;
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}
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}
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static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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u32 mec_int_cntl_reg, mec_int_cntl;
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int i, j, k, num_xcc;
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num_xcc = NUM_XCC(adev->gfx.xcc_mask);
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switch (state) {
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case AMDGPU_IRQ_STATE_DISABLE:
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case AMDGPU_IRQ_STATE_ENABLE:
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for (i = 0; i < num_xcc; i++) {
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WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
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OPCODE_ERROR_INT_ENABLE,
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state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
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for (j = 0; j < adev->gfx.mec.num_mec; j++) {
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for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
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/* MECs start at 1 */
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mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k);
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if (mec_int_cntl_reg) {
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mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i);
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mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
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OPCODE_ERROR_INT_ENABLE,
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state == AMDGPU_IRQ_STATE_ENABLE ?
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1 : 0);
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WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i);
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}
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}
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}
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}
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break;
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default:
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break;
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}
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return 0;
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}
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static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev,
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static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_irq_src *source,
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unsigned type,
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unsigned type,
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@ -3116,6 +3168,15 @@ static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev,
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return 0;
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return 0;
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}
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}
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static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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DRM_ERROR("Illegal opcode in command stream\n");
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gfx_v9_4_3_fault(adev, entry);
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return 0;
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}
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static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev,
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static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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struct amdgpu_iv_entry *entry)
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@ -4228,6 +4289,11 @@ static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = {
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.process = gfx_v9_4_3_priv_reg_irq,
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.process = gfx_v9_4_3_priv_reg_irq,
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};
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};
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static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = {
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.set = gfx_v9_4_3_set_bad_op_fault_state,
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.process = gfx_v9_4_3_bad_op_irq,
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};
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static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = {
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static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = {
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.set = gfx_v9_4_3_set_priv_inst_fault_state,
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.set = gfx_v9_4_3_set_priv_inst_fault_state,
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.process = gfx_v9_4_3_priv_inst_irq,
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.process = gfx_v9_4_3_priv_inst_irq,
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@ -4241,6 +4307,9 @@ static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev)
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adev->gfx.priv_reg_irq.num_types = 1;
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adev->gfx.priv_reg_irq.num_types = 1;
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adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs;
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adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs;
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adev->gfx.bad_op_irq.num_types = 1;
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adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs;
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adev->gfx.priv_inst_irq.num_types = 1;
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adev->gfx.priv_inst_irq.num_types = 1;
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adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs;
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adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs;
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}
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}
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