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clk: remove zte zx driver
The zte zx platform is getting removed, so this driver is no longer needed. Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120131026.1721788-3-arnd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Arnd Bergmann
Stephen Boyd
parent
7765f32a8e
commit
bcbe6005eb
@ -1,34 +0,0 @@
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Device Tree Clock bindings for ZTE zx296702
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"zte,zx296702-topcrm-clk":
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zx296702 top clock selection, divider and gating
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"zte,zx296702-lsp0crpm-clk" and
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"zte,zx296702-lsp1crpm-clk":
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zx296702 device level clock selection and gating
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- reg: Address and length of the register set
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h
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for the full list of zx296702 clock IDs.
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topclk: topcrm@09800000 {
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compatible = "zte,zx296702-topcrm-clk";
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reg = <0x09800000 0x1000>;
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#clock-cells = <1>;
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};
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uart0: serial@09405000 {
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compatible = "zte,zx296702-uart";
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reg = <0x09405000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&lsp1clk ZX296702_UART0_PCLK>;
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};
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@ -1,37 +0,0 @@
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Device Tree Clock bindings for ZTE zx296718
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"zte,zx296718-topcrm":
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zx296718 top clock selection, divider and gating
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"zte,zx296718-lsp0crm" and
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"zte,zx296718-lsp1crm":
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zx296718 device level clock selection and gating
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"zte,zx296718-audiocrm":
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zx296718 audio clock selection, divider and gating
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- reg: Address and length of the register set
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h
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for the full list of zx296718 clock IDs.
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topclk: topcrm@1461000 {
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compatible = "zte,zx296718-topcrm-clk";
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reg = <0x01461000 0x1000>;
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#clock-cells = <1>;
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};
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usbphy0:usb-phy0 {
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compatible = "zte,zx296718-usb-phy";
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#phy-cells = <0>;
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clocks = <&topclk USB20_PHY_CLK>;
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clock-names = "phyclk";
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};
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@ -120,6 +120,5 @@ obj-y += versatile/
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ifeq ($(CONFIG_COMMON_CLK), y)
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obj-$(CONFIG_X86) += x86/
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endif
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obj-$(CONFIG_ARCH_ZX) += zte/
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obj-$(CONFIG_ARCH_ZYNQ) += zynq/
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obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/
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@ -1,4 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-y := clk.o
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obj-$(CONFIG_SOC_ZX296702) += clk-zx296702.o
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obj-$(CONFIG_ARCH_ZX) += clk-zx296718.o
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@ -1,741 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2014 Linaro Ltd.
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* Copyright (C) 2014 ZTE Corporation.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <dt-bindings/clock/zx296702-clock.h>
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#include "clk.h"
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static DEFINE_SPINLOCK(reg_lock);
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static void __iomem *topcrm_base;
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static void __iomem *lsp0crpm_base;
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static void __iomem *lsp1crpm_base;
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static struct clk *topclk[ZX296702_TOPCLK_END];
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static struct clk *lsp0clk[ZX296702_LSP0CLK_END];
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static struct clk *lsp1clk[ZX296702_LSP1CLK_END];
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static struct clk_onecell_data topclk_data;
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static struct clk_onecell_data lsp0clk_data;
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static struct clk_onecell_data lsp1clk_data;
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#define CLK_MUX (topcrm_base + 0x04)
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#define CLK_DIV (topcrm_base + 0x08)
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#define CLK_EN0 (topcrm_base + 0x0c)
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#define CLK_EN1 (topcrm_base + 0x10)
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#define VOU_LOCAL_CLKEN (topcrm_base + 0x68)
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#define VOU_LOCAL_CLKSEL (topcrm_base + 0x70)
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#define VOU_LOCAL_DIV2_SET (topcrm_base + 0x74)
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#define CLK_MUX1 (topcrm_base + 0x8c)
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#define CLK_SDMMC1 (lsp0crpm_base + 0x0c)
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#define CLK_GPIO (lsp0crpm_base + 0x2c)
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#define CLK_SPDIF0 (lsp0crpm_base + 0x10)
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#define SPDIF0_DIV (lsp0crpm_base + 0x14)
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#define CLK_I2S0 (lsp0crpm_base + 0x18)
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#define I2S0_DIV (lsp0crpm_base + 0x1c)
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#define CLK_I2S1 (lsp0crpm_base + 0x20)
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#define I2S1_DIV (lsp0crpm_base + 0x24)
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#define CLK_I2S2 (lsp0crpm_base + 0x34)
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#define I2S2_DIV (lsp0crpm_base + 0x38)
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#define CLK_UART0 (lsp1crpm_base + 0x20)
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#define CLK_UART1 (lsp1crpm_base + 0x24)
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#define CLK_SDMMC0 (lsp1crpm_base + 0x2c)
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#define CLK_SPDIF1 (lsp1crpm_base + 0x30)
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#define SPDIF1_DIV (lsp1crpm_base + 0x34)
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static const struct zx_pll_config pll_a9_config[] = {
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{ .rate = 700000000, .cfg0 = 0x800405d1, .cfg1 = 0x04555555 },
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{ .rate = 800000000, .cfg0 = 0x80040691, .cfg1 = 0x04aaaaaa },
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{ .rate = 900000000, .cfg0 = 0x80040791, .cfg1 = 0x04000000 },
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{ .rate = 1000000000, .cfg0 = 0x80040851, .cfg1 = 0x04555555 },
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{ .rate = 1100000000, .cfg0 = 0x80040911, .cfg1 = 0x04aaaaaa },
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{ .rate = 1200000000, .cfg0 = 0x80040a11, .cfg1 = 0x04000000 },
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};
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static const struct clk_div_table main_hlk_div[] = {
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{ .val = 1, .div = 2, },
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{ .val = 3, .div = 4, },
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{ /* sentinel */ }
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};
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static const struct clk_div_table a9_as1_aclk_divider[] = {
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{ .val = 0, .div = 1, },
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{ .val = 1, .div = 2, },
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{ .val = 3, .div = 4, },
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{ /* sentinel */ }
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};
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static const struct clk_div_table sec_wclk_divider[] = {
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{ .val = 0, .div = 1, },
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{ .val = 1, .div = 2, },
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{ .val = 3, .div = 4, },
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{ .val = 5, .div = 6, },
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{ .val = 7, .div = 8, },
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{ /* sentinel */ }
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};
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static const char * const matrix_aclk_sel[] = {
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"pll_mm0_198M",
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"osc",
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"clk_148M5",
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"pll_lsp_104M",
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};
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static const char * const a9_wclk_sel[] = {
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"pll_a9",
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"osc",
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"clk_500",
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"clk_250",
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};
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static const char * const a9_as1_aclk_sel[] = {
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"clk_250",
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"osc",
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"pll_mm0_396M",
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"pll_mac_333M",
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};
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static const char * const a9_trace_clkin_sel[] = {
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"clk_74M25",
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"pll_mm1_108M",
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"clk_125",
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"clk_148M5",
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};
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static const char * const decppu_aclk_sel[] = {
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"clk_250",
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"pll_mm0_198M",
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"pll_lsp_104M",
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"pll_audio_294M912",
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};
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static const char * const vou_main_wclk_sel[] = {
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"clk_148M5",
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"clk_74M25",
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"clk_27",
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"pll_mm1_54M",
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};
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static const char * const vou_scaler_wclk_sel[] = {
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"clk_250",
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"pll_mac_333M",
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"pll_audio_294M912",
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"pll_mm0_198M",
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};
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static const char * const r2d_wclk_sel[] = {
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"pll_audio_294M912",
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"pll_mac_333M",
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"pll_a9_350M",
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"pll_mm0_396M",
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};
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static const char * const ddr_wclk_sel[] = {
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"pll_mac_333M",
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"pll_ddr_266M",
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"pll_audio_294M912",
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"pll_mm0_198M",
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};
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static const char * const nand_wclk_sel[] = {
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"pll_lsp_104M",
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"osc",
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};
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static const char * const lsp_26_wclk_sel[] = {
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"pll_lsp_26M",
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"osc",
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};
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static const char * const vl0_sel[] = {
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"vou_main_channel_div",
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"vou_aux_channel_div",
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};
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static const char * const hdmi_sel[] = {
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"vou_main_channel_wclk",
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"vou_aux_channel_wclk",
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};
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static const char * const sdmmc0_wclk_sel[] = {
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"lsp1_104M_wclk",
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"lsp1_26M_wclk",
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};
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static const char * const sdmmc1_wclk_sel[] = {
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"lsp0_104M_wclk",
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"lsp0_26M_wclk",
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};
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static const char * const uart_wclk_sel[] = {
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"lsp1_104M_wclk",
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"lsp1_26M_wclk",
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};
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static const char * const spdif0_wclk_sel[] = {
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"lsp0_104M_wclk",
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"lsp0_26M_wclk",
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};
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static const char * const spdif1_wclk_sel[] = {
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"lsp1_104M_wclk",
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"lsp1_26M_wclk",
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};
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static const char * const i2s_wclk_sel[] = {
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"lsp0_104M_wclk",
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"lsp0_26M_wclk",
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};
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static inline struct clk *zx_divtbl(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width,
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const struct clk_div_table *table)
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{
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return clk_register_divider_table(NULL, name, parent, 0, reg, shift,
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width, 0, table, ®_lock);
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}
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static inline struct clk *zx_div(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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return clk_register_divider(NULL, name, parent, 0,
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reg, shift, width, 0, ®_lock);
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}
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static inline struct clk *zx_mux(const char *name, const char * const *parents,
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int num_parents, void __iomem *reg, u8 shift, u8 width)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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0, reg, shift, width, 0, ®_lock);
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}
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static inline struct clk *zx_gate(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate(NULL, name, parent, CLK_IGNORE_UNUSED,
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reg, shift, CLK_SET_RATE_PARENT, ®_lock);
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}
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static void __init zx296702_top_clocks_init(struct device_node *np)
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{
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struct clk **clk = topclk;
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int i;
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topcrm_base = of_iomap(np, 0);
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WARN_ON(!topcrm_base);
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clk[ZX296702_OSC] =
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clk_register_fixed_rate(NULL, "osc", NULL, 0, 30000000);
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clk[ZX296702_PLL_A9] =
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clk_register_zx_pll("pll_a9", "osc", 0, topcrm_base
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+ 0x01c, pll_a9_config,
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ARRAY_SIZE(pll_a9_config), ®_lock);
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/* TODO: pll_a9_350M look like changeble follow a9 pll */
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clk[ZX296702_PLL_A9_350M] =
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clk_register_fixed_rate(NULL, "pll_a9_350M", "osc", 0,
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350000000);
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clk[ZX296702_PLL_MAC_1000M] =
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clk_register_fixed_rate(NULL, "pll_mac_1000M", "osc", 0,
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1000000000);
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clk[ZX296702_PLL_MAC_333M] =
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clk_register_fixed_rate(NULL, "pll_mac_333M", "osc", 0,
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333000000);
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clk[ZX296702_PLL_MM0_1188M] =
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clk_register_fixed_rate(NULL, "pll_mm0_1188M", "osc", 0,
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1188000000);
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clk[ZX296702_PLL_MM0_396M] =
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clk_register_fixed_rate(NULL, "pll_mm0_396M", "osc", 0,
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396000000);
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clk[ZX296702_PLL_MM0_198M] =
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clk_register_fixed_rate(NULL, "pll_mm0_198M", "osc", 0,
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198000000);
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clk[ZX296702_PLL_MM1_108M] =
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clk_register_fixed_rate(NULL, "pll_mm1_108M", "osc", 0,
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108000000);
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clk[ZX296702_PLL_MM1_72M] =
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clk_register_fixed_rate(NULL, "pll_mm1_72M", "osc", 0,
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72000000);
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clk[ZX296702_PLL_MM1_54M] =
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clk_register_fixed_rate(NULL, "pll_mm1_54M", "osc", 0,
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54000000);
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clk[ZX296702_PLL_LSP_104M] =
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clk_register_fixed_rate(NULL, "pll_lsp_104M", "osc", 0,
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104000000);
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clk[ZX296702_PLL_LSP_26M] =
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clk_register_fixed_rate(NULL, "pll_lsp_26M", "osc", 0,
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26000000);
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clk[ZX296702_PLL_DDR_266M] =
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clk_register_fixed_rate(NULL, "pll_ddr_266M", "osc", 0,
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266000000);
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clk[ZX296702_PLL_AUDIO_294M912] =
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clk_register_fixed_rate(NULL, "pll_audio_294M912", "osc", 0,
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294912000);
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/* bus clock */
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clk[ZX296702_MATRIX_ACLK] =
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zx_mux("matrix_aclk", matrix_aclk_sel,
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ARRAY_SIZE(matrix_aclk_sel), CLK_MUX, 2, 2);
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clk[ZX296702_MAIN_HCLK] =
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zx_divtbl("main_hclk", "matrix_aclk", CLK_DIV, 0, 2,
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main_hlk_div);
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clk[ZX296702_MAIN_PCLK] =
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zx_divtbl("main_pclk", "matrix_aclk", CLK_DIV, 2, 2,
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main_hlk_div);
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/* cpu clock */
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clk[ZX296702_CLK_500] =
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clk_register_fixed_factor(NULL, "clk_500", "pll_mac_1000M", 0,
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1, 2);
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clk[ZX296702_CLK_250] =
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clk_register_fixed_factor(NULL, "clk_250", "pll_mac_1000M", 0,
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1, 4);
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clk[ZX296702_CLK_125] =
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clk_register_fixed_factor(NULL, "clk_125", "clk_250", 0, 1, 2);
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clk[ZX296702_CLK_148M5] =
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clk_register_fixed_factor(NULL, "clk_148M5", "pll_mm0_1188M", 0,
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1, 8);
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clk[ZX296702_CLK_74M25] =
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clk_register_fixed_factor(NULL, "clk_74M25", "pll_mm0_1188M", 0,
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1, 16);
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clk[ZX296702_A9_WCLK] =
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zx_mux("a9_wclk", a9_wclk_sel, ARRAY_SIZE(a9_wclk_sel), CLK_MUX,
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0, 2);
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clk[ZX296702_A9_AS1_ACLK_MUX] =
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zx_mux("a9_as1_aclk_mux", a9_as1_aclk_sel,
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ARRAY_SIZE(a9_as1_aclk_sel), CLK_MUX, 4, 2);
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clk[ZX296702_A9_TRACE_CLKIN_MUX] =
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zx_mux("a9_trace_clkin_mux", a9_trace_clkin_sel,
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ARRAY_SIZE(a9_trace_clkin_sel), CLK_MUX1, 0, 2);
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clk[ZX296702_A9_AS1_ACLK_DIV] =
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zx_divtbl("a9_as1_aclk_div", "a9_as1_aclk_mux", CLK_DIV, 4, 2,
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a9_as1_aclk_divider);
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/* multi-media clock */
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clk[ZX296702_CLK_2] =
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clk_register_fixed_factor(NULL, "clk_2", "pll_mm1_72M", 0,
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1, 36);
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clk[ZX296702_CLK_27] =
|
||||
clk_register_fixed_factor(NULL, "clk_27", "pll_mm1_54M", 0,
|
||||
1, 2);
|
||||
clk[ZX296702_DECPPU_ACLK_MUX] =
|
||||
zx_mux("decppu_aclk_mux", decppu_aclk_sel,
|
||||
ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 6, 2);
|
||||
clk[ZX296702_PPU_ACLK_MUX] =
|
||||
zx_mux("ppu_aclk_mux", decppu_aclk_sel,
|
||||
ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 8, 2);
|
||||
clk[ZX296702_MALI400_ACLK_MUX] =
|
||||
zx_mux("mali400_aclk_mux", decppu_aclk_sel,
|
||||
ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 12, 2);
|
||||
clk[ZX296702_VOU_ACLK_MUX] =
|
||||
zx_mux("vou_aclk_mux", decppu_aclk_sel,
|
||||
ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 10, 2);
|
||||
clk[ZX296702_VOU_MAIN_WCLK_MUX] =
|
||||
zx_mux("vou_main_wclk_mux", vou_main_wclk_sel,
|
||||
ARRAY_SIZE(vou_main_wclk_sel), CLK_MUX, 14, 2);
|
||||
clk[ZX296702_VOU_AUX_WCLK_MUX] =
|
||||
zx_mux("vou_aux_wclk_mux", vou_main_wclk_sel,
|
||||
ARRAY_SIZE(vou_main_wclk_sel), CLK_MUX, 16, 2);
|
||||
clk[ZX296702_VOU_SCALER_WCLK_MUX] =
|
||||
zx_mux("vou_scaler_wclk_mux", vou_scaler_wclk_sel,
|
||||
ARRAY_SIZE(vou_scaler_wclk_sel), CLK_MUX,
|
||||
18, 2);
|
||||
clk[ZX296702_R2D_ACLK_MUX] =
|
||||
zx_mux("r2d_aclk_mux", decppu_aclk_sel,
|
||||
ARRAY_SIZE(decppu_aclk_sel), CLK_MUX, 20, 2);
|
||||
clk[ZX296702_R2D_WCLK_MUX] =
|
||||
zx_mux("r2d_wclk_mux", r2d_wclk_sel,
|
||||
ARRAY_SIZE(r2d_wclk_sel), CLK_MUX, 22, 2);
|
||||
|
||||
/* other clock */
|
||||
clk[ZX296702_CLK_50] =
|
||||
clk_register_fixed_factor(NULL, "clk_50", "pll_mac_1000M",
|
||||
0, 1, 20);
|
||||
clk[ZX296702_CLK_25] =
|
||||
clk_register_fixed_factor(NULL, "clk_25", "pll_mac_1000M",
|
||||
0, 1, 40);
|
||||
clk[ZX296702_CLK_12] =
|
||||
clk_register_fixed_factor(NULL, "clk_12", "pll_mm1_72M",
|
||||
0, 1, 6);
|
||||
clk[ZX296702_CLK_16M384] =
|
||||
clk_register_fixed_factor(NULL, "clk_16M384",
|
||||
"pll_audio_294M912", 0, 1, 18);
|
||||
clk[ZX296702_CLK_32K768] =
|
||||
clk_register_fixed_factor(NULL, "clk_32K768", "clk_16M384",
|
||||
0, 1, 500);
|
||||
clk[ZX296702_SEC_WCLK_DIV] =
|
||||
zx_divtbl("sec_wclk_div", "pll_lsp_104M", CLK_DIV, 6, 3,
|
||||
sec_wclk_divider);
|
||||
clk[ZX296702_DDR_WCLK_MUX] =
|
||||
zx_mux("ddr_wclk_mux", ddr_wclk_sel,
|
||||
ARRAY_SIZE(ddr_wclk_sel), CLK_MUX, 24, 2);
|
||||
clk[ZX296702_NAND_WCLK_MUX] =
|
||||
zx_mux("nand_wclk_mux", nand_wclk_sel,
|
||||
ARRAY_SIZE(nand_wclk_sel), CLK_MUX, 24, 2);
|
||||
clk[ZX296702_LSP_26_WCLK_MUX] =
|
||||
zx_mux("lsp_26_wclk_mux", lsp_26_wclk_sel,
|
||||
ARRAY_SIZE(lsp_26_wclk_sel), CLK_MUX, 27, 1);
|
||||
|
||||
/* gates */
|
||||
clk[ZX296702_A9_AS0_ACLK] =
|
||||
zx_gate("a9_as0_aclk", "matrix_aclk", CLK_EN0, 0);
|
||||
clk[ZX296702_A9_AS1_ACLK] =
|
||||
zx_gate("a9_as1_aclk", "a9_as1_aclk_div", CLK_EN0, 1);
|
||||
clk[ZX296702_A9_TRACE_CLKIN] =
|
||||
zx_gate("a9_trace_clkin", "a9_trace_clkin_mux", CLK_EN0, 2);
|
||||
clk[ZX296702_DECPPU_AXI_M_ACLK] =
|
||||
zx_gate("decppu_axi_m_aclk", "decppu_aclk_mux", CLK_EN0, 3);
|
||||
clk[ZX296702_DECPPU_AHB_S_HCLK] =
|
||||
zx_gate("decppu_ahb_s_hclk", "main_hclk", CLK_EN0, 4);
|
||||
clk[ZX296702_PPU_AXI_M_ACLK] =
|
||||
zx_gate("ppu_axi_m_aclk", "ppu_aclk_mux", CLK_EN0, 5);
|
||||
clk[ZX296702_PPU_AHB_S_HCLK] =
|
||||
zx_gate("ppu_ahb_s_hclk", "main_hclk", CLK_EN0, 6);
|
||||
clk[ZX296702_VOU_AXI_M_ACLK] =
|
||||
zx_gate("vou_axi_m_aclk", "vou_aclk_mux", CLK_EN0, 7);
|
||||
clk[ZX296702_VOU_APB_PCLK] =
|
||||
zx_gate("vou_apb_pclk", "main_pclk", CLK_EN0, 8);
|
||||
clk[ZX296702_VOU_MAIN_CHANNEL_WCLK] =
|
||||
zx_gate("vou_main_channel_wclk", "vou_main_wclk_mux",
|
||||
CLK_EN0, 9);
|
||||
clk[ZX296702_VOU_AUX_CHANNEL_WCLK] =
|
||||
zx_gate("vou_aux_channel_wclk", "vou_aux_wclk_mux",
|
||||
CLK_EN0, 10);
|
||||
clk[ZX296702_VOU_HDMI_OSCLK_CEC] =
|
||||
zx_gate("vou_hdmi_osclk_cec", "clk_2", CLK_EN0, 11);
|
||||
clk[ZX296702_VOU_SCALER_WCLK] =
|
||||
zx_gate("vou_scaler_wclk", "vou_scaler_wclk_mux", CLK_EN0, 12);
|
||||
clk[ZX296702_MALI400_AXI_M_ACLK] =
|
||||
zx_gate("mali400_axi_m_aclk", "mali400_aclk_mux", CLK_EN0, 13);
|
||||
clk[ZX296702_MALI400_APB_PCLK] =
|
||||
zx_gate("mali400_apb_pclk", "main_pclk", CLK_EN0, 14);
|
||||
clk[ZX296702_R2D_WCLK] =
|
||||
zx_gate("r2d_wclk", "r2d_wclk_mux", CLK_EN0, 15);
|
||||
clk[ZX296702_R2D_AXI_M_ACLK] =
|
||||
zx_gate("r2d_axi_m_aclk", "r2d_aclk_mux", CLK_EN0, 16);
|
||||
clk[ZX296702_R2D_AHB_HCLK] =
|
||||
zx_gate("r2d_ahb_hclk", "main_hclk", CLK_EN0, 17);
|
||||
clk[ZX296702_DDR3_AXI_S0_ACLK] =
|
||||
zx_gate("ddr3_axi_s0_aclk", "matrix_aclk", CLK_EN0, 18);
|
||||
clk[ZX296702_DDR3_APB_PCLK] =
|
||||
zx_gate("ddr3_apb_pclk", "main_pclk", CLK_EN0, 19);
|
||||
clk[ZX296702_DDR3_WCLK] =
|
||||
zx_gate("ddr3_wclk", "ddr_wclk_mux", CLK_EN0, 20);
|
||||
clk[ZX296702_USB20_0_AHB_HCLK] =
|
||||
zx_gate("usb20_0_ahb_hclk", "main_hclk", CLK_EN0, 21);
|
||||
clk[ZX296702_USB20_0_EXTREFCLK] =
|
||||
zx_gate("usb20_0_extrefclk", "clk_12", CLK_EN0, 22);
|
||||
clk[ZX296702_USB20_1_AHB_HCLK] =
|
||||
zx_gate("usb20_1_ahb_hclk", "main_hclk", CLK_EN0, 23);
|
||||
clk[ZX296702_USB20_1_EXTREFCLK] =
|
||||
zx_gate("usb20_1_extrefclk", "clk_12", CLK_EN0, 24);
|
||||
clk[ZX296702_USB20_2_AHB_HCLK] =
|
||||
zx_gate("usb20_2_ahb_hclk", "main_hclk", CLK_EN0, 25);
|
||||
clk[ZX296702_USB20_2_EXTREFCLK] =
|
||||
zx_gate("usb20_2_extrefclk", "clk_12", CLK_EN0, 26);
|
||||
clk[ZX296702_GMAC_AXI_M_ACLK] =
|
||||
zx_gate("gmac_axi_m_aclk", "matrix_aclk", CLK_EN0, 27);
|
||||
clk[ZX296702_GMAC_APB_PCLK] =
|
||||
zx_gate("gmac_apb_pclk", "main_pclk", CLK_EN0, 28);
|
||||
clk[ZX296702_GMAC_125_CLKIN] =
|
||||
zx_gate("gmac_125_clkin", "clk_125", CLK_EN0, 29);
|
||||
clk[ZX296702_GMAC_RMII_CLKIN] =
|
||||
zx_gate("gmac_rmii_clkin", "clk_50", CLK_EN0, 30);
|
||||
clk[ZX296702_GMAC_25M_CLK] =
|
||||
zx_gate("gmac_25M_clk", "clk_25", CLK_EN0, 31);
|
||||
clk[ZX296702_NANDFLASH_AHB_HCLK] =
|
||||
zx_gate("nandflash_ahb_hclk", "main_hclk", CLK_EN1, 0);
|
||||
clk[ZX296702_NANDFLASH_WCLK] =
|
||||
zx_gate("nandflash_wclk", "nand_wclk_mux", CLK_EN1, 1);
|
||||
clk[ZX296702_LSP0_APB_PCLK] =
|
||||
zx_gate("lsp0_apb_pclk", "main_pclk", CLK_EN1, 2);
|
||||
clk[ZX296702_LSP0_AHB_HCLK] =
|
||||
zx_gate("lsp0_ahb_hclk", "main_hclk", CLK_EN1, 3);
|
||||
clk[ZX296702_LSP0_26M_WCLK] =
|
||||
zx_gate("lsp0_26M_wclk", "lsp_26_wclk_mux", CLK_EN1, 4);
|
||||
clk[ZX296702_LSP0_104M_WCLK] =
|
||||
zx_gate("lsp0_104M_wclk", "pll_lsp_104M", CLK_EN1, 5);
|
||||
clk[ZX296702_LSP0_16M384_WCLK] =
|
||||
zx_gate("lsp0_16M384_wclk", "clk_16M384", CLK_EN1, 6);
|
||||
clk[ZX296702_LSP1_APB_PCLK] =
|
||||
zx_gate("lsp1_apb_pclk", "main_pclk", CLK_EN1, 7);
|
||||
/* FIXME: wclk enable bit is bit8. We hack it as reserved 31 for
|
||||
* UART does not work after parent clk is disabled/enabled */
|
||||
clk[ZX296702_LSP1_26M_WCLK] =
|
||||
zx_gate("lsp1_26M_wclk", "lsp_26_wclk_mux", CLK_EN1, 31);
|
||||
clk[ZX296702_LSP1_104M_WCLK] =
|
||||
zx_gate("lsp1_104M_wclk", "pll_lsp_104M", CLK_EN1, 9);
|
||||
clk[ZX296702_LSP1_32K_CLK] =
|
||||
zx_gate("lsp1_32K_clk", "clk_32K768", CLK_EN1, 10);
|
||||
clk[ZX296702_AON_HCLK] =
|
||||
zx_gate("aon_hclk", "main_hclk", CLK_EN1, 11);
|
||||
clk[ZX296702_SYS_CTRL_PCLK] =
|
||||
zx_gate("sys_ctrl_pclk", "main_pclk", CLK_EN1, 12);
|
||||
clk[ZX296702_DMA_PCLK] =
|
||||
zx_gate("dma_pclk", "main_pclk", CLK_EN1, 13);
|
||||
clk[ZX296702_DMA_ACLK] =
|
||||
zx_gate("dma_aclk", "matrix_aclk", CLK_EN1, 14);
|
||||
clk[ZX296702_SEC_HCLK] =
|
||||
zx_gate("sec_hclk", "main_hclk", CLK_EN1, 15);
|
||||
clk[ZX296702_AES_WCLK] =
|
||||
zx_gate("aes_wclk", "sec_wclk_div", CLK_EN1, 16);
|
||||
clk[ZX296702_DES_WCLK] =
|
||||
zx_gate("des_wclk", "sec_wclk_div", CLK_EN1, 17);
|
||||
clk[ZX296702_IRAM_ACLK] =
|
||||
zx_gate("iram_aclk", "matrix_aclk", CLK_EN1, 18);
|
||||
clk[ZX296702_IROM_ACLK] =
|
||||
zx_gate("irom_aclk", "matrix_aclk", CLK_EN1, 19);
|
||||
clk[ZX296702_BOOT_CTRL_HCLK] =
|
||||
zx_gate("boot_ctrl_hclk", "main_hclk", CLK_EN1, 20);
|
||||
clk[ZX296702_EFUSE_CLK_30] =
|
||||
zx_gate("efuse_clk_30", "osc", CLK_EN1, 21);
|
||||
|
||||
/* TODO: add VOU Local clocks */
|
||||
clk[ZX296702_VOU_MAIN_CHANNEL_DIV] =
|
||||
zx_div("vou_main_channel_div", "vou_main_channel_wclk",
|
||||
VOU_LOCAL_DIV2_SET, 1, 1);
|
||||
clk[ZX296702_VOU_AUX_CHANNEL_DIV] =
|
||||
zx_div("vou_aux_channel_div", "vou_aux_channel_wclk",
|
||||
VOU_LOCAL_DIV2_SET, 0, 1);
|
||||
clk[ZX296702_VOU_TV_ENC_HD_DIV] =
|
||||
zx_div("vou_tv_enc_hd_div", "vou_tv_enc_hd_mux",
|
||||
VOU_LOCAL_DIV2_SET, 3, 1);
|
||||
clk[ZX296702_VOU_TV_ENC_SD_DIV] =
|
||||
zx_div("vou_tv_enc_sd_div", "vou_tv_enc_sd_mux",
|
||||
VOU_LOCAL_DIV2_SET, 2, 1);
|
||||
clk[ZX296702_VL0_MUX] =
|
||||
zx_mux("vl0_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 8, 1);
|
||||
clk[ZX296702_VL1_MUX] =
|
||||
zx_mux("vl1_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 9, 1);
|
||||
clk[ZX296702_VL2_MUX] =
|
||||
zx_mux("vl2_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 10, 1);
|
||||
clk[ZX296702_GL0_MUX] =
|
||||
zx_mux("gl0_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 5, 1);
|
||||
clk[ZX296702_GL1_MUX] =
|
||||
zx_mux("gl1_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 6, 1);
|
||||
clk[ZX296702_GL2_MUX] =
|
||||
zx_mux("gl2_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 7, 1);
|
||||
clk[ZX296702_WB_MUX] =
|
||||
zx_mux("wb_mux", vl0_sel, ARRAY_SIZE(vl0_sel),
|
||||
VOU_LOCAL_CLKSEL, 11, 1);
|
||||
clk[ZX296702_HDMI_MUX] =
|
||||
zx_mux("hdmi_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
|
||||
VOU_LOCAL_CLKSEL, 4, 1);
|
||||
clk[ZX296702_VOU_TV_ENC_HD_MUX] =
|
||||
zx_mux("vou_tv_enc_hd_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
|
||||
VOU_LOCAL_CLKSEL, 3, 1);
|
||||
clk[ZX296702_VOU_TV_ENC_SD_MUX] =
|
||||
zx_mux("vou_tv_enc_sd_mux", hdmi_sel, ARRAY_SIZE(hdmi_sel),
|
||||
VOU_LOCAL_CLKSEL, 2, 1);
|
||||
clk[ZX296702_VL0_CLK] =
|
||||
zx_gate("vl0_clk", "vl0_mux", VOU_LOCAL_CLKEN, 8);
|
||||
clk[ZX296702_VL1_CLK] =
|
||||
zx_gate("vl1_clk", "vl1_mux", VOU_LOCAL_CLKEN, 9);
|
||||
clk[ZX296702_VL2_CLK] =
|
||||
zx_gate("vl2_clk", "vl2_mux", VOU_LOCAL_CLKEN, 10);
|
||||
clk[ZX296702_GL0_CLK] =
|
||||
zx_gate("gl0_clk", "gl0_mux", VOU_LOCAL_CLKEN, 5);
|
||||
clk[ZX296702_GL1_CLK] =
|
||||
zx_gate("gl1_clk", "gl1_mux", VOU_LOCAL_CLKEN, 6);
|
||||
clk[ZX296702_GL2_CLK] =
|
||||
zx_gate("gl2_clk", "gl2_mux", VOU_LOCAL_CLKEN, 7);
|
||||
clk[ZX296702_WB_CLK] =
|
||||
zx_gate("wb_clk", "wb_mux", VOU_LOCAL_CLKEN, 11);
|
||||
clk[ZX296702_CL_CLK] =
|
||||
zx_gate("cl_clk", "vou_main_channel_div", VOU_LOCAL_CLKEN, 12);
|
||||
clk[ZX296702_MAIN_MIX_CLK] =
|
||||
zx_gate("main_mix_clk", "vou_main_channel_div",
|
||||
VOU_LOCAL_CLKEN, 4);
|
||||
clk[ZX296702_AUX_MIX_CLK] =
|
||||
zx_gate("aux_mix_clk", "vou_aux_channel_div",
|
||||
VOU_LOCAL_CLKEN, 3);
|
||||
clk[ZX296702_HDMI_CLK] =
|
||||
zx_gate("hdmi_clk", "hdmi_mux", VOU_LOCAL_CLKEN, 2);
|
||||
clk[ZX296702_VOU_TV_ENC_HD_DAC_CLK] =
|
||||
zx_gate("vou_tv_enc_hd_dac_clk", "vou_tv_enc_hd_div",
|
||||
VOU_LOCAL_CLKEN, 1);
|
||||
clk[ZX296702_VOU_TV_ENC_SD_DAC_CLK] =
|
||||
zx_gate("vou_tv_enc_sd_dac_clk", "vou_tv_enc_sd_div",
|
||||
VOU_LOCAL_CLKEN, 0);
|
||||
|
||||
/* CA9 PERIPHCLK = a9_wclk / 2 */
|
||||
clk[ZX296702_A9_PERIPHCLK] =
|
||||
clk_register_fixed_factor(NULL, "a9_periphclk", "a9_wclk",
|
||||
0, 1, 2);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(topclk); i++) {
|
||||
if (IS_ERR(clk[i])) {
|
||||
pr_err("zx296702 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
topclk_data.clks = topclk;
|
||||
topclk_data.clk_num = ARRAY_SIZE(topclk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &topclk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(zx296702_top_clk, "zte,zx296702-topcrm-clk",
|
||||
zx296702_top_clocks_init);
|
||||
|
||||
static void __init zx296702_lsp0_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct clk **clk = lsp0clk;
|
||||
int i;
|
||||
|
||||
lsp0crpm_base = of_iomap(np, 0);
|
||||
WARN_ON(!lsp0crpm_base);
|
||||
|
||||
/* SDMMC1 */
|
||||
clk[ZX296702_SDMMC1_WCLK_MUX] =
|
||||
zx_mux("sdmmc1_wclk_mux", sdmmc1_wclk_sel,
|
||||
ARRAY_SIZE(sdmmc1_wclk_sel), CLK_SDMMC1, 4, 1);
|
||||
clk[ZX296702_SDMMC1_WCLK_DIV] =
|
||||
zx_div("sdmmc1_wclk_div", "sdmmc1_wclk_mux", CLK_SDMMC1, 12, 4);
|
||||
clk[ZX296702_SDMMC1_WCLK] =
|
||||
zx_gate("sdmmc1_wclk", "sdmmc1_wclk_div", CLK_SDMMC1, 1);
|
||||
clk[ZX296702_SDMMC1_PCLK] =
|
||||
zx_gate("sdmmc1_pclk", "lsp0_apb_pclk", CLK_SDMMC1, 0);
|
||||
|
||||
clk[ZX296702_GPIO_CLK] =
|
||||
zx_gate("gpio_clk", "lsp0_apb_pclk", CLK_GPIO, 0);
|
||||
|
||||
/* SPDIF */
|
||||
clk[ZX296702_SPDIF0_WCLK_MUX] =
|
||||
zx_mux("spdif0_wclk_mux", spdif0_wclk_sel,
|
||||
ARRAY_SIZE(spdif0_wclk_sel), CLK_SPDIF0, 4, 1);
|
||||
clk[ZX296702_SPDIF0_WCLK] =
|
||||
zx_gate("spdif0_wclk", "spdif0_wclk_mux", CLK_SPDIF0, 1);
|
||||
clk[ZX296702_SPDIF0_PCLK] =
|
||||
zx_gate("spdif0_pclk", "lsp0_apb_pclk", CLK_SPDIF0, 0);
|
||||
|
||||
clk[ZX296702_SPDIF0_DIV] =
|
||||
clk_register_zx_audio("spdif0_div", "spdif0_wclk", 0,
|
||||
SPDIF0_DIV);
|
||||
|
||||
/* I2S */
|
||||
clk[ZX296702_I2S0_WCLK_MUX] =
|
||||
zx_mux("i2s0_wclk_mux", i2s_wclk_sel,
|
||||
ARRAY_SIZE(i2s_wclk_sel), CLK_I2S0, 4, 1);
|
||||
clk[ZX296702_I2S0_WCLK] =
|
||||
zx_gate("i2s0_wclk", "i2s0_wclk_mux", CLK_I2S0, 1);
|
||||
clk[ZX296702_I2S0_PCLK] =
|
||||
zx_gate("i2s0_pclk", "lsp0_apb_pclk", CLK_I2S0, 0);
|
||||
|
||||
clk[ZX296702_I2S0_DIV] =
|
||||
clk_register_zx_audio("i2s0_div", "i2s0_wclk", 0, I2S0_DIV);
|
||||
|
||||
clk[ZX296702_I2S1_WCLK_MUX] =
|
||||
zx_mux("i2s1_wclk_mux", i2s_wclk_sel,
|
||||
ARRAY_SIZE(i2s_wclk_sel), CLK_I2S1, 4, 1);
|
||||
clk[ZX296702_I2S1_WCLK] =
|
||||
zx_gate("i2s1_wclk", "i2s1_wclk_mux", CLK_I2S1, 1);
|
||||
clk[ZX296702_I2S1_PCLK] =
|
||||
zx_gate("i2s1_pclk", "lsp0_apb_pclk", CLK_I2S1, 0);
|
||||
|
||||
clk[ZX296702_I2S1_DIV] =
|
||||
clk_register_zx_audio("i2s1_div", "i2s1_wclk", 0, I2S1_DIV);
|
||||
|
||||
clk[ZX296702_I2S2_WCLK_MUX] =
|
||||
zx_mux("i2s2_wclk_mux", i2s_wclk_sel,
|
||||
ARRAY_SIZE(i2s_wclk_sel), CLK_I2S2, 4, 1);
|
||||
clk[ZX296702_I2S2_WCLK] =
|
||||
zx_gate("i2s2_wclk", "i2s2_wclk_mux", CLK_I2S2, 1);
|
||||
clk[ZX296702_I2S2_PCLK] =
|
||||
zx_gate("i2s2_pclk", "lsp0_apb_pclk", CLK_I2S2, 0);
|
||||
|
||||
clk[ZX296702_I2S2_DIV] =
|
||||
clk_register_zx_audio("i2s2_div", "i2s2_wclk", 0, I2S2_DIV);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lsp0clk); i++) {
|
||||
if (IS_ERR(clk[i])) {
|
||||
pr_err("zx296702 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
lsp0clk_data.clks = lsp0clk;
|
||||
lsp0clk_data.clk_num = ARRAY_SIZE(lsp0clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &lsp0clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(zx296702_lsp0_clk, "zte,zx296702-lsp0crpm-clk",
|
||||
zx296702_lsp0_clocks_init);
|
||||
|
||||
static void __init zx296702_lsp1_clocks_init(struct device_node *np)
|
||||
{
|
||||
struct clk **clk = lsp1clk;
|
||||
int i;
|
||||
|
||||
lsp1crpm_base = of_iomap(np, 0);
|
||||
WARN_ON(!lsp1crpm_base);
|
||||
|
||||
/* UART0 */
|
||||
clk[ZX296702_UART0_WCLK_MUX] =
|
||||
zx_mux("uart0_wclk_mux", uart_wclk_sel,
|
||||
ARRAY_SIZE(uart_wclk_sel), CLK_UART0, 4, 1);
|
||||
/* FIXME: uart wclk enable bit is bit1 in. We hack it as reserved 31 for
|
||||
* UART does not work after parent clk is disabled/enabled */
|
||||
clk[ZX296702_UART0_WCLK] =
|
||||
zx_gate("uart0_wclk", "uart0_wclk_mux", CLK_UART0, 31);
|
||||
clk[ZX296702_UART0_PCLK] =
|
||||
zx_gate("uart0_pclk", "lsp1_apb_pclk", CLK_UART0, 0);
|
||||
|
||||
/* UART1 */
|
||||
clk[ZX296702_UART1_WCLK_MUX] =
|
||||
zx_mux("uart1_wclk_mux", uart_wclk_sel,
|
||||
ARRAY_SIZE(uart_wclk_sel), CLK_UART1, 4, 1);
|
||||
clk[ZX296702_UART1_WCLK] =
|
||||
zx_gate("uart1_wclk", "uart1_wclk_mux", CLK_UART1, 1);
|
||||
clk[ZX296702_UART1_PCLK] =
|
||||
zx_gate("uart1_pclk", "lsp1_apb_pclk", CLK_UART1, 0);
|
||||
|
||||
/* SDMMC0 */
|
||||
clk[ZX296702_SDMMC0_WCLK_MUX] =
|
||||
zx_mux("sdmmc0_wclk_mux", sdmmc0_wclk_sel,
|
||||
ARRAY_SIZE(sdmmc0_wclk_sel), CLK_SDMMC0, 4, 1);
|
||||
clk[ZX296702_SDMMC0_WCLK_DIV] =
|
||||
zx_div("sdmmc0_wclk_div", "sdmmc0_wclk_mux", CLK_SDMMC0, 12, 4);
|
||||
clk[ZX296702_SDMMC0_WCLK] =
|
||||
zx_gate("sdmmc0_wclk", "sdmmc0_wclk_div", CLK_SDMMC0, 1);
|
||||
clk[ZX296702_SDMMC0_PCLK] =
|
||||
zx_gate("sdmmc0_pclk", "lsp1_apb_pclk", CLK_SDMMC0, 0);
|
||||
|
||||
clk[ZX296702_SPDIF1_WCLK_MUX] =
|
||||
zx_mux("spdif1_wclk_mux", spdif1_wclk_sel,
|
||||
ARRAY_SIZE(spdif1_wclk_sel), CLK_SPDIF1, 4, 1);
|
||||
clk[ZX296702_SPDIF1_WCLK] =
|
||||
zx_gate("spdif1_wclk", "spdif1_wclk_mux", CLK_SPDIF1, 1);
|
||||
clk[ZX296702_SPDIF1_PCLK] =
|
||||
zx_gate("spdif1_pclk", "lsp1_apb_pclk", CLK_SPDIF1, 0);
|
||||
|
||||
clk[ZX296702_SPDIF1_DIV] =
|
||||
clk_register_zx_audio("spdif1_div", "spdif1_wclk", 0,
|
||||
SPDIF1_DIV);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lsp1clk); i++) {
|
||||
if (IS_ERR(clk[i])) {
|
||||
pr_err("zx296702 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
lsp1clk_data.clks = lsp1clk;
|
||||
lsp1clk_data.clk_num = ARRAY_SIZE(lsp1clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &lsp1clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(zx296702_lsp1_clk, "zte,zx296702-lsp1crpm-clk",
|
||||
zx296702_lsp1_clocks_init);
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,446 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright 2014 Linaro Ltd.
|
||||
* Copyright (C) 2014 ZTE Corporation.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/gcd.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/div64.h>
|
||||
|
||||
#include "clk.h"
|
||||
|
||||
#define to_clk_zx_pll(_hw) container_of(_hw, struct clk_zx_pll, hw)
|
||||
#define to_clk_zx_audio(_hw) container_of(_hw, struct clk_zx_audio, hw)
|
||||
|
||||
#define CFG0_CFG1_OFFSET 4
|
||||
#define LOCK_FLAG 30
|
||||
#define POWER_DOWN 31
|
||||
|
||||
static int rate_to_idx(struct clk_zx_pll *zx_pll, unsigned long rate)
|
||||
{
|
||||
const struct zx_pll_config *config = zx_pll->lookup_table;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < zx_pll->count; i++) {
|
||||
if (config[i].rate > rate)
|
||||
return i > 0 ? i - 1 : 0;
|
||||
|
||||
if (config[i].rate == rate)
|
||||
return i;
|
||||
}
|
||||
|
||||
return i - 1;
|
||||
}
|
||||
|
||||
static int hw_to_idx(struct clk_zx_pll *zx_pll)
|
||||
{
|
||||
const struct zx_pll_config *config = zx_pll->lookup_table;
|
||||
u32 hw_cfg0, hw_cfg1;
|
||||
int i;
|
||||
|
||||
hw_cfg0 = readl_relaxed(zx_pll->reg_base);
|
||||
hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET);
|
||||
|
||||
/* For matching the value in lookup table */
|
||||
hw_cfg0 &= ~BIT(zx_pll->lock_bit);
|
||||
|
||||
/* Check availability of pd_bit */
|
||||
if (zx_pll->pd_bit < 32)
|
||||
hw_cfg0 |= BIT(zx_pll->pd_bit);
|
||||
|
||||
for (i = 0; i < zx_pll->count; i++) {
|
||||
if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1)
|
||||
return i;
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static unsigned long zx_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
|
||||
int idx;
|
||||
|
||||
idx = hw_to_idx(zx_pll);
|
||||
if (unlikely(idx == -EINVAL))
|
||||
return 0;
|
||||
|
||||
return zx_pll->lookup_table[idx].rate;
|
||||
}
|
||||
|
||||
static long zx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
|
||||
int idx;
|
||||
|
||||
idx = rate_to_idx(zx_pll, rate);
|
||||
|
||||
return zx_pll->lookup_table[idx].rate;
|
||||
}
|
||||
|
||||
static int zx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
/* Assume current cpu is not running on current PLL */
|
||||
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
|
||||
const struct zx_pll_config *config;
|
||||
int idx;
|
||||
|
||||
idx = rate_to_idx(zx_pll, rate);
|
||||
config = &zx_pll->lookup_table[idx];
|
||||
|
||||
writel_relaxed(config->cfg0, zx_pll->reg_base);
|
||||
writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int zx_pll_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
|
||||
u32 reg;
|
||||
|
||||
/* If pd_bit is not available, simply return success. */
|
||||
if (zx_pll->pd_bit > 31)
|
||||
return 0;
|
||||
|
||||
reg = readl_relaxed(zx_pll->reg_base);
|
||||
writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base);
|
||||
|
||||
return readl_relaxed_poll_timeout(zx_pll->reg_base, reg,
|
||||
reg & BIT(zx_pll->lock_bit), 0, 100);
|
||||
}
|
||||
|
||||
static void zx_pll_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
|
||||
u32 reg;
|
||||
|
||||
if (zx_pll->pd_bit > 31)
|
||||
return;
|
||||
|
||||
reg = readl_relaxed(zx_pll->reg_base);
|
||||
writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base);
|
||||
}
|
||||
|
||||
static int zx_pll_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
|
||||
u32 reg;
|
||||
|
||||
reg = readl_relaxed(zx_pll->reg_base);
|
||||
|
||||
return !(reg & BIT(zx_pll->pd_bit));
|
||||
}
|
||||
|
||||
const struct clk_ops zx_pll_ops = {
|
||||
.recalc_rate = zx_pll_recalc_rate,
|
||||
.round_rate = zx_pll_round_rate,
|
||||
.set_rate = zx_pll_set_rate,
|
||||
.enable = zx_pll_enable,
|
||||
.disable = zx_pll_disable,
|
||||
.is_enabled = zx_pll_is_enabled,
|
||||
};
|
||||
EXPORT_SYMBOL(zx_pll_ops);
|
||||
|
||||
struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
|
||||
unsigned long flags, void __iomem *reg_base,
|
||||
const struct zx_pll_config *lookup_table,
|
||||
int count, spinlock_t *lock)
|
||||
{
|
||||
struct clk_zx_pll *zx_pll;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
zx_pll = kzalloc(sizeof(*zx_pll), GFP_KERNEL);
|
||||
if (!zx_pll)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &zx_pll_ops;
|
||||
init.flags = flags;
|
||||
init.parent_names = parent_name ? &parent_name : NULL;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
|
||||
zx_pll->reg_base = reg_base;
|
||||
zx_pll->lookup_table = lookup_table;
|
||||
zx_pll->count = count;
|
||||
zx_pll->lock_bit = LOCK_FLAG;
|
||||
zx_pll->pd_bit = POWER_DOWN;
|
||||
zx_pll->lock = lock;
|
||||
zx_pll->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &zx_pll->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(zx_pll);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
#define BPAR 1000000
|
||||
static u32 calc_reg(u32 parent_rate, u32 rate)
|
||||
{
|
||||
u32 sel, integ, fra_div, tmp;
|
||||
u64 tmp64 = (u64)parent_rate * BPAR;
|
||||
|
||||
do_div(tmp64, rate);
|
||||
integ = (u32)tmp64 / BPAR;
|
||||
integ = integ >> 1;
|
||||
|
||||
tmp = (u32)tmp64 % BPAR;
|
||||
sel = tmp / BPAR;
|
||||
|
||||
tmp = tmp % BPAR;
|
||||
fra_div = tmp * 0xff / BPAR;
|
||||
tmp = (sel << 24) | (integ << 16) | (0xff << 8) | fra_div;
|
||||
|
||||
/* Set I2S integer divider as 1. This bit is reserved for SPDIF
|
||||
* and do no harm.
|
||||
*/
|
||||
tmp |= BIT(28);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
static u32 calc_rate(u32 reg, u32 parent_rate)
|
||||
{
|
||||
u32 sel, integ, fra_div, tmp;
|
||||
u64 tmp64 = (u64)parent_rate * BPAR;
|
||||
|
||||
tmp = reg;
|
||||
sel = (tmp >> 24) & BIT(0);
|
||||
integ = (tmp >> 16) & 0xff;
|
||||
fra_div = tmp & 0xff;
|
||||
|
||||
tmp = fra_div * BPAR;
|
||||
tmp = tmp / 0xff;
|
||||
tmp += sel * BPAR;
|
||||
tmp += 2 * integ * BPAR;
|
||||
do_div(tmp64, tmp);
|
||||
|
||||
return (u32)tmp64;
|
||||
}
|
||||
|
||||
static unsigned long zx_audio_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
|
||||
u32 reg;
|
||||
|
||||
reg = readl_relaxed(zx_audio->reg_base);
|
||||
return calc_rate(reg, parent_rate);
|
||||
}
|
||||
|
||||
static long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
if (rate * 2 > *prate)
|
||||
return -EINVAL;
|
||||
|
||||
reg = calc_reg(*prate, rate);
|
||||
return calc_rate(reg, *prate);
|
||||
}
|
||||
|
||||
static int zx_audio_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
|
||||
u32 reg;
|
||||
|
||||
reg = calc_reg(parent_rate, rate);
|
||||
writel_relaxed(reg, zx_audio->reg_base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define ZX_AUDIO_EN BIT(25)
|
||||
static int zx_audio_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
|
||||
u32 reg;
|
||||
|
||||
reg = readl_relaxed(zx_audio->reg_base);
|
||||
writel_relaxed(reg & ~ZX_AUDIO_EN, zx_audio->reg_base);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void zx_audio_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_zx_audio *zx_audio = to_clk_zx_audio(hw);
|
||||
u32 reg;
|
||||
|
||||
reg = readl_relaxed(zx_audio->reg_base);
|
||||
writel_relaxed(reg | ZX_AUDIO_EN, zx_audio->reg_base);
|
||||
}
|
||||
|
||||
static const struct clk_ops zx_audio_ops = {
|
||||
.recalc_rate = zx_audio_recalc_rate,
|
||||
.round_rate = zx_audio_round_rate,
|
||||
.set_rate = zx_audio_set_rate,
|
||||
.enable = zx_audio_enable,
|
||||
.disable = zx_audio_disable,
|
||||
};
|
||||
|
||||
struct clk *clk_register_zx_audio(const char *name,
|
||||
const char * const parent_name,
|
||||
unsigned long flags,
|
||||
void __iomem *reg_base)
|
||||
{
|
||||
struct clk_zx_audio *zx_audio;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
|
||||
zx_audio = kzalloc(sizeof(*zx_audio), GFP_KERNEL);
|
||||
if (!zx_audio)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &zx_audio_ops;
|
||||
init.flags = flags;
|
||||
init.parent_names = parent_name ? &parent_name : NULL;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
|
||||
zx_audio->reg_base = reg_base;
|
||||
zx_audio->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &zx_audio->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(zx_audio);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
#define CLK_AUDIO_DIV_FRAC BIT(0)
|
||||
#define CLK_AUDIO_DIV_INT BIT(1)
|
||||
#define CLK_AUDIO_DIV_UNCOMMON BIT(1)
|
||||
|
||||
#define CLK_AUDIO_DIV_FRAC_NSHIFT 16
|
||||
#define CLK_AUDIO_DIV_INT_FRAC_RE BIT(16)
|
||||
#define CLK_AUDIO_DIV_INT_FRAC_MAX (0xffff)
|
||||
#define CLK_AUDIO_DIV_INT_FRAC_MIN (0x2)
|
||||
#define CLK_AUDIO_DIV_INT_INT_SHIFT 24
|
||||
#define CLK_AUDIO_DIV_INT_INT_WIDTH 4
|
||||
|
||||
struct zx_clk_audio_div_table {
|
||||
unsigned long rate;
|
||||
unsigned int int_reg;
|
||||
unsigned int frac_reg;
|
||||
};
|
||||
|
||||
#define to_clk_zx_audio_div(_hw) container_of(_hw, struct clk_zx_audio_divider, hw)
|
||||
|
||||
static unsigned long audio_calc_rate(struct clk_zx_audio_divider *audio_div,
|
||||
u32 reg_frac, u32 reg_int,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long rate, m, n;
|
||||
|
||||
m = reg_frac & 0xffff;
|
||||
n = (reg_frac >> 16) & 0xffff;
|
||||
|
||||
m = (reg_int & 0xffff) * n + m;
|
||||
rate = (parent_rate * n) / m;
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static void audio_calc_reg(struct clk_zx_audio_divider *audio_div,
|
||||
struct zx_clk_audio_div_table *div_table,
|
||||
unsigned long rate, unsigned long parent_rate)
|
||||
{
|
||||
unsigned int reg_int, reg_frac;
|
||||
unsigned long m, n, div;
|
||||
|
||||
reg_int = parent_rate / rate;
|
||||
|
||||
if (reg_int > CLK_AUDIO_DIV_INT_FRAC_MAX)
|
||||
reg_int = CLK_AUDIO_DIV_INT_FRAC_MAX;
|
||||
else if (reg_int < CLK_AUDIO_DIV_INT_FRAC_MIN)
|
||||
reg_int = 0;
|
||||
m = parent_rate - rate * reg_int;
|
||||
n = rate;
|
||||
|
||||
div = gcd(m, n);
|
||||
m = m / div;
|
||||
n = n / div;
|
||||
|
||||
if ((m >> 16) || (n >> 16)) {
|
||||
if (m > n) {
|
||||
n = n * 0xffff / m;
|
||||
m = 0xffff;
|
||||
} else {
|
||||
m = m * 0xffff / n;
|
||||
n = 0xffff;
|
||||
}
|
||||
}
|
||||
reg_frac = m | (n << 16);
|
||||
|
||||
div_table->rate = parent_rate * n / (reg_int * n + m);
|
||||
div_table->int_reg = reg_int;
|
||||
div_table->frac_reg = reg_frac;
|
||||
}
|
||||
|
||||
static unsigned long zx_audio_div_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
|
||||
u32 reg_frac, reg_int;
|
||||
|
||||
reg_frac = readl_relaxed(zx_audio_div->reg_base);
|
||||
reg_int = readl_relaxed(zx_audio_div->reg_base + 0x4);
|
||||
|
||||
return audio_calc_rate(zx_audio_div, reg_frac, reg_int, parent_rate);
|
||||
}
|
||||
|
||||
static long zx_audio_div_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
|
||||
struct zx_clk_audio_div_table divt;
|
||||
|
||||
audio_calc_reg(zx_audio_div, &divt, rate, *prate);
|
||||
|
||||
return audio_calc_rate(zx_audio_div, divt.frac_reg, divt.int_reg, *prate);
|
||||
}
|
||||
|
||||
static int zx_audio_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
|
||||
struct zx_clk_audio_div_table divt;
|
||||
unsigned int val;
|
||||
|
||||
audio_calc_reg(zx_audio_div, &divt, rate, parent_rate);
|
||||
if (divt.rate != rate)
|
||||
pr_debug("the real rate is:%ld", divt.rate);
|
||||
|
||||
writel_relaxed(divt.frac_reg, zx_audio_div->reg_base);
|
||||
|
||||
val = readl_relaxed(zx_audio_div->reg_base + 0x4);
|
||||
val &= ~0xffff;
|
||||
val |= divt.int_reg | CLK_AUDIO_DIV_INT_FRAC_RE;
|
||||
writel_relaxed(val, zx_audio_div->reg_base + 0x4);
|
||||
|
||||
mdelay(1);
|
||||
|
||||
val = readl_relaxed(zx_audio_div->reg_base + 0x4);
|
||||
val &= ~CLK_AUDIO_DIV_INT_FRAC_RE;
|
||||
writel_relaxed(val, zx_audio_div->reg_base + 0x4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops zx_audio_div_ops = {
|
||||
.recalc_rate = zx_audio_div_recalc_rate,
|
||||
.round_rate = zx_audio_div_round_rate,
|
||||
.set_rate = zx_audio_div_set_rate,
|
||||
};
|
||||
@ -1,174 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright 2015 Linaro Ltd.
|
||||
* Copyright (C) 2014 ZTE Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __ZTE_CLK_H
|
||||
#define __ZTE_CLK_H
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#define PNAME(x) static const char *x[]
|
||||
|
||||
struct zx_pll_config {
|
||||
unsigned long rate;
|
||||
u32 cfg0;
|
||||
u32 cfg1;
|
||||
};
|
||||
|
||||
struct clk_zx_pll {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg_base;
|
||||
const struct zx_pll_config *lookup_table; /* order by rate asc */
|
||||
int count;
|
||||
spinlock_t *lock;
|
||||
u8 pd_bit; /* power down bit */
|
||||
u8 lock_bit; /* pll lock flag bit */
|
||||
};
|
||||
|
||||
#define PLL_RATE(_rate, _cfg0, _cfg1) \
|
||||
{ \
|
||||
.rate = _rate, \
|
||||
.cfg0 = _cfg0, \
|
||||
.cfg1 = _cfg1, \
|
||||
}
|
||||
|
||||
#define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \
|
||||
{ \
|
||||
.reg_base = (void __iomem *) _reg, \
|
||||
.lookup_table = _table, \
|
||||
.count = ARRAY_SIZE(_table), \
|
||||
.pd_bit = _pd, \
|
||||
.lock_bit = _lock, \
|
||||
.hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
|
||||
CLK_GET_RATE_NOCACHE), \
|
||||
}
|
||||
|
||||
/*
|
||||
* The pd_bit is not available on ZX296718, so let's pass something
|
||||
* bigger than 31, e.g. 0xff, to indicate that.
|
||||
*/
|
||||
#define ZX296718_PLL(_name, _parent, _reg, _table) \
|
||||
ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
|
||||
|
||||
struct zx_clk_gate {
|
||||
struct clk_gate gate;
|
||||
u16 id;
|
||||
};
|
||||
|
||||
#define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \
|
||||
{ \
|
||||
.gate = { \
|
||||
.reg = (void __iomem *) _reg, \
|
||||
.bit_idx = (_bit), \
|
||||
.flags = _gflags, \
|
||||
.lock = &clk_lock, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&clk_gate_ops, \
|
||||
_flag | CLK_IGNORE_UNUSED), \
|
||||
}, \
|
||||
.id = _id, \
|
||||
}
|
||||
|
||||
struct zx_clk_fixed_factor {
|
||||
struct clk_fixed_factor factor;
|
||||
u16 id;
|
||||
};
|
||||
|
||||
#define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \
|
||||
{ \
|
||||
.factor = { \
|
||||
.div = _div, \
|
||||
.mult = _mult, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&clk_fixed_factor_ops, \
|
||||
_flag), \
|
||||
}, \
|
||||
.id = _id, \
|
||||
}
|
||||
|
||||
struct zx_clk_mux {
|
||||
struct clk_mux mux;
|
||||
u16 id;
|
||||
};
|
||||
|
||||
#define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \
|
||||
{ \
|
||||
.mux = { \
|
||||
.reg = (void __iomem *) _reg, \
|
||||
.mask = BIT(_width) - 1, \
|
||||
.shift = _shift, \
|
||||
.flags = _mflag, \
|
||||
.lock = &clk_lock, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS(_name, \
|
||||
_parent, \
|
||||
&clk_mux_ops, \
|
||||
_flag), \
|
||||
}, \
|
||||
.id = _id, \
|
||||
}
|
||||
|
||||
#define MUX(_id, _name, _parent, _reg, _shift, _width) \
|
||||
MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
|
||||
|
||||
struct zx_clk_div {
|
||||
struct clk_divider div;
|
||||
u16 id;
|
||||
};
|
||||
|
||||
#define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \
|
||||
{ \
|
||||
.div = { \
|
||||
.reg = (void __iomem *) _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.flags = 0, \
|
||||
.table = _table, \
|
||||
.lock = &clk_lock, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&clk_divider_ops, \
|
||||
_flag), \
|
||||
}, \
|
||||
.id = _id, \
|
||||
}
|
||||
|
||||
struct clk_zx_audio_divider {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg_base;
|
||||
unsigned int rate_count;
|
||||
spinlock_t *lock;
|
||||
u16 id;
|
||||
};
|
||||
|
||||
#define AUDIO_DIV(_id, _name, _parent, _reg) \
|
||||
{ \
|
||||
.reg_base = (void __iomem *) _reg, \
|
||||
.lock = &clk_lock, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&zx_audio_div_ops, \
|
||||
0), \
|
||||
.id = _id, \
|
||||
}
|
||||
|
||||
struct clk *clk_register_zx_pll(const char *name, const char *parent_name,
|
||||
unsigned long flags, void __iomem *reg_base,
|
||||
const struct zx_pll_config *lookup_table, int count, spinlock_t *lock);
|
||||
|
||||
struct clk_zx_audio {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg_base;
|
||||
};
|
||||
|
||||
struct clk *clk_register_zx_audio(const char *name,
|
||||
const char * const parent_name,
|
||||
unsigned long flags, void __iomem *reg_base);
|
||||
|
||||
extern const struct clk_ops zx_pll_ops;
|
||||
extern const struct clk_ops zx_audio_div_ops;
|
||||
|
||||
#endif
|
||||
@ -1,180 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright 2014 Linaro Ltd.
|
||||
* Copyright (C) 2014 ZTE Corporation.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_ZX296702_H
|
||||
#define __DT_BINDINGS_CLOCK_ZX296702_H
|
||||
|
||||
#define ZX296702_OSC 0
|
||||
#define ZX296702_PLL_A9 1
|
||||
#define ZX296702_PLL_A9_350M 2
|
||||
#define ZX296702_PLL_MAC_1000M 3
|
||||
#define ZX296702_PLL_MAC_333M 4
|
||||
#define ZX296702_PLL_MM0_1188M 5
|
||||
#define ZX296702_PLL_MM0_396M 6
|
||||
#define ZX296702_PLL_MM0_198M 7
|
||||
#define ZX296702_PLL_MM1_108M 8
|
||||
#define ZX296702_PLL_MM1_72M 9
|
||||
#define ZX296702_PLL_MM1_54M 10
|
||||
#define ZX296702_PLL_LSP_104M 11
|
||||
#define ZX296702_PLL_LSP_26M 12
|
||||
#define ZX296702_PLL_AUDIO_294M912 13
|
||||
#define ZX296702_PLL_DDR_266M 14
|
||||
#define ZX296702_CLK_148M5 15
|
||||
#define ZX296702_MATRIX_ACLK 16
|
||||
#define ZX296702_MAIN_HCLK 17
|
||||
#define ZX296702_MAIN_PCLK 18
|
||||
#define ZX296702_CLK_500 19
|
||||
#define ZX296702_CLK_250 20
|
||||
#define ZX296702_CLK_125 21
|
||||
#define ZX296702_CLK_74M25 22
|
||||
#define ZX296702_A9_WCLK 23
|
||||
#define ZX296702_A9_AS1_ACLK_MUX 24
|
||||
#define ZX296702_A9_TRACE_CLKIN_MUX 25
|
||||
#define ZX296702_A9_AS1_ACLK_DIV 26
|
||||
#define ZX296702_CLK_2 27
|
||||
#define ZX296702_CLK_27 28
|
||||
#define ZX296702_DECPPU_ACLK_MUX 29
|
||||
#define ZX296702_PPU_ACLK_MUX 30
|
||||
#define ZX296702_MALI400_ACLK_MUX 31
|
||||
#define ZX296702_VOU_ACLK_MUX 32
|
||||
#define ZX296702_VOU_MAIN_WCLK_MUX 33
|
||||
#define ZX296702_VOU_AUX_WCLK_MUX 34
|
||||
#define ZX296702_VOU_SCALER_WCLK_MUX 35
|
||||
#define ZX296702_R2D_ACLK_MUX 36
|
||||
#define ZX296702_R2D_WCLK_MUX 37
|
||||
#define ZX296702_CLK_50 38
|
||||
#define ZX296702_CLK_25 39
|
||||
#define ZX296702_CLK_12 40
|
||||
#define ZX296702_CLK_16M384 41
|
||||
#define ZX296702_CLK_32K768 42
|
||||
#define ZX296702_SEC_WCLK_DIV 43
|
||||
#define ZX296702_DDR_WCLK_MUX 44
|
||||
#define ZX296702_NAND_WCLK_MUX 45
|
||||
#define ZX296702_LSP_26_WCLK_MUX 46
|
||||
#define ZX296702_A9_AS0_ACLK 47
|
||||
#define ZX296702_A9_AS1_ACLK 48
|
||||
#define ZX296702_A9_TRACE_CLKIN 49
|
||||
#define ZX296702_DECPPU_AXI_M_ACLK 50
|
||||
#define ZX296702_DECPPU_AHB_S_HCLK 51
|
||||
#define ZX296702_PPU_AXI_M_ACLK 52
|
||||
#define ZX296702_PPU_AHB_S_HCLK 53
|
||||
#define ZX296702_VOU_AXI_M_ACLK 54
|
||||
#define ZX296702_VOU_APB_PCLK 55
|
||||
#define ZX296702_VOU_MAIN_CHANNEL_WCLK 56
|
||||
#define ZX296702_VOU_AUX_CHANNEL_WCLK 57
|
||||
#define ZX296702_VOU_HDMI_OSCLK_CEC 58
|
||||
#define ZX296702_VOU_SCALER_WCLK 59
|
||||
#define ZX296702_MALI400_AXI_M_ACLK 60
|
||||
#define ZX296702_MALI400_APB_PCLK 61
|
||||
#define ZX296702_R2D_WCLK 62
|
||||
#define ZX296702_R2D_AXI_M_ACLK 63
|
||||
#define ZX296702_R2D_AHB_HCLK 64
|
||||
#define ZX296702_DDR3_AXI_S0_ACLK 65
|
||||
#define ZX296702_DDR3_APB_PCLK 66
|
||||
#define ZX296702_DDR3_WCLK 67
|
||||
#define ZX296702_USB20_0_AHB_HCLK 68
|
||||
#define ZX296702_USB20_0_EXTREFCLK 69
|
||||
#define ZX296702_USB20_1_AHB_HCLK 70
|
||||
#define ZX296702_USB20_1_EXTREFCLK 71
|
||||
#define ZX296702_USB20_2_AHB_HCLK 72
|
||||
#define ZX296702_USB20_2_EXTREFCLK 73
|
||||
#define ZX296702_GMAC_AXI_M_ACLK 74
|
||||
#define ZX296702_GMAC_APB_PCLK 75
|
||||
#define ZX296702_GMAC_125_CLKIN 76
|
||||
#define ZX296702_GMAC_RMII_CLKIN 77
|
||||
#define ZX296702_GMAC_25M_CLK 78
|
||||
#define ZX296702_NANDFLASH_AHB_HCLK 79
|
||||
#define ZX296702_NANDFLASH_WCLK 80
|
||||
#define ZX296702_LSP0_APB_PCLK 81
|
||||
#define ZX296702_LSP0_AHB_HCLK 82
|
||||
#define ZX296702_LSP0_26M_WCLK 83
|
||||
#define ZX296702_LSP0_104M_WCLK 84
|
||||
#define ZX296702_LSP0_16M384_WCLK 85
|
||||
#define ZX296702_LSP1_APB_PCLK 86
|
||||
#define ZX296702_LSP1_26M_WCLK 87
|
||||
#define ZX296702_LSP1_104M_WCLK 88
|
||||
#define ZX296702_LSP1_32K_CLK 89
|
||||
#define ZX296702_AON_HCLK 90
|
||||
#define ZX296702_SYS_CTRL_PCLK 91
|
||||
#define ZX296702_DMA_PCLK 92
|
||||
#define ZX296702_DMA_ACLK 93
|
||||
#define ZX296702_SEC_HCLK 94
|
||||
#define ZX296702_AES_WCLK 95
|
||||
#define ZX296702_DES_WCLK 96
|
||||
#define ZX296702_IRAM_ACLK 97
|
||||
#define ZX296702_IROM_ACLK 98
|
||||
#define ZX296702_BOOT_CTRL_HCLK 99
|
||||
#define ZX296702_EFUSE_CLK_30 100
|
||||
#define ZX296702_VOU_MAIN_CHANNEL_DIV 101
|
||||
#define ZX296702_VOU_AUX_CHANNEL_DIV 102
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#define ZX296702_VOU_TV_ENC_HD_DIV 103
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#define ZX296702_VOU_TV_ENC_SD_DIV 104
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#define ZX296702_VL0_MUX 105
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#define ZX296702_VL1_MUX 106
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#define ZX296702_VL2_MUX 107
|
||||
#define ZX296702_GL0_MUX 108
|
||||
#define ZX296702_GL1_MUX 109
|
||||
#define ZX296702_GL2_MUX 110
|
||||
#define ZX296702_WB_MUX 111
|
||||
#define ZX296702_HDMI_MUX 112
|
||||
#define ZX296702_VOU_TV_ENC_HD_MUX 113
|
||||
#define ZX296702_VOU_TV_ENC_SD_MUX 114
|
||||
#define ZX296702_VL0_CLK 115
|
||||
#define ZX296702_VL1_CLK 116
|
||||
#define ZX296702_VL2_CLK 117
|
||||
#define ZX296702_GL0_CLK 118
|
||||
#define ZX296702_GL1_CLK 119
|
||||
#define ZX296702_GL2_CLK 120
|
||||
#define ZX296702_WB_CLK 121
|
||||
#define ZX296702_CL_CLK 122
|
||||
#define ZX296702_MAIN_MIX_CLK 123
|
||||
#define ZX296702_AUX_MIX_CLK 124
|
||||
#define ZX296702_HDMI_CLK 125
|
||||
#define ZX296702_VOU_TV_ENC_HD_DAC_CLK 126
|
||||
#define ZX296702_VOU_TV_ENC_SD_DAC_CLK 127
|
||||
#define ZX296702_A9_PERIPHCLK 128
|
||||
#define ZX296702_TOPCLK_END 129
|
||||
|
||||
#define ZX296702_SDMMC1_WCLK_MUX 0
|
||||
#define ZX296702_SDMMC1_WCLK_DIV 1
|
||||
#define ZX296702_SDMMC1_WCLK 2
|
||||
#define ZX296702_SDMMC1_PCLK 3
|
||||
#define ZX296702_SPDIF0_WCLK_MUX 4
|
||||
#define ZX296702_SPDIF0_WCLK 5
|
||||
#define ZX296702_SPDIF0_PCLK 6
|
||||
#define ZX296702_SPDIF0_DIV 7
|
||||
#define ZX296702_I2S0_WCLK_MUX 8
|
||||
#define ZX296702_I2S0_WCLK 9
|
||||
#define ZX296702_I2S0_PCLK 10
|
||||
#define ZX296702_I2S0_DIV 11
|
||||
#define ZX296702_I2S1_WCLK_MUX 12
|
||||
#define ZX296702_I2S1_WCLK 13
|
||||
#define ZX296702_I2S1_PCLK 14
|
||||
#define ZX296702_I2S1_DIV 15
|
||||
#define ZX296702_I2S2_WCLK_MUX 16
|
||||
#define ZX296702_I2S2_WCLK 17
|
||||
#define ZX296702_I2S2_PCLK 18
|
||||
#define ZX296702_I2S2_DIV 19
|
||||
#define ZX296702_GPIO_CLK 20
|
||||
#define ZX296702_LSP0CLK_END 21
|
||||
|
||||
#define ZX296702_UART0_WCLK_MUX 0
|
||||
#define ZX296702_UART0_WCLK 1
|
||||
#define ZX296702_UART0_PCLK 2
|
||||
#define ZX296702_UART1_WCLK_MUX 3
|
||||
#define ZX296702_UART1_WCLK 4
|
||||
#define ZX296702_UART1_PCLK 5
|
||||
#define ZX296702_SDMMC0_WCLK_MUX 6
|
||||
#define ZX296702_SDMMC0_WCLK_DIV 7
|
||||
#define ZX296702_SDMMC0_WCLK 8
|
||||
#define ZX296702_SDMMC0_PCLK 9
|
||||
#define ZX296702_SPDIF1_WCLK_MUX 10
|
||||
#define ZX296702_SPDIF1_WCLK 11
|
||||
#define ZX296702_SPDIF1_PCLK 12
|
||||
#define ZX296702_SPDIF1_DIV 13
|
||||
#define ZX296702_LSP1CLK_END 14
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_ZX296702_H */
|
||||
Loading…
Reference in New Issue
Block a user