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spi: refactor spi-coldfire-qspi to use SPI queue framework.
Use the new SPI queue framework; remove use of workqueue, replace mcfqspi_transfer with mcfqspi_transfer_one_message, add mcfqspi_prepare_transfer_hw and mcfqspi_unprepare_transfer_hw, update power management routines. Signed-off-by: Steven King <sfking@fdwdc.com> Acked-by: Greg Ungerer <gerg@snapgear.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Steven King
Grant Likely
parent
5fda88f5e1
commit
bc98d13f5c
@ -25,12 +25,12 @@
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#include <linux/errno.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/workqueue.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/spi/spi.h>
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#include <linux/pm_runtime.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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@ -78,10 +78,7 @@ struct mcfqspi {
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wait_queue_head_t waitq;
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struct work_struct work;
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struct workqueue_struct *workq;
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spinlock_t lock;
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struct list_head msgq;
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struct device *dev;
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};
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static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
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@ -303,120 +300,80 @@ static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
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}
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}
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static void mcfqspi_work(struct work_struct *work)
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static int mcfqspi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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{
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struct mcfqspi *mcfqspi = container_of(work, struct mcfqspi, work);
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unsigned long flags;
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struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
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struct spi_device *spi = msg->spi;
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struct spi_transfer *t;
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int status = 0;
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spin_lock_irqsave(&mcfqspi->lock, flags);
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while (!list_empty(&mcfqspi->msgq)) {
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struct spi_message *msg;
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struct spi_device *spi;
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struct spi_transfer *xfer;
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int status = 0;
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list_for_each_entry(t, &msg->transfers, transfer_list) {
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bool cs_high = spi->mode & SPI_CS_HIGH;
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u16 qmr = MCFQSPI_QMR_MSTR;
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msg = container_of(mcfqspi->msgq.next, struct spi_message,
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queue);
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if (t->bits_per_word)
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qmr |= t->bits_per_word << 10;
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else
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qmr |= spi->bits_per_word << 10;
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if (spi->mode & SPI_CPHA)
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qmr |= MCFQSPI_QMR_CPHA;
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if (spi->mode & SPI_CPOL)
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qmr |= MCFQSPI_QMR_CPOL;
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if (t->speed_hz)
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qmr |= mcfqspi_qmr_baud(t->speed_hz);
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else
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qmr |= mcfqspi_qmr_baud(spi->max_speed_hz);
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mcfqspi_wr_qmr(mcfqspi, qmr);
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list_del_init(&msg->queue);
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spin_unlock_irqrestore(&mcfqspi->lock, flags);
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mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
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spi = msg->spi;
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mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
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if ((t->bits_per_word ? t->bits_per_word :
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spi->bits_per_word) == 8)
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mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf,
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t->rx_buf);
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else
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mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
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t->rx_buf);
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mcfqspi_wr_qir(mcfqspi, 0);
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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bool cs_high = spi->mode & SPI_CS_HIGH;
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u16 qmr = MCFQSPI_QMR_MSTR;
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if (xfer->bits_per_word)
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qmr |= xfer->bits_per_word << 10;
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else
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qmr |= spi->bits_per_word << 10;
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if (spi->mode & SPI_CPHA)
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qmr |= MCFQSPI_QMR_CPHA;
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if (spi->mode & SPI_CPOL)
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qmr |= MCFQSPI_QMR_CPOL;
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if (xfer->speed_hz)
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qmr |= mcfqspi_qmr_baud(xfer->speed_hz);
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else
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qmr |= mcfqspi_qmr_baud(spi->max_speed_hz);
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mcfqspi_wr_qmr(mcfqspi, qmr);
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mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
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mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
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if ((xfer->bits_per_word ? xfer->bits_per_word :
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spi->bits_per_word) == 8)
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mcfqspi_transfer_msg8(mcfqspi, xfer->len,
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xfer->tx_buf,
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xfer->rx_buf);
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else
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mcfqspi_transfer_msg16(mcfqspi, xfer->len / 2,
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xfer->tx_buf,
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xfer->rx_buf);
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mcfqspi_wr_qir(mcfqspi, 0);
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if (xfer->delay_usecs)
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udelay(xfer->delay_usecs);
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if (xfer->cs_change) {
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if (!list_is_last(&xfer->transfer_list,
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&msg->transfers))
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mcfqspi_cs_deselect(mcfqspi,
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spi->chip_select,
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cs_high);
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} else {
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if (list_is_last(&xfer->transfer_list,
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&msg->transfers))
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mcfqspi_cs_deselect(mcfqspi,
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spi->chip_select,
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cs_high);
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}
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msg->actual_length += xfer->len;
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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if (t->cs_change) {
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if (!list_is_last(&t->transfer_list, &msg->transfers))
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mcfqspi_cs_deselect(mcfqspi, spi->chip_select,
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cs_high);
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} else {
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if (list_is_last(&t->transfer_list, &msg->transfers))
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mcfqspi_cs_deselect(mcfqspi, spi->chip_select,
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cs_high);
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}
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msg->status = status;
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msg->complete(msg->context);
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spin_lock_irqsave(&mcfqspi->lock, flags);
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msg->actual_length += t->len;
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}
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spin_unlock_irqrestore(&mcfqspi->lock, flags);
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msg->status = status;
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spi_finalize_current_message(master);
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return status;
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}
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static int mcfqspi_transfer(struct spi_device *spi, struct spi_message *msg)
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static int mcfqspi_prepare_transfer_hw(struct spi_master *master)
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{
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struct mcfqspi *mcfqspi;
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struct spi_transfer *xfer;
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unsigned long flags;
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struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
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mcfqspi = spi_master_get_devdata(spi->master);
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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if (xfer->bits_per_word && ((xfer->bits_per_word < 8)
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|| (xfer->bits_per_word > 16))) {
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dev_dbg(&spi->dev,
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"%d bits per word is not supported\n",
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xfer->bits_per_word);
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goto fail;
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}
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if (xfer->speed_hz) {
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u32 real_speed = MCFQSPI_BUSCLK /
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mcfqspi_qmr_baud(xfer->speed_hz);
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if (real_speed != xfer->speed_hz)
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dev_dbg(&spi->dev,
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"using speed %d instead of %d\n",
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real_speed, xfer->speed_hz);
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}
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}
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msg->status = -EINPROGRESS;
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msg->actual_length = 0;
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spin_lock_irqsave(&mcfqspi->lock, flags);
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list_add_tail(&msg->queue, &mcfqspi->msgq);
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queue_work(mcfqspi->workq, &mcfqspi->work);
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spin_unlock_irqrestore(&mcfqspi->lock, flags);
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pm_runtime_get_sync(mcfqspi->dev);
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return 0;
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}
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static int mcfqspi_unprepare_transfer_hw(struct spi_master *master)
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{
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struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
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pm_runtime_put_sync(mcfqspi->dev);
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return 0;
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fail:
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msg->status = -EINVAL;
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return -EINVAL;
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}
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static int mcfqspi_setup(struct spi_device *spi)
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@ -502,21 +459,10 @@ static int __devinit mcfqspi_probe(struct platform_device *pdev)
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}
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clk_enable(mcfqspi->clk);
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mcfqspi->workq = create_singlethread_workqueue(dev_name(master->dev.parent));
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if (!mcfqspi->workq) {
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dev_dbg(&pdev->dev, "create_workqueue failed\n");
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status = -ENOMEM;
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goto fail4;
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}
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INIT_WORK(&mcfqspi->work, mcfqspi_work);
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spin_lock_init(&mcfqspi->lock);
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INIT_LIST_HEAD(&mcfqspi->msgq);
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init_waitqueue_head(&mcfqspi->waitq);
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pdata = pdev->dev.platform_data;
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if (!pdata) {
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dev_dbg(&pdev->dev, "platform data is missing\n");
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goto fail5;
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goto fail4;
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}
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master->bus_num = pdata->bus_num;
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master->num_chipselect = pdata->num_chipselect;
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@ -525,28 +471,33 @@ static int __devinit mcfqspi_probe(struct platform_device *pdev)
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status = mcfqspi_cs_setup(mcfqspi);
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if (status) {
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dev_dbg(&pdev->dev, "error initializing cs_control\n");
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goto fail5;
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goto fail4;
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}
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init_waitqueue_head(&mcfqspi->waitq);
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mcfqspi->dev = &pdev->dev;
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master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
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master->setup = mcfqspi_setup;
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master->transfer = mcfqspi_transfer;
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master->transfer_one_message = mcfqspi_transfer_one_message;
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master->prepare_transfer_hardware = mcfqspi_prepare_transfer_hw;
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master->unprepare_transfer_hardware = mcfqspi_unprepare_transfer_hw;
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platform_set_drvdata(pdev, master);
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status = spi_register_master(master);
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if (status) {
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dev_dbg(&pdev->dev, "spi_register_master failed\n");
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goto fail6;
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goto fail5;
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}
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pm_runtime_enable(mcfqspi->dev);
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dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
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return 0;
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fail6:
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mcfqspi_cs_teardown(mcfqspi);
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fail5:
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destroy_workqueue(mcfqspi->workq);
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mcfqspi_cs_teardown(mcfqspi);
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fail4:
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clk_disable(mcfqspi->clk);
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clk_put(mcfqspi->clk);
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@ -570,12 +521,12 @@ static int __devexit mcfqspi_remove(struct platform_device *pdev)
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struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pm_runtime_disable(mcfqspi->dev);
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/* disable the hardware (set the baud rate to 0) */
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mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
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platform_set_drvdata(pdev, NULL);
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mcfqspi_cs_teardown(mcfqspi);
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destroy_workqueue(mcfqspi->workq);
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clk_disable(mcfqspi->clk);
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clk_put(mcfqspi->clk);
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free_irq(mcfqspi->irq, mcfqspi);
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@ -587,11 +538,13 @@ static int __devexit mcfqspi_remove(struct platform_device *pdev)
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return 0;
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}
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#ifdef CONFIG_PM
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#ifdef CONFIG_PM_SLEEP
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static int mcfqspi_suspend(struct device *dev)
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{
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struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev));
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struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
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struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
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spi_master_suspend(master);
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clk_disable(mcfqspi->clk);
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@ -599,6 +552,29 @@ static int mcfqspi_suspend(struct device *dev)
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}
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static int mcfqspi_resume(struct device *dev)
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{
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struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
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struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
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spi_master_resume(master);
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clk_enable(mcfqspi->clk);
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return 0;
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}
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#endif
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#ifdef CONFIG_PM_RUNTIME
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static int mcfqspi_runtime_suspend(struct device *dev)
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{
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struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev));
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clk_disable(mcfqspi->clk);
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return 0;
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}
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static int mcfqspi_runtime_resume(struct device *dev)
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{
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struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev));
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@ -606,21 +582,18 @@ static int mcfqspi_resume(struct device *dev)
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return 0;
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}
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static struct dev_pm_ops mcfqspi_dev_pm_ops = {
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.suspend = mcfqspi_suspend,
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.resume = mcfqspi_resume,
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};
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#define MCFQSPI_DEV_PM_OPS (&mcfqspi_dev_pm_ops)
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#else
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#define MCFQSPI_DEV_PM_OPS NULL
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#endif
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static const struct dev_pm_ops mcfqspi_pm = {
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SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
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SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
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NULL)
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};
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static struct platform_driver mcfqspi_driver = {
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.driver.name = DRIVER_NAME,
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.driver.owner = THIS_MODULE,
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.driver.pm = MCFQSPI_DEV_PM_OPS,
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.driver.pm = &mcfqspi_pm,
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.probe = mcfqspi_probe,
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.remove = __devexit_p(mcfqspi_remove),
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};
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