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drm/amdgpu/gfx10: Enable bad opcode interrupt
For the bad opcode case, it will cause CP/ME hang. The firmware will prevent the ME side from hanging by raising a bad opcode interrupt. And the driver needs to perform a vmid reset when receiving the interrupt. v2: update irq naming (drop priv) (Alex) Acked-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -4740,6 +4740,13 @@ static int gfx_v10_0_sw_init(void *handle)
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if (r)
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return r;
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/* Bad opcode Event */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
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GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR,
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&adev->gfx.bad_op_irq);
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if (r)
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return r;
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/* Privileged reg */
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
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&adev->gfx.priv_reg_irq);
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@ -7416,6 +7423,7 @@ static int gfx_v10_0_hw_fini(void *handle)
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amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
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amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
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amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
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/* WA added for Vangogh asic fixing the SMU suspend failure
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* It needs to set power gating again during gfxoff control
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@ -7726,6 +7734,10 @@ static int gfx_v10_0_late_init(void *handle)
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if (r)
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return r;
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r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
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if (r)
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return r;
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return 0;
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}
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@ -9162,6 +9174,51 @@ static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
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return 0;
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}
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static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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u32 cp_int_cntl_reg, cp_int_cntl;
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int i, j;
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switch (state) {
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case AMDGPU_IRQ_STATE_DISABLE:
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case AMDGPU_IRQ_STATE_ENABLE:
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for (i = 0; i < adev->gfx.me.num_me; i++) {
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for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
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cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
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if (cp_int_cntl_reg) {
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cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
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cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
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OPCODE_ERROR_INT_ENABLE,
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state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
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WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
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}
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}
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}
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for (i = 0; i < adev->gfx.mec.num_mec; i++) {
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for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
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/* MECs start at 1 */
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cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
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if (cp_int_cntl_reg) {
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cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
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cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
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OPCODE_ERROR_INT_ENABLE,
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state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
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WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
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}
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}
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}
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break;
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default:
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break;
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}
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return 0;
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}
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static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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unsigned int type,
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@ -9237,6 +9294,15 @@ static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
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return 0;
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}
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static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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DRM_ERROR("Illegal opcode in command stream \n");
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gfx_v10_0_handle_priv_fault(adev, entry);
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return 0;
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}
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static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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@ -9624,6 +9690,11 @@ static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
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.process = gfx_v10_0_priv_reg_irq,
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};
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static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = {
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.set = gfx_v10_0_set_bad_op_fault_state,
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.process = gfx_v10_0_bad_op_irq,
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};
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static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
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.set = gfx_v10_0_set_priv_inst_fault_state,
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.process = gfx_v10_0_priv_inst_irq,
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@ -9645,6 +9716,9 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
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adev->gfx.priv_reg_irq.num_types = 1;
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adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
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adev->gfx.bad_op_irq.num_types = 1;
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adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs;
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adev->gfx.priv_inst_irq.num_types = 1;
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adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
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}
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