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soc: mediatek: mmsys: add MT8365 support
Add DSI mmsys connections for the MT8365 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Link: https://lore.kernel.org/r/20210519161847.3747352-3-fparent@baylibre.com [mb: take the mask field into account] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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drivers/soc/mediatek/mt8365-mmsys.h
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drivers/soc/mediatek/mt8365-mmsys.h
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@ -0,0 +1,60 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8365_MMSYS_H
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#define __SOC_MEDIATEK_MT8365_MMSYS_H
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#define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0xf3c
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#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL 0xf4c
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#define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xf50
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#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN 0xf54
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#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60
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#define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64
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#define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68
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#define MT8365_RDMA0_SOUT_COLOR0 0x1
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#define MT8365_DITHER_MOUT_EN_DSI0 0x1
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#define MT8365_DSI0_SEL_IN_DITHER 0x1
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#define MT8365_RDMA0_SEL_IN_OVL0 0x0
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#define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0
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#define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0
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#define MT8365_OVL0_MOUT_PATH0_SEL BIT(0)
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static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
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MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL
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},
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
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MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0
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},
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{
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
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MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
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MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0
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},
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{
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DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,
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MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
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MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
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},
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{
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
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MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
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},
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{
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
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MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
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},
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{
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
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MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
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MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
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},
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};
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#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */
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@ -13,6 +13,7 @@
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#include "mtk-mmsys.h"
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#include "mt8167-mmsys.h"
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#include "mt8183-mmsys.h"
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#include "mt8365-mmsys.h"
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static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
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.clk_driver = "clk-mt2701-mm",
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@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
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.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
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};
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static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
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.clk_driver = "clk-mt8365-mm",
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.routes = mt8365_mmsys_routing_table,
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.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
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};
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struct mtk_mmsys {
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void __iomem *regs;
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const struct mtk_mmsys_driver_data *data;
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@ -160,6 +167,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
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.compatible = "mediatek,mt8183-mmsys",
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.data = &mt8183_mmsys_driver_data,
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},
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{
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.compatible = "mediatek,mt8365-mmsys",
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.data = &mt8365_mmsys_driver_data,
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},
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{ }
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};
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