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riscv: dts: sophgo: add clock generator for Sophgo CV1800 series SoC

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Add clock generator node for CV1800B and CV1812H.

Until now, It uses DT override to minimize duplication. This may
change in the future. See the last link for the discussion on
maintaining DT of CV1800 series.

Link: 6f4e9b8ecb/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf
Link: https://lore.kernel.org/all/IA1PR20MB495373158F3B690EF3BF2901BB8BA@IA1PR20MB4953.namprd20.prod.outlook.com/
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/IA1PR20MB4953ED6A4B57773865F49D6DBB262@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
This commit is contained in:
Inochi Amaoto 2024-03-09 17:02:55 +08:00
parent 89a7056ed4
commit bb7b341962
3 changed files with 14 additions and 0 deletions
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4
arch/riscv/boot/dts/sophgo/cv1800b.dtsi
View File

@ -16,3 +16,7 @@
&clint {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
};
&clk {
compatible = "sophgo,cv1800-clk";
};

4
arch/riscv/boot/dts/sophgo/cv1812h.dtsi
View File

@ -22,3 +22,7 @@
&clint {
compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
};
&clk {
compatible = "sophgo,cv1810-clk";
};

6
arch/riscv/boot/dts/sophgo/cv18xx.dtsi
View File

@ -61,6 +61,12 @@
dma-noncoherent;
ranges;
clk: clock-controller@3002000 {
reg = <0x03002000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
gpio0: gpio@3020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3020000 0x1000>;