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Merge branch 'drm-next-4.19' of git://people.freedesktop.org/~agd5f/linux into drm-next

Browse Source 
More features for 4.19:
- Use core pcie functionality rather than duplicating our own for pcie
  gens and lanes
- Scheduler function naming cleanups
- More documentation
- Reworked DC/Powerplay interfaces to improve power savings
- Initial stutter mode support for RV (power feature)
- Vega12 powerplay updates
- GFXOFF fixes
- Misc fixes

Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180705221447.2807-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie 2018-07-10 10:57:02 +10:00
commit ba7ca97d73
137 changed files with 4243 additions and 2887 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
Documentation/gpu/amdgpu.rst
View File

@ -5,6 +5,13 @@
The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
Next (GCN) architecture.
Module Parameters
=================
The amdgpu driver supports the following module parameters:
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
Core Driver Infrastructure
==========================
@ -115,3 +122,8 @@ pp_power_profile_mode
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
:doc: pp_power_profile_mode
busy_percent
~~~~~~~~~~~~
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
:doc: busy_percent

55
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@ -190,6 +190,7 @@ struct amdgpu_job;
struct amdgpu_irq_src;
struct amdgpu_fpriv;
struct amdgpu_bo_va_mapping;
struct amdgpu_atif;
enum amdgpu_cp_irq {
AMDGPU_CP_IRQ_GFX_EOP = 0,
@ -683,8 +684,8 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_entity_cleanup(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr);
void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
@ -930,6 +931,11 @@ struct amdgpu_ngg {
bool init;
};
struct sq_work {
struct work_struct work;
unsigned ih_data;
};
struct amdgpu_gfx {
struct mutex gpu_clock_mutex;
struct amdgpu_gfx_config config;
@ -970,6 +976,8 @@ struct amdgpu_gfx {
struct amdgpu_irq_src priv_inst_irq;
struct amdgpu_irq_src cp_ecc_error_irq;
struct amdgpu_irq_src sq_irq;
struct sq_work sq_work;
/* gfx status */
uint32_t gfx_current_status;
/* ce ram size*/
@ -1271,43 +1279,6 @@ struct amdgpu_vram_scratch {
/*
* ACPI
*/
struct amdgpu_atif_notification_cfg {
bool enabled;
int command_code;
};
struct amdgpu_atif_notifications {
bool display_switch;
bool expansion_mode_change;
bool thermal_state;
bool forced_power_state;
bool system_power_state;
bool display_conf_change;
bool px_gfx_switch;
bool brightness_change;
bool dgpu_display_event;
};
struct amdgpu_atif_functions {
bool system_params;
bool sbios_requests;
bool select_active_disp;
bool lid_state;
bool get_tv_standard;
bool set_tv_standard;
bool get_panel_expansion_mode;
bool set_panel_expansion_mode;
bool temperature_change;
bool graphics_device_types;
};
struct amdgpu_atif {
struct amdgpu_atif_notifications notifications;
struct amdgpu_atif_functions functions;
struct amdgpu_atif_notification_cfg notification_cfg;
struct amdgpu_encoder *encoder_for_bl;
};
struct amdgpu_atcs_functions {
bool get_ext_state;
bool pcie_perf_req;
@ -1468,7 +1439,7 @@ struct amdgpu_device {
#if defined(CONFIG_DEBUG_FS)
struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
#endif
struct amdgpu_atif atif;
struct amdgpu_atif *atif;
struct amdgpu_atcs atcs;
struct mutex srbm_mutex;
/* GRBM index mutex. Protects concurrent access to GRBM index */
@ -1896,6 +1867,12 @@ static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false;
static inline bool amdgpu_has_atpx(void) { return false; }
#endif
#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
void *amdgpu_atpx_get_dhandle(void);
#else
static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
#endif
/*
* KMS
*/

137
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
View File

@ -34,6 +34,45 @@
#include "amd_acpi.h"
#include "atom.h"
struct amdgpu_atif_notification_cfg {
bool enabled;
int command_code;
};
struct amdgpu_atif_notifications {
bool display_switch;
bool expansion_mode_change;
bool thermal_state;
bool forced_power_state;
bool system_power_state;
bool display_conf_change;
bool px_gfx_switch;
bool brightness_change;
bool dgpu_display_event;
};
struct amdgpu_atif_functions {
bool system_params;
bool sbios_requests;
bool select_active_disp;
bool lid_state;
bool get_tv_standard;
bool set_tv_standard;
bool get_panel_expansion_mode;
bool set_panel_expansion_mode;
bool temperature_change;
bool graphics_device_types;
};
struct amdgpu_atif {
acpi_handle handle;
struct amdgpu_atif_notifications notifications;
struct amdgpu_atif_functions functions;
struct amdgpu_atif_notification_cfg notification_cfg;
struct amdgpu_encoder *encoder_for_bl;
};
/* Call the ATIF method
*/
/**
@ -46,8 +85,9 @@
* Executes the requested ATIF function (all asics).
* Returns a pointer to the acpi output buffer.
*/
static union acpi_object *amdgpu_atif_call(acpi_handle handle, int function,
struct acpi_buffer *params)
static union acpi_object *amdgpu_atif_call(struct amdgpu_atif *atif,
int function,
struct acpi_buffer *params)
{
acpi_status status;
union acpi_object atif_arg_elements[2];
@ -70,7 +110,8 @@ static union acpi_object *amdgpu_atif_call(acpi_handle handle, int function,
atif_arg_elements[1].integer.value = 0;
}
status = acpi_evaluate_object(handle, "ATIF", &atif_arg, &buffer);
status = acpi_evaluate_object(atif->handle, NULL, &atif_arg,
&buffer);
/* Fail only if calling the method fails and ATIF is supported */
if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
@ -141,15 +182,14 @@ static void amdgpu_atif_parse_functions(struct amdgpu_atif_functions *f, u32 mas
* (all asics).
* returns 0 on success, error on failure.
*/
static int amdgpu_atif_verify_interface(acpi_handle handle,
struct amdgpu_atif *atif)
static int amdgpu_atif_verify_interface(struct amdgpu_atif *atif)
{
union acpi_object *info;
struct atif_verify_interface output;
size_t size;
int err = 0;
info = amdgpu_atif_call(handle, ATIF_FUNCTION_VERIFY_INTERFACE, NULL);
info = amdgpu_atif_call(atif, ATIF_FUNCTION_VERIFY_INTERFACE, NULL);
if (!info)
return -EIO;
@ -176,6 +216,35 @@ out:
return err;
}
static acpi_handle amdgpu_atif_probe_handle(acpi_handle dhandle)
{
acpi_handle handle = NULL;
char acpi_method_name[255] = { 0 };
struct acpi_buffer buffer = { sizeof(acpi_method_name), acpi_method_name };
acpi_status status;
/* For PX/HG systems, ATIF and ATPX are in the iGPU's namespace, on dGPU only
* systems, ATIF is in the dGPU's namespace.
*/
status = acpi_get_handle(dhandle, "ATIF", &handle);
if (ACPI_SUCCESS(status))
goto out;
if (amdgpu_has_atpx()) {
status = acpi_get_handle(amdgpu_atpx_get_dhandle(), "ATIF",
&handle);
if (ACPI_SUCCESS(status))
goto out;
}
DRM_DEBUG_DRIVER("No ATIF handle found\n");
return NULL;
out:
acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
DRM_DEBUG_DRIVER("Found ATIF handle %s\n", acpi_method_name);
return handle;
}
/**
* amdgpu_atif_get_notification_params - determine notify configuration
*
@ -188,15 +257,16 @@ out:
* where n is specified in the result if a notifier is used.
* Returns 0 on success, error on failure.
*/
static int amdgpu_atif_get_notification_params(acpi_handle handle,
struct amdgpu_atif_notification_cfg *n)
static int amdgpu_atif_get_notification_params(struct amdgpu_atif *atif)
{
union acpi_object *info;
struct amdgpu_atif_notification_cfg *n = &atif->notification_cfg;
struct atif_system_params params;
size_t size;
int err = 0;
info = amdgpu_atif_call(handle, ATIF_FUNCTION_GET_SYSTEM_PARAMETERS, NULL);
info = amdgpu_atif_call(atif, ATIF_FUNCTION_GET_SYSTEM_PARAMETERS,
NULL);
if (!info) {
err = -EIO;
goto out;
@ -250,14 +320,15 @@ out:
* (all asics).
* Returns 0 on success, error on failure.
*/
static int amdgpu_atif_get_sbios_requests(acpi_handle handle,
struct atif_sbios_requests *req)
static int amdgpu_atif_get_sbios_requests(struct amdgpu_atif *atif,
struct atif_sbios_requests *req)
{
union acpi_object *info;
size_t size;
int count = 0;
info = amdgpu_atif_call(handle, ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS, NULL);
info = amdgpu_atif_call(atif, ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS,
NULL);
if (!info)
return -EIO;
@ -290,11 +361,10 @@ out:
* Returns NOTIFY code
*/
static int amdgpu_atif_handler(struct amdgpu_device *adev,
struct acpi_bus_event *event)
struct acpi_bus_event *event)
{
struct amdgpu_atif *atif = &adev->atif;
struct amdgpu_atif *atif = adev->atif;
struct atif_sbios_requests req;
acpi_handle handle;
int count;
DRM_DEBUG_DRIVER("event, device_class = %s, type = %#x\n",
@ -303,14 +373,14 @@ static int amdgpu_atif_handler(struct amdgpu_device *adev,
if (strcmp(event->device_class, ACPI_VIDEO_CLASS) != 0)
return NOTIFY_DONE;
if (!atif->notification_cfg.enabled ||
if (!atif ||
!atif->notification_cfg.enabled ||
event->type != atif->notification_cfg.command_code)
/* Not our event */
return NOTIFY_DONE;
/* Check pending SBIOS requests */
handle = ACPI_HANDLE(&adev->pdev->dev);
count = amdgpu_atif_get_sbios_requests(handle, &req);
count = amdgpu_atif_get_sbios_requests(atif, &req);
if (count <= 0)
return NOTIFY_DONE;
@ -641,8 +711,8 @@ static int amdgpu_acpi_event(struct notifier_block *nb,
*/
int amdgpu_acpi_init(struct amdgpu_device *adev)
{
acpi_handle handle;
struct amdgpu_atif *atif = &adev->atif;
acpi_handle handle, atif_handle;
struct amdgpu_atif *atif;
struct amdgpu_atcs *atcs = &adev->atcs;
int ret;
@ -658,12 +728,26 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
DRM_DEBUG_DRIVER("Call to ATCS verify_interface failed: %d\n", ret);
}
/* Call the ATIF method */
ret = amdgpu_atif_verify_interface(handle, atif);
if (ret) {
DRM_DEBUG_DRIVER("Call to ATIF verify_interface failed: %d\n", ret);
/* Probe for ATIF, and initialize it if found */
atif_handle = amdgpu_atif_probe_handle(handle);
if (!atif_handle)
goto out;
atif = kzalloc(sizeof(*atif), GFP_KERNEL);
if (!atif) {
DRM_WARN("Not enough memory to initialize ATIF\n");
goto out;
}
atif->handle = atif_handle;
/* Call the ATIF method */
ret = amdgpu_atif_verify_interface(atif);
if (ret) {
DRM_DEBUG_DRIVER("Call to ATIF verify_interface failed: %d\n", ret);
kfree(atif);
goto out;
}
adev->atif = atif;
if (atif->notifications.brightness_change) {
struct drm_encoder *tmp;
@ -693,8 +777,7 @@ int amdgpu_acpi_init(struct amdgpu_device *adev)
}
if (atif->functions.system_params) {
ret = amdgpu_atif_get_notification_params(handle,
&atif->notification_cfg);
ret = amdgpu_atif_get_notification_params(atif);
if (ret) {
DRM_DEBUG_DRIVER("Call to GET_SYSTEM_PARAMS failed: %d\n",
ret);
@ -720,4 +803,6 @@ out:
void amdgpu_acpi_fini(struct amdgpu_device *adev)
{
unregister_acpi_notifier(&adev->acpi_nb);
if (adev->atif)
kfree(adev->atif);
}

10
drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
View File

@ -32,7 +32,7 @@ struct amdgpu_atpx_functions {
bool switch_start;
bool switch_end;
bool disp_connectors_mapping;
bool disp_detetion_ports;
bool disp_detection_ports;
};
struct amdgpu_atpx {
@ -90,6 +90,12 @@ bool amdgpu_atpx_dgpu_req_power_for_displays(void) {
return amdgpu_atpx_priv.atpx.dgpu_req_power_for_displays;
}
#if defined(CONFIG_ACPI)
void *amdgpu_atpx_get_dhandle(void) {
return amdgpu_atpx_priv.dhandle;
}
#endif
/**
* amdgpu_atpx_call - call an ATPX method
*
@ -156,7 +162,7 @@ static void amdgpu_atpx_parse_functions(struct amdgpu_atpx_functions *f, u32 mas
f->switch_start = mask & ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED;
f->switch_end = mask & ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED;
f->disp_connectors_mapping = mask & ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED;
f->disp_detetion_ports = mask & ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED;
f->disp_detection_ports = mask & ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED;
}
/**

8
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
View File

@ -314,17 +314,17 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
(adev->pdev->revision == 0x81) ||
(adev->pdev->device == 0x665f)) {
info->is_kicker = true;
strcpy(fw_name, "radeon/bonaire_k_smc.bin");
strcpy(fw_name, "amdgpu/bonaire_k_smc.bin");
} else {
strcpy(fw_name, "radeon/bonaire_smc.bin");
strcpy(fw_name, "amdgpu/bonaire_smc.bin");
}
break;
case CHIP_HAWAII:
if (adev->pdev->revision == 0x80) {
info->is_kicker = true;
strcpy(fw_name, "radeon/hawaii_k_smc.bin");
strcpy(fw_name, "amdgpu/hawaii_k_smc.bin");
} else {
strcpy(fw_name, "radeon/hawaii_smc.bin");
strcpy(fw_name, "amdgpu/hawaii_smc.bin");
}
break;
case CHIP_TOPAZ:

14
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
View File

@ -104,7 +104,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
failed:
for (j = 0; j < i; j++)
drm_sched_entity_fini(&adev->rings[j]->sched,
drm_sched_entity_destroy(&adev->rings[j]->sched,
&ctx->rings[j].entity);
kfree(ctx->fences);
ctx->fences = NULL;
@ -178,7 +178,7 @@ static void amdgpu_ctx_do_release(struct kref *ref)
if (ctx->adev->rings[i] == &ctx->adev->gfx.kiq.ring)
continue;
drm_sched_entity_fini(&ctx->adev->rings[i]->sched,
drm_sched_entity_destroy(&ctx->adev->rings[i]->sched,
&ctx->rings[i].entity);
}
@ -444,7 +444,7 @@ void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
idr_init(&mgr->ctx_handles);
}
void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)
void amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr)
{
struct amdgpu_ctx *ctx;
struct idr *idp;
@ -466,14 +466,14 @@ void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)
if (ctx->adev->rings[i] == &ctx->adev->gfx.kiq.ring)
continue;
max_wait = drm_sched_entity_do_release(&ctx->adev->rings[i]->sched,
max_wait = drm_sched_entity_flush(&ctx->adev->rings[i]->sched,
&ctx->rings[i].entity, max_wait);
}
}
mutex_unlock(&mgr->lock);
}
void amdgpu_ctx_mgr_entity_cleanup(struct amdgpu_ctx_mgr *mgr)
void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)
{
struct amdgpu_ctx *ctx;
struct idr *idp;
@ -492,7 +492,7 @@ void amdgpu_ctx_mgr_entity_cleanup(struct amdgpu_ctx_mgr *mgr)
continue;
if (kref_read(&ctx->refcount) == 1)
drm_sched_entity_cleanup(&ctx->adev->rings[i]->sched,
drm_sched_entity_fini(&ctx->adev->rings[i]->sched,
&ctx->rings[i].entity);
else
DRM_ERROR("ctx %p is still alive\n", ctx);
@ -506,7 +506,7 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
struct idr *idp;
uint32_t id;
amdgpu_ctx_mgr_entity_cleanup(mgr);
amdgpu_ctx_mgr_entity_fini(mgr);
idp = &mgr->ctx_handles;

165
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -1076,7 +1076,7 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
/**
* amdgpu_device_ip_set_clockgating_state - set the CG state
*
* @adev: amdgpu_device pointer
* @dev: amdgpu_device pointer
* @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
* @state: clockgating state (gate or ungate)
*
@ -1110,7 +1110,7 @@ int amdgpu_device_ip_set_clockgating_state(void *dev,
/**
* amdgpu_device_ip_set_powergating_state - set the PG state
*
* @adev: amdgpu_device pointer
* @dev: amdgpu_device pointer
* @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
* @state: powergating state (gate or ungate)
*
@ -1221,7 +1221,7 @@ bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
* amdgpu_device_ip_get_ip_block - get a hw IP pointer
*
* @adev: amdgpu_device pointer
* @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
* @type: Type of hardware IP (SMU, GFX, UVD, etc.)
*
* Returns a pointer to the hardware IP block structure
* if it exists for the asic, otherwise NULL.
@ -1707,10 +1707,6 @@ static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
if (amdgpu_emu_mode == 1)
return 0;
r = amdgpu_ib_ring_tests(adev);
if (r)
DRM_ERROR("ib ring test failed (%d).\n", r);
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.valid)
continue;
@ -1730,17 +1726,34 @@ static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
}
}
if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) {
/* enable gfx powergating */
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_PG_STATE_GATE);
/* enable gfxoff */
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_SMC,
AMD_PG_STATE_GATE);
}
return 0;
}
static int amdgpu_device_ip_late_set_pg_state(struct amdgpu_device *adev)
{
int i = 0, r;
if (amdgpu_emu_mode == 1)
return 0;
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.valid)
continue;
/* skip CG for VCE/UVD, it's handled specially */
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
adev->ip_blocks[i].version->funcs->set_powergating_state) {
/* enable powergating to save power */
r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
AMD_PG_STATE_GATE);
if (r) {
DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
}
}
return 0;
}
@ -1774,6 +1787,9 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
}
}
amdgpu_device_ip_late_set_cg_state(adev);
amdgpu_device_ip_late_set_pg_state(adev);
queue_delayed_work(system_wq, &adev->late_init_work,
msecs_to_jiffies(AMDGPU_RESUME_MS));
@ -1812,6 +1828,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
if (adev->powerplay.pp_funcs->set_powergating_by_smu)
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false);
r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
/* XXX handle errors */
if (r) {
@ -1900,7 +1918,11 @@ static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
{
struct amdgpu_device *adev =
container_of(work, struct amdgpu_device, late_init_work.work);
amdgpu_device_ip_late_set_cg_state(adev);
int r;
r = amdgpu_ib_ring_tests(adev);
if (r)
DRM_ERROR("ib ring test failed (%d).\n", r);
}
/**
@ -1921,12 +1943,6 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
if (amdgpu_sriov_vf(adev))
amdgpu_virt_request_full_gpu(adev, false);
/* ungate SMC block powergating */
if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_SMC,
AMD_PG_STATE_UNGATE);
/* ungate SMC block first */
r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
AMD_CG_STATE_UNGATE);
@ -1934,6 +1950,10 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
}
/* call smu to disable gfx off feature first when suspend */
if (adev->powerplay.pp_funcs->set_powergating_by_smu)
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false);
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.valid)
continue;
@ -2209,7 +2229,7 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
* amdgpu_device_init - initialize the driver
*
* @adev: amdgpu_device pointer
* @pdev: drm dev pointer
* @ddev: drm dev pointer
* @pdev: pci dev pointer
* @flags: driver flags
*
@ -2582,8 +2602,9 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
/**
* amdgpu_device_suspend - initiate device suspend
*
* @pdev: drm dev pointer
* @state: suspend state
* @dev: drm dev pointer
* @suspend: suspend state
* @fbcon : notify the fbdev of suspend
*
* Puts the hw in the suspend state (all asics).
* Returns 0 for success or an error on failure.
@ -2681,7 +2702,9 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
/**
* amdgpu_device_resume - initiate device resume
*
* @pdev: drm dev pointer
* @dev: drm dev pointer
* @resume: resume state
* @fbcon : notify the fbdev of resume
*
* Bring the hw back to operating state (all asics).
* Returns 0 for success or an error on failure.
@ -3144,6 +3167,7 @@ out:
* amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf
*
* @adev: amdgpu device pointer
* @from_hypervisor: request from hypervisor
*
* do VF FLR and reinitialize Asic
* return 0 means successed otherwise failed
@ -3191,7 +3215,7 @@ error:
*
* @adev: amdgpu device pointer
* @job: which job trigger hang
* @force forces reset regardless of amdgpu_gpu_recovery
* @force: forces reset regardless of amdgpu_gpu_recovery
*
* Attempt to reset the GPU if it has hung (all asics).
* Returns 0 for success or an error on failure.
@ -3291,8 +3315,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
*/
static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
{
u32 mask;
int ret;
struct pci_dev *pdev;
enum pci_bus_speed speed_cap;
enum pcie_link_width link_width;
if (amdgpu_pcie_gen_cap)
adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
@ -3310,27 +3335,61 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
}
if (adev->pm.pcie_gen_mask == 0) {
ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
if (!ret) {
adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
/* asic caps */
pdev = adev->pdev;
speed_cap = pcie_get_speed_cap(pdev);
if (speed_cap == PCI_SPEED_UNKNOWN) {
adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
if (mask & DRM_PCIE_SPEED_25)
adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
if (mask & DRM_PCIE_SPEED_50)
adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
if (mask & DRM_PCIE_SPEED_80)
adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
} else {
adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
if (speed_cap == PCIE_SPEED_16_0GT)
adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
else if (speed_cap == PCIE_SPEED_8_0GT)
adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
else if (speed_cap == PCIE_SPEED_5_0GT)
adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
else
adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
}
/* platform caps */
pdev = adev->ddev->pdev->bus->self;
speed_cap = pcie_get_speed_cap(pdev);
if (speed_cap == PCI_SPEED_UNKNOWN) {
adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
} else {
if (speed_cap == PCIE_SPEED_16_0GT)
adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
else if (speed_cap == PCIE_SPEED_8_0GT)
adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
else if (speed_cap == PCIE_SPEED_5_0GT)
adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
else
adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
}
}
if (adev->pm.pcie_mlw_mask == 0) {
ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
if (!ret) {
switch (mask) {
case 32:
pdev = adev->ddev->pdev->bus->self;
link_width = pcie_get_width_cap(pdev);
if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {
adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
} else {
switch (link_width) {
case PCIE_LNK_X32:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
@ -3339,7 +3398,7 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 16:
case PCIE_LNK_X16:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
@ -3347,36 +3406,34 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 12:
case PCIE_LNK_X12:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 8:
case PCIE_LNK_X8:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 4:
case PCIE_LNK_X4:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 2:
case PCIE_LNK_X2:
adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
break;
case 1:
case PCIE_LNK_X1:
adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
break;
default:
break;
}
} else {
adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
}
}
}

7
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
View File

@ -28,6 +28,7 @@
#include "amdgpu_i2c.h"
#include "amdgpu_dpm.h"
#include "atom.h"
#include "amd_pcie.h"
void amdgpu_dpm_print_class_info(u32 class, u32 class2)
{
@ -936,9 +937,11 @@ enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
case AMDGPU_PCIE_GEN3:
return AMDGPU_PCIE_GEN3;
default:
if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) &&
(default_gen == AMDGPU_PCIE_GEN3))
return AMDGPU_PCIE_GEN3;
else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) &&
(default_gen == AMDGPU_PCIE_GEN2))
return AMDGPU_PCIE_GEN2;
else
return AMDGPU_PCIE_GEN1;

14
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
View File

@ -287,12 +287,6 @@ enum amdgpu_pcie_gen {
#define amdgpu_dpm_force_performance_level(adev, l) \
((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
#define amdgpu_dpm_powergate_uvd(adev, g) \
((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
#define amdgpu_dpm_powergate_vce(adev, g) \
((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
#define amdgpu_dpm_get_current_power_state(adev) \
((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
@ -347,6 +341,10 @@ enum amdgpu_pcie_gen {
((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
(adev)->powerplay.pp_handle, msg_id))
#define amdgpu_dpm_set_powergating_by_smu(adev, block_type, gate) \
((adev)->powerplay.pp_funcs->set_powergating_by_smu(\
(adev)->powerplay.pp_handle, block_type, gate))
#define amdgpu_dpm_get_power_profile_mode(adev, buf) \
((adev)->powerplay.pp_funcs->get_power_profile_mode(\
(adev)->powerplay.pp_handle, buf))
@ -359,10 +357,6 @@ enum amdgpu_pcie_gen {
((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
(adev)->powerplay.pp_handle, type, parameter, size))
#define amdgpu_dpm_set_mmhub_powergating_by_smu(adev) \
((adev)->powerplay.pp_funcs->set_mmhub_powergating_by_smu( \
(adev)->powerplay.pp_handle))
struct amdgpu_dpm {
struct amdgpu_ps *ps;
/* number of valid power states */

241
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View File

@ -1,10 +1,3 @@
/**
* \file amdgpu_drv.c
* AMD Amdgpu driver
*
* \author Gareth Hughes <gareth@valinux.com>
*/
/*
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
* All Rights Reserved.
@ -122,7 +115,8 @@ uint amdgpu_pg_mask = 0xffffffff;
uint amdgpu_sdma_phase_quantum = 32;
char *amdgpu_disable_cu = NULL;
char *amdgpu_virtual_display = NULL;
uint amdgpu_pp_feature_mask = 0xffff3fff; /* gfxoff (bit 15) disabled by default */
/* OverDrive(bit 14),gfxoff(bit 15),stutter mode(bit 17) disabled by default*/
uint amdgpu_pp_feature_mask = 0xfffd3fff;
int amdgpu_ngg = 0;
int amdgpu_prim_buf_per_se = 0;
int amdgpu_pos_buf_per_se = 0;
@ -135,102 +129,239 @@ int amdgpu_gpu_recovery = -1; /* auto */
int amdgpu_emu_mode = 0;
uint amdgpu_smu_memory_pool_size = 0;
/**
* DOC: vramlimit (int)
* Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
*/
MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
/**
* DOC: vis_vramlimit (int)
* Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
*/
MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
/**
* DOC: gartsize (uint)
* Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
*/
MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
/**
* DOC: gttsize (int)
* Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
* otherwise 3/4 RAM size).
*/
MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
/**
* DOC: moverate (int)
* Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
*/
MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
module_param_named(moverate, amdgpu_moverate, int, 0600);
/**
* DOC: benchmark (int)
* Run benchmarks. The default is 0 (Skip benchmarks).
*/
MODULE_PARM_DESC(benchmark, "Run benchmark");
module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
/**
* DOC: test (int)
* Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
*/
MODULE_PARM_DESC(test, "Run tests");
module_param_named(test, amdgpu_testing, int, 0444);
/**
* DOC: audio (int)
* Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
*/
MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
module_param_named(audio, amdgpu_audio, int, 0444);
/**
* DOC: disp_priority (int)
* Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
*/
MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
/**
* DOC: hw_i2c (int)
* To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
*/
MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
/**
* DOC: pcie_gen2 (int)
* To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
*/
MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
/**
* DOC: msi (int)
* To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
*/
MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
module_param_named(msi, amdgpu_msi, int, 0444);
/**
* DOC: lockup_timeout (int)
* Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be adjusted to 10000.
* Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 10000.
*/
MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)");
module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
/**
* DOC: dpm (int)
* Override for dynamic power management setting (1 = enable, 0 = disable). The default is -1 (auto).
*/
MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
module_param_named(dpm, amdgpu_dpm, int, 0444);
/**
* DOC: fw_load_type (int)
* Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto).
*/
MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
/**
* DOC: aspm (int)
* To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
*/
MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
module_param_named(aspm, amdgpu_aspm, int, 0444);
/**
* DOC: runpm (int)
* Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down
* the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality.
*/
MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
/**
* DOC: ip_block_mask (uint)
* Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
* Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
* some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
* the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
*/
MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
/**
* DOC: bapm (int)
* Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
* The default -1 (auto, enabled)
*/
MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
module_param_named(bapm, amdgpu_bapm, int, 0444);
/**
* DOC: deep_color (int)
* Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
*/
MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
module_param_named(deep_color, amdgpu_deep_color, int, 0444);
/**
* DOC: vm_size (int)
* Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
*/
MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
module_param_named(vm_size, amdgpu_vm_size, int, 0444);
/**
* DOC: vm_fragment_size (int)
* Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
*/
MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
/**
* DOC: vm_block_size (int)
* Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
*/
MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
/**
* DOC: vm_fault_stop (int)
* Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
*/
MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
/**
* DOC: vm_debug (int)
* Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
*/
MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
/**
* DOC: vm_update_mode (int)
* Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
* is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
*/
MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
/**
* DOC: vram_page_split (int)
* Override the number of pages after we split VRAM allocations (default 512, -1 = disable). The default is 512.
*/
MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)");
module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
/**
* DOC: exp_hw_support (int)
* Enable experimental hw support (1 = enable). The default is 0 (disabled).
*/
MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
/**
* DOC: dc (int)
* Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
*/
MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
module_param_named(dc, amdgpu_dc, int, 0444);
MODULE_PARM_DESC(dc_log, "Display Core Log Level (0 = minimal (default), 1 = chatty");
module_param_named(dc_log, amdgpu_dc_log, int, 0444);
/**
* DOC: sched_jobs (int)
* Override the max number of jobs supported in the sw queue. The default is 32.
*/
MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
/**
* DOC: sched_hw_submission (int)
* Override the max number of HW submissions. The default is 2.
*/
MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
/**
* DOC: ppfeaturemask (uint)
* Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
* The default is the current set of stable power features.
*/
MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
@ -240,58 +371,135 @@ module_param_named(no_evict, amdgpu_no_evict, int, 0444);
MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)");
module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444);
/**
* DOC: pcie_gen_cap (uint)
* Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
* The default is 0 (automatic for each asic).
*/
MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
/**
* DOC: pcie_lane_cap (uint)
* Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
* The default is 0 (automatic for each asic).
*/
MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
/**
* DOC: cg_mask (uint)
* Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
* drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
*/
MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
/**
* DOC: pg_mask (uint)
* Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
* drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
*/
MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
/**
* DOC: sdma_phase_quantum (uint)
* Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
*/
MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
/**
* DOC: disable_cu (charp)
* Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
*/
MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
/**
* DOC: virtual_display (charp)
* Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
* or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
* the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
* device at 26:00.0. The default is NULL.
*/
MODULE_PARM_DESC(virtual_display,
"Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
/**
* DOC: ngg (int)
* Set to enable Next Generation Graphics (1 = enable). The default is 0 (disabled).
*/
MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))");
module_param_named(ngg, amdgpu_ngg, int, 0444);
/**
* DOC: prim_buf_per_se (int)
* Override the size of Primitive Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
*/
MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)");
module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444);
/**
* DOC: pos_buf_per_se (int)
* Override the size of Position Buffer per Shader Engine in Byte. The default is 0 (depending on gfx).
*/
MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)");
module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444);
/**
* DOC: cntl_sb_buf_per_se (int)
* Override the size of Control Sideband per Shader Engine in Byte. The default is 0 (depending on gfx).
*/
MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)");
module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444);
/**
* DOC: param_buf_per_se (int)
* Override the size of Off-Chip Pramater Cache per Shader Engine in Byte. The default is 0 (depending on gfx).
*/
MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)");
module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444);
/**
* DOC: job_hang_limit (int)
* Set how much time allow a job hang and not drop it. The default is 0.
*/
MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
/**
* DOC: lbpw (int)
* Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
*/
MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
module_param_named(lbpw, amdgpu_lbpw, int, 0444);
MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
/**
* DOC: gpu_recovery (int)
* Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
*/
MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
/**
* DOC: emu_mode (int)
* Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
*/
MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
/**
* DOC: si_support (int)
* Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
* set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
* otherwise using amdgpu driver.
*/
#ifdef CONFIG_DRM_AMDGPU_SI
#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
@ -305,6 +513,12 @@ MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)")
module_param_named(si_support, amdgpu_si_support, int, 0444);
#endif
/**
* DOC: cik_support (int)
* Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
* set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
* otherwise using amdgpu driver.
*/
#ifdef CONFIG_DRM_AMDGPU_CIK
#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
@ -318,6 +532,11 @@ MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)
module_param_named(cik_support, amdgpu_cik_support, int, 0444);
#endif
/**
* DOC: smu_memory_pool_size (uint)
* It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
* E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
*/
MODULE_PARM_DESC(smu_memory_pool_size,
"reserve gtt for smu debug usage, 0 = disable,"
"0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
@ -664,7 +883,7 @@ retry_init:
err_pci:
pci_disable_device(pdev);
err_free:
drm_dev_unref(dev);
drm_dev_put(dev);
return ret;
}
@ -674,7 +893,7 @@ amdgpu_pci_remove(struct pci_dev *pdev)
struct drm_device *dev = pci_get_drvdata(pdev);
drm_dev_unregister(dev);
drm_dev_unref(dev);
drm_dev_put(dev);
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
}
@ -860,7 +1079,7 @@ static int amdgpu_flush(struct file *f, fl_owner_t id)
struct drm_file *file_priv = f->private_data;
struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
amdgpu_ctx_mgr_entity_fini(&fpriv->ctx_mgr);
amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr);
return 0;
}

2
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
View File

@ -146,7 +146,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
AMDGPU_GEM_CREATE_VRAM_CLEARED,
true, NULL, &gobj);
ttm_bo_type_kernel, NULL, &gobj);
if (ret) {
pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
return -ENOMEM;

8
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
View File

@ -234,7 +234,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
}
t = offset / AMDGPU_GPU_PAGE_SIZE;
p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
for (i = 0; i < pages; i++, p++) {
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
adev->gart.pages[p] = NULL;
@ -243,7 +243,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
if (!adev->gart.ptr)
continue;
for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
t, page_base, flags);
page_base += AMDGPU_GPU_PAGE_SIZE;
@ -282,7 +282,7 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
for (i = 0; i < pages; i++) {
page_base = dma_addr[i];
for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
page_base += AMDGPU_GPU_PAGE_SIZE;
}
@ -319,7 +319,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
t = offset / AMDGPU_GPU_PAGE_SIZE;
p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
for (i = 0; i < pages; i++, p++)
adev->gart.pages[p] = pagelist ? pagelist[i] : NULL;
#endif

2
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
View File

@ -37,6 +37,8 @@ struct amdgpu_bo;
#define AMDGPU_GPU_PAGE_SHIFT 12
#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
#define AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE)
struct amdgpu_gart {
u64 table_addr;
struct amdgpu_bo *robj;

6
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
View File

@ -265,7 +265,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
r = amdgpu_gem_object_create(adev, size, args->in.alignment,
(u32)(0xffffffff & args->in.domains),
flags, false, resv, &gobj);
flags, ttm_bo_type_device, resv, &gobj);
if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
if (!r) {
struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
@ -317,7 +317,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
/* create a gem object to contain this object in */
r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
0, 0, NULL, &gobj);
0, ttm_bo_type_device, NULL, &gobj);
if (r)
return r;
@ -766,7 +766,7 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
amdgpu_display_supported_domains(adev));
r = amdgpu_gem_object_create(adev, args->size, 0, domain,
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
false, NULL, &gobj);
ttm_bo_type_device, NULL, &gobj);
if (r)
return -ENOMEM;

12
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
View File

@ -231,6 +231,12 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
/* wrap the last IB with fence */
if (job && job->uf_addr) {
amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
fence_flags | AMDGPU_FENCE_FLAG_64BIT);
}
r = amdgpu_fence_emit(ring, f, fence_flags);
if (r) {
dev_err(adev->dev, "failed to emit fence (%d)\n", r);
@ -243,12 +249,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
if (ring->funcs->insert_end)
ring->funcs->insert_end(ring);
/* wrap the last IB with fence */
if (job && job->uf_addr) {
amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
fence_flags | AMDGPU_FENCE_FLAG_64BIT);
}
if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
amdgpu_ring_patch_cond_exec(ring, patch_offset);

5
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
View File

@ -578,11 +578,6 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
}
}
adev->vm_manager.fence_context =
dma_fence_context_alloc(AMDGPU_MAX_RINGS);
for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
adev->vm_manager.seqno[i] = 0;
}
/**

5
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
View File

@ -58,7 +58,8 @@
*
* @adev: amdgpu device pointer
* @mm: process address space
* @mn: MMU notifier structur
* @mn: MMU notifier structure
* @type: type of MMU notifier
* @work: destruction work item
* @node: hash table node to find structure by adev and mn
* @lock: rw semaphore protecting the notifier nodes
@ -266,7 +267,7 @@ static void amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn,
* amdgpu_mn_invalidate_range_start_hsa - callback to notify about mm change
*
* @mn: our notifier
* @mn: the mm this callback is about
* @mm: the mm this callback is about
* @start: start of updated range
* @end: end of updated range
*

50
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
View File

@ -918,6 +918,36 @@ fail:
return -EINVAL;
}
/**
* DOC: busy_percent
*
* The amdgpu driver provides a sysfs API for reading how busy the GPU
* is as a percentage. The file gpu_busy_percent is used for this.
* The SMU firmware computes a percentage of load based on the
* aggregate activity level in the IP cores.
*/
static ssize_t amdgpu_get_busy_percent(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
int r, value, size = sizeof(value);
/* sanity check PP is enabled */
if (!(adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->read_sensor))
return -EINVAL;
/* read the IP busy sensor */
r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
(void *)&value, &size);
if (r)
return r;
return snprintf(buf, PAGE_SIZE, "%d\n", value);
}
static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
amdgpu_get_dpm_forced_performance_level,
@ -951,6 +981,8 @@ static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
amdgpu_get_pp_od_clk_voltage,
amdgpu_set_pp_od_clk_voltage);
static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
amdgpu_get_busy_percent, NULL);
static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
struct device_attribute *attr,
@ -1697,10 +1729,10 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
{
if (adev->powerplay.pp_funcs->powergate_uvd) {
if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
/* enable/disable UVD */
mutex_lock(&adev->pm.mutex);
amdgpu_dpm_powergate_uvd(adev, !enable);
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
mutex_unlock(&adev->pm.mutex);
} else {
if (enable) {
@ -1719,10 +1751,10 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
{
if (adev->powerplay.pp_funcs->powergate_vce) {
if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
/* enable/disable VCE */
mutex_lock(&adev->pm.mutex);
amdgpu_dpm_powergate_vce(adev, !enable);
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
mutex_unlock(&adev->pm.mutex);
} else {
if (enable) {
@ -1854,6 +1886,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
"pp_od_clk_voltage\n");
return ret;
}
ret = device_create_file(adev->dev,
&dev_attr_gpu_busy_percent);
if (ret) {
DRM_ERROR("failed to create device file "
"gpu_busy_level\n");
return ret;
}
ret = amdgpu_debugfs_pm_init(adev);
if (ret) {
DRM_ERROR("Failed to register debugfs file for dpm!\n");
@ -1889,6 +1928,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
&dev_attr_pp_power_profile_mode);
device_remove_file(adev->dev,
&dev_attr_pp_od_clk_voltage);
device_remove_file(adev->dev, &dev_attr_gpu_busy_percent);
}
void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
@ -1919,7 +1959,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
if (!amdgpu_device_has_dc_support(adev)) {
mutex_lock(&adev->pm.mutex);
amdgpu_dpm_get_active_displays(adev);
adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtcs;
adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
/* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */

1
drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
View File

@ -191,7 +191,6 @@ error:
/**
* amdgpu_gem_map_attach - &dma_buf_ops.attach implementation
* @dma_buf: shared DMA buffer
* @target_dev: target device
* @attach: DMA-buf attachment
*
* Makes sure that the shared DMA buffer can be accessed by the target device.

1
drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright 2009 VMware, Inc.
*

2
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
View File

@ -162,7 +162,7 @@ error_mem:
static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
{
if (adev->mman.mem_global_referenced) {
drm_sched_entity_fini(adev->mman.entity.sched,
drm_sched_entity_destroy(adev->mman.entity.sched,
&adev->mman.entity);
mutex_destroy(&adev->mman.gtt_window_lock);
drm_global_item_unref(&adev->mman.bo_global_ref.ref);

12
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
View File

@ -53,11 +53,11 @@
/* Firmware Names */
#ifdef CONFIG_DRM_AMDGPU_CIK
#define FIRMWARE_BONAIRE "radeon/bonaire_uvd.bin"
#define FIRMWARE_KABINI "radeon/kabini_uvd.bin"
#define FIRMWARE_KAVERI "radeon/kaveri_uvd.bin"
#define FIRMWARE_HAWAII "radeon/hawaii_uvd.bin"
#define FIRMWARE_MULLINS "radeon/mullins_uvd.bin"
#define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin"
#define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin"
#define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin"
#define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin"
#define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin"
#endif
#define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin"
#define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin"
@ -309,7 +309,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
kfree(adev->uvd.inst[j].saved_bo);
drm_sched_entity_fini(&adev->uvd.inst[j].ring.sched, &adev->uvd.inst[j].entity);
drm_sched_entity_destroy(&adev->uvd.inst[j].ring.sched, &adev->uvd.inst[j].entity);
amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo,
&adev->uvd.inst[j].gpu_addr,

12
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
View File

@ -40,11 +40,11 @@
/* Firmware Names */
#ifdef CONFIG_DRM_AMDGPU_CIK
#define FIRMWARE_BONAIRE "radeon/bonaire_vce.bin"
#define FIRMWARE_KABINI "radeon/kabini_vce.bin"
#define FIRMWARE_KAVERI "radeon/kaveri_vce.bin"
#define FIRMWARE_HAWAII "radeon/hawaii_vce.bin"
#define FIRMWARE_MULLINS "radeon/mullins_vce.bin"
#define FIRMWARE_BONAIRE "amdgpu/bonaire_vce.bin"
#define FIRMWARE_KABINI "amdgpu/kabini_vce.bin"
#define FIRMWARE_KAVERI "amdgpu/kaveri_vce.bin"
#define FIRMWARE_HAWAII "amdgpu/hawaii_vce.bin"
#define FIRMWARE_MULLINS "amdgpu/mullins_vce.bin"
#endif
#define FIRMWARE_TONGA "amdgpu/tonga_vce.bin"
#define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin"
@ -222,7 +222,7 @@ int amdgpu_vce_sw_fini(struct amdgpu_device *adev)
if (adev->vce.vcpu_bo == NULL)
return 0;
drm_sched_entity_fini(&adev->vce.ring[0].sched, &adev->vce.entity);
drm_sched_entity_destroy(&adev->vce.ring[0].sched, &adev->vce.entity);
amdgpu_bo_free_kernel(&adev->vce.vcpu_bo, &adev->vce.gpu_addr,
(void **)&adev->vce.cpu_addr);

14
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
View File

@ -1082,7 +1082,7 @@ restart:
struct amdgpu_vm_bo_base,
vm_status);
bo_base->moved = false;
list_move(&bo_base->vm_status, &vm->idle);
list_del_init(&bo_base->vm_status);
bo = bo_base->bo->parent;
if (!bo)
@ -1567,7 +1567,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
if (nodes) {
addr = nodes->start << PAGE_SHIFT;
max_entries = (nodes->size - pfn) *
(PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
AMDGPU_GPU_PAGES_IN_CPU_PAGE;
} else {
addr = 0;
max_entries = S64_MAX;
@ -1578,7 +1578,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
max_entries = min(max_entries, 16ull * 1024ull);
for (count = 1;
count < max_entries / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
++count) {
uint64_t idx = pfn + count;
@ -1592,7 +1592,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
dma_addr = pages_addr;
} else {
addr = pages_addr[pfn];
max_entries = count * (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
}
} else if (flags & AMDGPU_PTE_VALID) {
@ -1607,7 +1607,7 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
if (r)
return r;
pfn += (last - start + 1) / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
if (nodes && nodes->size == pfn) {
pfn = 0;
++nodes;
@ -2643,7 +2643,7 @@ error_free_root:
vm->root.base.bo = NULL;
error_free_sched_entity:
drm_sched_entity_fini(&ring->sched, &vm->entity);
drm_sched_entity_destroy(&ring->sched, &vm->entity);
return r;
}
@ -2780,7 +2780,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
}
drm_sched_entity_fini(vm->entity.sched, &vm->entity);
drm_sched_entity_destroy(vm->entity.sched, &vm->entity);
if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
dev_err(adev->dev, "still active bo inside vm\n");

2
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
View File

@ -112,7 +112,7 @@ u64 amdgpu_vram_mgr_bo_invisible_size(struct amdgpu_bo *bo)
unsigned pages = mem->num_pages;
u64 usage = 0;
if (adev->gmc.visible_vram_size == adev->gmc.real_vram_size)
if (amdgpu_gmc_vram_full_visible(&adev->gmc))
return 0;
if (mem->start >= adev->gmc.visible_vram_size >> PAGE_SHIFT)

2
drivers/gpu/drm/amd/amdgpu/atom.c
View File

@ -1221,7 +1221,7 @@ static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index,
ectx.abort = false;
ectx.last_jump = 0;
if (ws)
ectx.ws = kcalloc(4, ws, GFP_ATOMIC);
ectx.ws = kcalloc(4, ws, GFP_KERNEL);
else
ectx.ws = NULL;

28
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
View File

@ -49,10 +49,10 @@
#include "gmc/gmc_7_1_d.h"
#include "gmc/gmc_7_1_sh_mask.h"
MODULE_FIRMWARE("radeon/bonaire_smc.bin");
MODULE_FIRMWARE("radeon/bonaire_k_smc.bin");
MODULE_FIRMWARE("radeon/hawaii_smc.bin");
MODULE_FIRMWARE("radeon/hawaii_k_smc.bin");
MODULE_FIRMWARE("amdgpu/bonaire_smc.bin");
MODULE_FIRMWARE("amdgpu/bonaire_k_smc.bin");
MODULE_FIRMWARE("amdgpu/hawaii_smc.bin");
MODULE_FIRMWARE("amdgpu/hawaii_k_smc.bin");
#define MC_CG_ARB_FREQ_F0 0x0a
#define MC_CG_ARB_FREQ_F1 0x0b
@ -5815,7 +5815,7 @@ static int ci_dpm_init_microcode(struct amdgpu_device *adev)
default: BUG();
}
snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
if (err)
goto out;
@ -5846,8 +5846,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
adev->pm.dpm.priv = pi;
pi->sys_pcie_mask =
(adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
@ -6767,6 +6766,19 @@ static int ci_dpm_read_sensor(void *handle, int idx,
}
}
static int ci_set_powergating_by_smu(void *handle,
uint32_t block_type, bool gate)
{
switch (block_type) {
case AMD_IP_BLOCK_TYPE_UVD:
ci_dpm_powergate_uvd(handle, gate);
break;
default:
break;
}
return 0;
}
static const struct amd_ip_funcs ci_dpm_ip_funcs = {
.name = "ci_dpm",
.early_init = ci_dpm_early_init,
@ -6804,7 +6816,7 @@ static const struct amd_pm_funcs ci_dpm_funcs = {
.debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
.force_performance_level = &ci_dpm_force_performance_level,
.vblank_too_short = &ci_dpm_vblank_too_short,
.powergate_uvd = &ci_dpm_powergate_uvd,
.set_powergating_by_smu = &ci_set_powergating_by_smu,
.set_fan_control_mode = &ci_dpm_set_fan_control_mode,
.get_fan_control_mode = &ci_dpm_get_fan_control_mode,
.set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,

36
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
View File

@ -54,16 +54,16 @@ static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
static int cik_sdma_soft_reset(void *handle);
MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
MODULE_FIRMWARE("radeon/kabini_sdma.bin");
MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
MODULE_FIRMWARE("radeon/mullins_sdma.bin");
MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");
MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");
MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin");
MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin");
MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin");
MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin");
MODULE_FIRMWARE("amdgpu/kabini_sdma.bin");
MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin");
MODULE_FIRMWARE("amdgpu/mullins_sdma.bin");
MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin");
u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
@ -132,9 +132,9 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev)
for (i = 0; i < adev->sdma.num_instances; i++) {
if (i == 0)
snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
else
snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
if (err)
goto out;
@ -177,9 +177,8 @@ static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
}
/**
@ -192,9 +191,8 @@ static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me],
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
(lower_32_bits(ring->wptr) << 2) & 0x3fffc);
}
@ -248,7 +246,7 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
u32 ref_and_mask;
if (ring == &ring->adev->sdma.instance[0].ring)
if (ring->me == 0)
ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
else
ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
@ -1290,8 +1288,10 @@ static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
for (i = 0; i < adev->sdma.num_instances; i++)
for (i = 0; i < adev->sdma.num_instances; i++) {
adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
adev->sdma.instance[i].ring.me = i;
}
}
static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {

48
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
View File

@ -44,30 +44,30 @@ static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
MODULE_FIRMWARE("radeon/tahiti_me.bin");
MODULE_FIRMWARE("radeon/tahiti_ce.bin");
MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin");
MODULE_FIRMWARE("amdgpu/tahiti_me.bin");
MODULE_FIRMWARE("amdgpu/tahiti_ce.bin");
MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin");
MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
MODULE_FIRMWARE("radeon/pitcairn_me.bin");
MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin");
MODULE_FIRMWARE("amdgpu/pitcairn_me.bin");
MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin");
MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin");
MODULE_FIRMWARE("radeon/verde_pfp.bin");
MODULE_FIRMWARE("radeon/verde_me.bin");
MODULE_FIRMWARE("radeon/verde_ce.bin");
MODULE_FIRMWARE("radeon/verde_rlc.bin");
MODULE_FIRMWARE("amdgpu/verde_pfp.bin");
MODULE_FIRMWARE("amdgpu/verde_me.bin");
MODULE_FIRMWARE("amdgpu/verde_ce.bin");
MODULE_FIRMWARE("amdgpu/verde_rlc.bin");
MODULE_FIRMWARE("radeon/oland_pfp.bin");
MODULE_FIRMWARE("radeon/oland_me.bin");
MODULE_FIRMWARE("radeon/oland_ce.bin");
MODULE_FIRMWARE("radeon/oland_rlc.bin");
MODULE_FIRMWARE("amdgpu/oland_pfp.bin");
MODULE_FIRMWARE("amdgpu/oland_me.bin");
MODULE_FIRMWARE("amdgpu/oland_ce.bin");
MODULE_FIRMWARE("amdgpu/oland_rlc.bin");
MODULE_FIRMWARE("radeon/hainan_pfp.bin");
MODULE_FIRMWARE("radeon/hainan_me.bin");
MODULE_FIRMWARE("radeon/hainan_ce.bin");
MODULE_FIRMWARE("radeon/hainan_rlc.bin");
MODULE_FIRMWARE("amdgpu/hainan_pfp.bin");
MODULE_FIRMWARE("amdgpu/hainan_me.bin");
MODULE_FIRMWARE("amdgpu/hainan_ce.bin");
MODULE_FIRMWARE("amdgpu/hainan_rlc.bin");
static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
@ -335,7 +335,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
default: BUG();
}
snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
if (err)
goto out;
@ -346,7 +346,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
if (err)
goto out;
@ -357,7 +357,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
if (err)
goto out;
@ -368,7 +368,7 @@ static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
if (err)
goto out;

64
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
View File

@ -57,36 +57,36 @@ static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
MODULE_FIRMWARE("radeon/bonaire_me.bin");
MODULE_FIRMWARE("radeon/bonaire_ce.bin");
MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
MODULE_FIRMWARE("radeon/bonaire_mec.bin");
MODULE_FIRMWARE("amdgpu/bonaire_pfp.bin");
MODULE_FIRMWARE("amdgpu/bonaire_me.bin");
MODULE_FIRMWARE("amdgpu/bonaire_ce.bin");
MODULE_FIRMWARE("amdgpu/bonaire_rlc.bin");
MODULE_FIRMWARE("amdgpu/bonaire_mec.bin");
MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
MODULE_FIRMWARE("radeon/hawaii_me.bin");
MODULE_FIRMWARE("radeon/hawaii_ce.bin");
MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
MODULE_FIRMWARE("radeon/hawaii_mec.bin");
MODULE_FIRMWARE("amdgpu/hawaii_pfp.bin");
MODULE_FIRMWARE("amdgpu/hawaii_me.bin");
MODULE_FIRMWARE("amdgpu/hawaii_ce.bin");
MODULE_FIRMWARE("amdgpu/hawaii_rlc.bin");
MODULE_FIRMWARE("amdgpu/hawaii_mec.bin");
MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
MODULE_FIRMWARE("radeon/kaveri_me.bin");
MODULE_FIRMWARE("radeon/kaveri_ce.bin");
MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
MODULE_FIRMWARE("radeon/kaveri_mec.bin");
MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
MODULE_FIRMWARE("amdgpu/kaveri_pfp.bin");
MODULE_FIRMWARE("amdgpu/kaveri_me.bin");
MODULE_FIRMWARE("amdgpu/kaveri_ce.bin");
MODULE_FIRMWARE("amdgpu/kaveri_rlc.bin");
MODULE_FIRMWARE("amdgpu/kaveri_mec.bin");
MODULE_FIRMWARE("amdgpu/kaveri_mec2.bin");
MODULE_FIRMWARE("radeon/kabini_pfp.bin");
MODULE_FIRMWARE("radeon/kabini_me.bin");
MODULE_FIRMWARE("radeon/kabini_ce.bin");
MODULE_FIRMWARE("radeon/kabini_rlc.bin");
MODULE_FIRMWARE("radeon/kabini_mec.bin");
MODULE_FIRMWARE("amdgpu/kabini_pfp.bin");
MODULE_FIRMWARE("amdgpu/kabini_me.bin");
MODULE_FIRMWARE("amdgpu/kabini_ce.bin");
MODULE_FIRMWARE("amdgpu/kabini_rlc.bin");
MODULE_FIRMWARE("amdgpu/kabini_mec.bin");
MODULE_FIRMWARE("radeon/mullins_pfp.bin");
MODULE_FIRMWARE("radeon/mullins_me.bin");
MODULE_FIRMWARE("radeon/mullins_ce.bin");
MODULE_FIRMWARE("radeon/mullins_rlc.bin");
MODULE_FIRMWARE("radeon/mullins_mec.bin");
MODULE_FIRMWARE("amdgpu/mullins_pfp.bin");
MODULE_FIRMWARE("amdgpu/mullins_me.bin");
MODULE_FIRMWARE("amdgpu/mullins_ce.bin");
MODULE_FIRMWARE("amdgpu/mullins_rlc.bin");
MODULE_FIRMWARE("amdgpu/mullins_mec.bin");
static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
{
@ -925,7 +925,7 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
default: BUG();
}
snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
if (err)
goto out;
@ -933,7 +933,7 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
if (err)
goto out;
snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
if (err)
goto out;
@ -941,7 +941,7 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
if (err)
goto out;
snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
if (err)
goto out;
@ -949,7 +949,7 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
if (err)
goto out;
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
if (err)
goto out;
@ -958,7 +958,7 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
goto out;
if (adev->asic_type == CHIP_KAVERI) {
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
if (err)
goto out;
@ -967,7 +967,7 @@ static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
goto out;
}
snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
if (err)
goto out;

120
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
View File

@ -704,6 +704,17 @@ static const u32 stoney_mgcg_cgcg_init[] =
mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
};
static const char * const sq_edc_source_names[] = {
"SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
"SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
"SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
"SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
"SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
"SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
"SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
};
static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
@ -2006,6 +2017,8 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
return 0;
}
static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
static int gfx_v8_0_sw_init(void *handle)
{
int i, j, k, r, ring_id;
@ -2069,6 +2082,8 @@ static int gfx_v8_0_sw_init(void *handle)
return r;
}
INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
gfx_v8_0_scratch_init(adev);
@ -5581,24 +5596,18 @@ static int gfx_v8_0_late_init(void *handle)
return r;
}
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_GFX,
AMD_PG_STATE_GATE);
return 0;
}
static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
bool enable)
{
if ((adev->asic_type == CHIP_POLARIS11) ||
if (((adev->asic_type == CHIP_POLARIS11) ||
(adev->asic_type == CHIP_POLARIS12) ||
(adev->asic_type == CHIP_VEGAM))
(adev->asic_type == CHIP_VEGAM)) &&
adev->powerplay.pp_funcs->set_powergating_by_smu)
/* Send msg to SMU via Powerplay */
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_SMC,
enable ?
AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
}
@ -6955,16 +6964,14 @@ static int gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device *adev,
return 0;
}
static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data)
{
u8 enc, se_id;
u32 enc, se_id, sh_id, cu_id;
char type[20];
int sq_edc_source = -1;
/* Parse all fields according to SQ_INTERRUPT* registers */
enc = (entry->src_data[0] >> 26) & 0x3;
se_id = (entry->src_data[0] >> 24) & 0x3;
enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
switch (enc) {
case 0:
@ -6974,19 +6981,37 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
"reg_timestamp %d, thread_trace_buff_full %d,"
"wlt %d, thread_trace %d.\n",
se_id,
(entry->src_data[0] >> 7) & 0x1,
(entry->src_data[0] >> 6) & 0x1,
(entry->src_data[0] >> 5) & 0x1,
(entry->src_data[0] >> 4) & 0x1,
(entry->src_data[0] >> 3) & 0x1,
(entry->src_data[0] >> 2) & 0x1,
(entry->src_data[0] >> 1) & 0x1,
entry->src_data[0] & 0x1
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT),
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
);
break;
case 1:
case 2:
cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID);
sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SH_ID);
/*
* This function can be called either directly from ISR
* or from BH in which case we can access SQ_EDC_INFO
* instance
*/
if (in_task()) {
mutex_lock(&adev->grbm_idx_mutex);
gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id);
sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
mutex_unlock(&adev->grbm_idx_mutex);
}
if (enc == 1)
sprintf(type, "instruction intr");
else
@ -6994,17 +7019,46 @@ static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
DRM_INFO(
"SQ %s detected: "
"se_id %d, cu_id %d, simd_id %d, wave_id %d, vm_id %d\n",
type, se_id,
(entry->src_data[0] >> 20) & 0xf,
(entry->src_data[0] >> 18) & 0x3,
(entry->src_data[0] >> 14) & 0xf,
(entry->src_data[0] >> 10) & 0xf
);
"se_id %d, sh_id %d, cu_id %d, simd_id %d, wave_id %d, vm_id %d "
"trap %s, sq_ed_info.source %s.\n",
type, se_id, sh_id, cu_id,
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, VM_ID),
REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
(sq_edc_source != -1) ? sq_edc_source_names[sq_edc_source] : "unavailable"
);
break;
default:
DRM_ERROR("SQ invalid encoding type\n.");
return -EINVAL;
}
}
static void gfx_v8_0_sq_irq_work_func(struct work_struct *work)
{
struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work);
struct sq_work *sq_work = container_of(work, struct sq_work, work);
gfx_v8_0_parse_sq_irq(adev, sq_work->ih_data);
}
static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
unsigned ih_data = entry->src_data[0];
/*
* Try to submit work so SQ_EDC_INFO can be accessed from
* BH. If previous work submission hasn't finished yet
* just print whatever info is possible directly from the ISR.
*/
if (work_pending(&adev->gfx.sq_work.work)) {
gfx_v8_0_parse_sq_irq(adev, ih_data);
} else {
adev->gfx.sq_work.ih_data = ih_data;
schedule_work(&adev->gfx.sq_work.work);
}
return 0;

4
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View File

@ -3714,6 +3714,10 @@ static int gfx_v9_0_set_powergating_state(void *handle,
/* update mgcg state */
gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
/* set gfx off through smu */
if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true);
break;
default:
break;

14
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
View File

@ -41,11 +41,11 @@ static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
static int gmc_v6_0_wait_for_idle(void *handle);
MODULE_FIRMWARE("radeon/tahiti_mc.bin");
MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
MODULE_FIRMWARE("radeon/verde_mc.bin");
MODULE_FIRMWARE("radeon/oland_mc.bin");
MODULE_FIRMWARE("radeon/si58_mc.bin");
MODULE_FIRMWARE("amdgpu/tahiti_mc.bin");
MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");
MODULE_FIRMWARE("amdgpu/verde_mc.bin");
MODULE_FIRMWARE("amdgpu/oland_mc.bin");
MODULE_FIRMWARE("amdgpu/si58_mc.bin");
#define MC_SEQ_MISC0__MT__MASK 0xf0000000
#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
@ -134,9 +134,9 @@ static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
is_58_fw = true;
if (is_58_fw)
snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
snprintf(fw_name, sizeof(fw_name), "amdgpu/si58_mc.bin");
else
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
if (err)
goto out;

9
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
View File

@ -47,8 +47,8 @@ static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
static int gmc_v7_0_wait_for_idle(void *handle);
MODULE_FIRMWARE("radeon/bonaire_mc.bin");
MODULE_FIRMWARE("radeon/hawaii_mc.bin");
MODULE_FIRMWARE("amdgpu/bonaire_mc.bin");
MODULE_FIRMWARE("amdgpu/hawaii_mc.bin");
MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
static const u32 golden_settings_iceland_a11[] =
@ -147,10 +147,7 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
default: BUG();
}
if (adev->asic_type == CHIP_TOPAZ)
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
else
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
if (err)

15
drivers/gpu/drm/amd/amdgpu/kv_dpm.c
View File

@ -3306,6 +3306,19 @@ static int kv_dpm_read_sensor(void *handle, int idx,
}
}
static int kv_set_powergating_by_smu(void *handle,
uint32_t block_type, bool gate)
{
switch (block_type) {
case AMD_IP_BLOCK_TYPE_UVD:
kv_dpm_powergate_uvd(handle, gate);
break;
default:
break;
}
return 0;
}
static const struct amd_ip_funcs kv_dpm_ip_funcs = {
.name = "kv_dpm",
.early_init = kv_dpm_early_init,
@ -3342,7 +3355,7 @@ static const struct amd_pm_funcs kv_dpm_funcs = {
.print_power_state = &kv_dpm_print_power_state,
.debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
.force_performance_level = &kv_dpm_force_performance_level,
.powergate_uvd = &kv_dpm_powergate_uvd,
.set_powergating_by_smu = kv_set_powergating_by_smu,
.enable_bapm = &kv_dpm_enable_bapm,
.get_vce_clock_state = amdgpu_get_vce_clock_state,
.check_state_equal = kv_check_state_equal,

4
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
View File

@ -471,8 +471,8 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
RENG_EXECUTE_ON_REG_UPDATE, 1);
WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
if (adev->powerplay.pp_funcs->set_mmhub_powergating_by_smu)
amdgpu_dpm_set_mmhub_powergating_by_smu(adev);
if (adev->powerplay.pp_funcs->set_powergating_by_smu)
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
} else {
pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,

12
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
View File

@ -202,8 +202,7 @@ static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
return wptr;
}
@ -218,9 +217,8 @@ static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
}
static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
@ -273,7 +271,7 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
{
u32 ref_and_mask = 0;
if (ring == &ring->adev->sdma.instance[0].ring)
if (ring->me == 0)
ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
else
ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
@ -1213,8 +1211,10 @@ static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
for (i = 0; i < adev->sdma.num_instances; i++)
for (i = 0; i < adev->sdma.num_instances; i++) {
adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
adev->sdma.instance[i].ring.me = i;
}
}
static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {

14
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
View File

@ -365,9 +365,7 @@ static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
/* XXX check if swapping is necessary on BE */
wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
} else {
int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
}
return wptr;
@ -394,9 +392,7 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));
} else {
int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], lower_32_bits(ring->wptr) << 2);
WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
}
}
@ -450,7 +446,7 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
{
u32 ref_and_mask = 0;
if (ring == &ring->adev->sdma.instance[0].ring)
if (ring->me == 0)
ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
else
ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
@ -1655,8 +1651,10 @@ static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
for (i = 0; i < adev->sdma.num_instances; i++)
for (i = 0; i < adev->sdma.num_instances; i++) {
adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
adev->sdma.instance[i].ring.me = i;
}
}
static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {

23
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
View File

@ -296,13 +296,12 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
} else {
u32 lowbit, highbit;
int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2;
highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
me, highbit, lowbit);
ring->me, highbit, lowbit);
wptr = highbit;
wptr = wptr << 32;
wptr |= lowbit;
@ -339,17 +338,15 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
ring->doorbell_index, ring->wptr << 2);
WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
} else {
int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
DRM_DEBUG("Not using doorbell -- "
"mmSDMA%i_GFX_RB_WPTR == 0x%08x "
"mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
me,
ring->me,
lower_32_bits(ring->wptr << 2),
me,
ring->me,
upper_32_bits(ring->wptr << 2));
WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
}
}
@ -430,7 +427,7 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
u32 ref_and_mask = 0;
const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
if (ring == &ring->adev->sdma.instance[0].ring)
if (ring->me == 0)
ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
else
ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
@ -1651,8 +1648,10 @@ static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
for (i = 0; i < adev->sdma.num_instances; i++)
for (i = 0; i < adev->sdma.num_instances; i++) {
adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
adev->sdma.instance[i].ring.me = i;
}
}
static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {

25
drivers/gpu/drm/amd/amdgpu/si_dpm.c
View File

@ -56,16 +56,16 @@
#define BIOS_SCRATCH_4 0x5cd
MODULE_FIRMWARE("radeon/tahiti_smc.bin");
MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
MODULE_FIRMWARE("radeon/verde_smc.bin");
MODULE_FIRMWARE("radeon/verde_k_smc.bin");
MODULE_FIRMWARE("radeon/oland_smc.bin");
MODULE_FIRMWARE("radeon/oland_k_smc.bin");
MODULE_FIRMWARE("radeon/hainan_smc.bin");
MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
MODULE_FIRMWARE("amdgpu/tahiti_smc.bin");
MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin");
MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin");
MODULE_FIRMWARE("amdgpu/verde_smc.bin");
MODULE_FIRMWARE("amdgpu/verde_k_smc.bin");
MODULE_FIRMWARE("amdgpu/oland_smc.bin");
MODULE_FIRMWARE("amdgpu/oland_k_smc.bin");
MODULE_FIRMWARE("amdgpu/hainan_smc.bin");
MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin");
MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin");
static const struct amd_pm_funcs si_dpm_funcs;
@ -7318,8 +7318,7 @@ static int si_dpm_init(struct amdgpu_device *adev)
pi = &eg_pi->rv7xx;
si_pi->sys_pcie_mask =
(adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
@ -7667,7 +7666,7 @@ static int si_dpm_init_microcode(struct amdgpu_device *adev)
default: BUG();
}
snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
if (err)
goto out;

5
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
View File

@ -470,7 +470,7 @@ static int uvd_v6_0_sw_fini(void *handle)
return r;
if (uvd_v6_0_enc_support(adev)) {
drm_sched_entity_fini(&adev->uvd.inst->ring_enc[0].sched, &adev->uvd.inst->entity_enc);
drm_sched_entity_destroy(&adev->uvd.inst->ring_enc[0].sched, &adev->uvd.inst->entity_enc);
for (i = 0; i < adev->uvd.num_enc_rings; ++i)
amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]);
@ -1569,7 +1569,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
.type = AMDGPU_RING_TYPE_UVD,
.align_mask = 0xf,
.nop = PACKET0(mmUVD_NO_OP, 0),
.support_64bit_ptrs = false,
.get_rptr = uvd_v6_0_ring_get_rptr,
.get_wptr = uvd_v6_0_ring_get_wptr,
@ -1587,7 +1586,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
.emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
.test_ring = uvd_v6_0_ring_test_ring,
.test_ib = amdgpu_uvd_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
.insert_nop = uvd_v6_0_ring_insert_nop,
.pad_ib = amdgpu_ring_generic_pad_ib,
.begin_use = amdgpu_uvd_ring_begin_use,
.end_use = amdgpu_uvd_ring_end_use,

2
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
View File

@ -491,7 +491,7 @@ static int uvd_v7_0_sw_fini(void *handle)
return r;
for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
drm_sched_entity_fini(&adev->uvd.inst[j].ring_enc[0].sched, &adev->uvd.inst[j].entity_enc);
drm_sched_entity_destroy(&adev->uvd.inst[j].ring_enc[0].sched, &adev->uvd.inst[j].entity_enc);
for (i = 0; i < adev->uvd.num_enc_rings; ++i)
amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);

10
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
View File

@ -56,7 +56,7 @@ static uint64_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
if (ring == &adev->vce.ring[0])
if (ring->me == 0)
return RREG32(mmVCE_RB_RPTR);
else
return RREG32(mmVCE_RB_RPTR2);
@ -73,7 +73,7 @@ static uint64_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
if (ring == &adev->vce.ring[0])
if (ring->me == 0)
return RREG32(mmVCE_RB_WPTR);
else
return RREG32(mmVCE_RB_WPTR2);
@ -90,7 +90,7 @@ static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
if (ring == &adev->vce.ring[0])
if (ring->me == 0)
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
else
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
@ -627,8 +627,10 @@ static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
for (i = 0; i < adev->vce.num_rings; i++)
for (i = 0; i < adev->vce.num_rings; i++) {
adev->vce.ring[i].funcs = &vce_v2_0_ring_funcs;
adev->vce.ring[i].me = i;
}
}
static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {

24
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
View File

@ -86,9 +86,9 @@ static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
if (ring == &adev->vce.ring[0])
if (ring->me == 0)
v = RREG32(mmVCE_RB_RPTR);
else if (ring == &adev->vce.ring[1])
else if (ring->me == 1)
v = RREG32(mmVCE_RB_RPTR2);
else
v = RREG32(mmVCE_RB_RPTR3);
@ -118,9 +118,9 @@ static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
if (ring == &adev->vce.ring[0])
if (ring->me == 0)
v = RREG32(mmVCE_RB_WPTR);
else if (ring == &adev->vce.ring[1])
else if (ring->me == 1)
v = RREG32(mmVCE_RB_WPTR2);
else
v = RREG32(mmVCE_RB_WPTR3);
@ -149,9 +149,9 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0)
WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
if (ring == &adev->vce.ring[0])
if (ring->me == 0)
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
else if (ring == &adev->vce.ring[1])
else if (ring->me == 1)
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
else
WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
@ -900,7 +900,7 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
.emit_frame_size =
4 + /* vce_v3_0_emit_pipeline_sync */
6, /* amdgpu_vce_ring_emit_fence x1 no user fence */
.emit_ib_size = 5, /* vce_v3_0_ring_emit_ib */
.emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */
.emit_ib = amdgpu_vce_ring_emit_ib,
.emit_fence = amdgpu_vce_ring_emit_fence,
.test_ring = amdgpu_vce_ring_test_ring,
@ -924,7 +924,7 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = {
6 + /* vce_v3_0_emit_vm_flush */
4 + /* vce_v3_0_emit_pipeline_sync */
6 + 6, /* amdgpu_vce_ring_emit_fence x2 vm fence */
.emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */
.emit_ib_size = 5, /* vce_v3_0_ring_emit_ib */
.emit_ib = vce_v3_0_ring_emit_ib,
.emit_vm_flush = vce_v3_0_emit_vm_flush,
.emit_pipeline_sync = vce_v3_0_emit_pipeline_sync,
@ -942,12 +942,16 @@ static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev)
int i;
if (adev->asic_type >= CHIP_STONEY) {
for (i = 0; i < adev->vce.num_rings; i++)
for (i = 0; i < adev->vce.num_rings; i++) {
adev->vce.ring[i].funcs = &vce_v3_0_ring_vm_funcs;
adev->vce.ring[i].me = i;
}
DRM_INFO("VCE enabled in VM mode\n");
} else {
for (i = 0; i < adev->vce.num_rings; i++)
for (i = 0; i < adev->vce.num_rings; i++) {
adev->vce.ring[i].funcs = &vce_v3_0_ring_phys_funcs;
adev->vce.ring[i].me = i;
}
DRM_INFO("VCE enabled in physical mode\n");
}
}

16
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
View File

@ -60,9 +60,9 @@ static uint64_t vce_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
if (ring == &adev->vce.ring[0])
if (ring->me == 0)
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR));
else if (ring == &adev->vce.ring[1])
else if (ring->me == 1)
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2));
else
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));
@ -82,9 +82,9 @@ static uint64_t vce_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
if (ring->use_doorbell)
return adev->wb.wb[ring->wptr_offs];
if (ring == &adev->vce.ring[0])
if (ring->me == 0)
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));
else if (ring == &adev->vce.ring[1])
else if (ring->me == 1)
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2));
else
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3));
@ -108,10 +108,10 @@ static void vce_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
return;
}
if (ring == &adev->vce.ring[0])
if (ring->me == 0)
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR),
lower_32_bits(ring->wptr));
else if (ring == &adev->vce.ring[1])
else if (ring->me == 1)
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2),
lower_32_bits(ring->wptr));
else
@ -1088,8 +1088,10 @@ static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev)
{
int i;
for (i = 0; i < adev->vce.num_rings; i++)
for (i = 0; i < adev->vce.num_rings; i++) {
adev->vce.ring[i].funcs = &vce_v4_0_ring_vm_funcs;
adev->vce.ring[i].me = i;
}
DRM_INFO("VCE enabled in VM mode\n");
}

4
drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
View File

@ -28,11 +28,11 @@
AMDGPUDM = amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o amdgpu_dm_color.o
ifneq ($(CONFIG_DRM_AMD_DC),)
AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o
AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o
endif
ifneq ($(CONFIG_DEBUG_FS),)
AMDGPUDM += amdgpu_dm_crc.o
AMDGPUDM += amdgpu_dm_crc.o amdgpu_dm_debugfs.o
endif
subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc

61
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -39,6 +39,9 @@
#include "dm_helpers.h"
#include "dm_services_types.h"
#include "amdgpu_dm_mst_types.h"
#if defined(CONFIG_DEBUG_FS)
#include "amdgpu_dm_debugfs.h"
#endif
#include "ivsrcid/ivsrcid_vislands30.h"
@ -1532,7 +1535,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
/*
* Temporary disable until pplib/smu interaction is implemented
*/
dm->dc->debug.disable_stutter = true;
dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
break;
#endif
default:
@ -2173,6 +2176,46 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
return color_space;
}
static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
{
if (timing_out->display_color_depth <= COLOR_DEPTH_888)
return;
timing_out->display_color_depth--;
}
static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
const struct drm_display_info *info)
{
int normalized_clk;
if (timing_out->display_color_depth <= COLOR_DEPTH_888)
return;
do {
normalized_clk = timing_out->pix_clk_khz;
/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
normalized_clk /= 2;
/* Adjusting pix clock following on HDMI spec based on colour depth */
switch (timing_out->display_color_depth) {
case COLOR_DEPTH_101010:
normalized_clk = (normalized_clk * 30) / 24;
break;
case COLOR_DEPTH_121212:
normalized_clk = (normalized_clk * 36) / 24;
break;
case COLOR_DEPTH_161616:
normalized_clk = (normalized_clk * 48) / 24;
break;
default:
return;
}
if (normalized_clk <= info->max_tmds_clock)
return;
reduce_mode_colour_depth(timing_out);
} while (timing_out->display_color_depth > COLOR_DEPTH_888);
}
/*****************************************************************************/
static void
@ -2181,6 +2224,7 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
const struct drm_connector *connector)
{
struct dc_crtc_timing *timing_out = &stream->timing;
const struct drm_display_info *info = &connector->display_info;
memset(timing_out, 0, sizeof(struct dc_crtc_timing));
@ -2189,8 +2233,10 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
timing_out->v_border_top = 0;
timing_out->v_border_bottom = 0;
/* TODO: un-hardcode */
if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
if (drm_mode_is_420_only(info, mode_in)
&& stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
&& stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
else
@ -2226,6 +2272,8 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
adjust_colour_depth_from_display_info(timing_out, info);
}
static void fill_audio_info(struct audio_info *audio_info,
@ -3619,6 +3667,13 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
&aconnector->base, &aencoder->base);
drm_connector_register(&aconnector->base);
#if defined(CONFIG_DEBUG_FS)
res = connector_debugfs_init(aconnector);
if (res) {
DRM_ERROR("Failed to create debugfs for connector");
goto out_free;
}
#endif
if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
|| connector_type == DRM_MODE_CONNECTOR_eDP)

170
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c Normal file
View File

@ -0,0 +1,170 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include <linux/debugfs.h>
#include "dc.h"
#include "dc_link.h"
#include "amdgpu.h"
#include "amdgpu_dm.h"
#include "amdgpu_dm_debugfs.h"
static ssize_t dp_link_rate_debugfs_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
/* TODO: create method to read link rate */
return 1;
}
static ssize_t dp_link_rate_debugfs_write(struct file *f, const char __user *buf,
size_t size, loff_t *pos)
{
/* TODO: create method to write link rate */
return 1;
}
static ssize_t dp_lane_count_debugfs_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
/* TODO: create method to read lane count */
return 1;
}
static ssize_t dp_lane_count_debugfs_write(struct file *f, const char __user *buf,
size_t size, loff_t *pos)
{
/* TODO: create method to write lane count */
return 1;
}
static ssize_t dp_voltage_swing_debugfs_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
/* TODO: create method to read voltage swing */
return 1;
}
static ssize_t dp_voltage_swing_debugfs_write(struct file *f, const char __user *buf,
size_t size, loff_t *pos)
{
/* TODO: create method to write voltage swing */
return 1;
}
static ssize_t dp_pre_emphasis_debugfs_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
/* TODO: create method to read pre-emphasis */
return 1;
}
static ssize_t dp_pre_emphasis_debugfs_write(struct file *f, const char __user *buf,
size_t size, loff_t *pos)
{
/* TODO: create method to write pre-emphasis */
return 1;
}
static ssize_t dp_phy_test_pattern_debugfs_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
/* TODO: create method to read PHY test pattern */
return 1;
}
static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
size_t size, loff_t *pos)
{
/* TODO: create method to write PHY test pattern */
return 1;
}
static const struct file_operations dp_link_rate_fops = {
.owner = THIS_MODULE,
.read = dp_link_rate_debugfs_read,
.write = dp_link_rate_debugfs_write,
.llseek = default_llseek
};
static const struct file_operations dp_lane_count_fops = {
.owner = THIS_MODULE,
.read = dp_lane_count_debugfs_read,
.write = dp_lane_count_debugfs_write,
.llseek = default_llseek
};
static const struct file_operations dp_voltage_swing_fops = {
.owner = THIS_MODULE,
.read = dp_voltage_swing_debugfs_read,
.write = dp_voltage_swing_debugfs_write,
.llseek = default_llseek
};
static const struct file_operations dp_pre_emphasis_fops = {
.owner = THIS_MODULE,
.read = dp_pre_emphasis_debugfs_read,
.write = dp_pre_emphasis_debugfs_write,
.llseek = default_llseek
};
static const struct file_operations dp_phy_test_pattern_fops = {
.owner = THIS_MODULE,
.read = dp_phy_test_pattern_debugfs_read,
.write = dp_phy_test_pattern_debugfs_write,
.llseek = default_llseek
};
static const struct {
char *name;
const struct file_operations *fops;
} dp_debugfs_entries[] = {
{"link_rate", &dp_link_rate_fops},
{"lane_count", &dp_lane_count_fops},
{"voltage_swing", &dp_voltage_swing_fops},
{"pre_emphasis", &dp_pre_emphasis_fops},
{"phy_test_pattern", &dp_phy_test_pattern_fops}
};
int connector_debugfs_init(struct amdgpu_dm_connector *connector)
{
int i;
struct dentry *ent, *dir = connector->base.debugfs_entry;
if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
ent = debugfs_create_file(dp_debugfs_entries[i].name,
0644,
dir,
connector,
dp_debugfs_entries[i].fops);
if (IS_ERR(ent))
return PTR_ERR(ent);
}
}
return 0;
}

13
drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.h → drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -23,13 +23,12 @@
*
*/
#ifndef __SOC_BOUNDING_BOX_H__
#define __SOC_BOUNDING_BOX_H__
#ifndef __AMDGPU_DM_DEBUGFS_H__
#define __AMDGPU_DM_DEBUGFS_H__
#include "dml_common_defs.h"
#include "amdgpu.h"
#include "amdgpu_dm.h"
void dml_socbb_set_latencies(soc_bounding_box_st *to_box, soc_bounding_box_st *from_box);
voltage_scaling_st dml_socbb_voltage_scaling(const soc_bounding_box_st *box, enum voltage_state voltage);
double dml_socbb_return_bw_mhz(soc_bounding_box_st *box, enum voltage_state voltage);
int connector_debugfs_init(struct amdgpu_dm_connector *connector);
#endif

535
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c Normal file
View File

@ -0,0 +1,535 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*/
#include <linux/string.h>
#include <linux/acpi.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/amdgpu_drm.h>
#include "dm_services.h"
#include "amdgpu.h"
#include "amdgpu_dm.h"
#include "amdgpu_dm_irq.h"
#include "amdgpu_pm.h"
#include "dm_pp_smu.h"
bool dm_pp_apply_display_requirements(
const struct dc_context *ctx,
const struct dm_pp_display_configuration *pp_display_cfg)
{
struct amdgpu_device *adev = ctx->driver_context;
int i;
if (adev->pm.dpm_enabled) {
memset(&adev->pm.pm_display_cfg, 0,
sizeof(adev->pm.pm_display_cfg));
adev->pm.pm_display_cfg.cpu_cc6_disable =
pp_display_cfg->cpu_cc6_disable;
adev->pm.pm_display_cfg.cpu_pstate_disable =
pp_display_cfg->cpu_pstate_disable;
adev->pm.pm_display_cfg.cpu_pstate_separation_time =
pp_display_cfg->cpu_pstate_separation_time;
adev->pm.pm_display_cfg.nb_pstate_switch_disable =
pp_display_cfg->nb_pstate_switch_disable;
adev->pm.pm_display_cfg.num_display =
pp_display_cfg->display_count;
adev->pm.pm_display_cfg.num_path_including_non_display =
pp_display_cfg->display_count;
adev->pm.pm_display_cfg.min_core_set_clock =
pp_display_cfg->min_engine_clock_khz/10;
adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
adev->pm.pm_display_cfg.min_mem_set_clock =
pp_display_cfg->min_memory_clock_khz/10;
adev->pm.pm_display_cfg.min_dcef_deep_sleep_set_clk =
pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
adev->pm.pm_display_cfg.min_dcef_set_clk =
pp_display_cfg->min_dcfclock_khz/10;
adev->pm.pm_display_cfg.multi_monitor_in_sync =
pp_display_cfg->all_displays_in_sync;
adev->pm.pm_display_cfg.min_vblank_time =
pp_display_cfg->avail_mclk_switch_time_us;
adev->pm.pm_display_cfg.display_clk =
pp_display_cfg->disp_clk_khz/10;
adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
adev->pm.pm_display_cfg.line_time_in_us =
pp_display_cfg->line_time_in_us;
adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh;
adev->pm.pm_display_cfg.crossfire_display_index = -1;
adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
for (i = 0; i < pp_display_cfg->display_count; i++) {
const struct dm_pp_single_disp_config *dc_cfg =
&pp_display_cfg->disp_configs[i];
adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1;
}
/* TODO: complete implementation of
* pp_display_configuration_change().
* Follow example of:
* PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
* PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
if (adev->powerplay.pp_funcs->display_configuration_change)
adev->powerplay.pp_funcs->display_configuration_change(
adev->powerplay.pp_handle,
&adev->pm.pm_display_cfg);
/* TODO: replace by a separate call to 'apply display cfg'? */
amdgpu_pm_compute_clocks(adev);
}
return true;
}
static void get_default_clock_levels(
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels *clks)
{
uint32_t disp_clks_in_khz[6] = {
300000, 400000, 496560, 626090, 685720, 757900 };
uint32_t sclks_in_khz[6] = {
300000, 360000, 423530, 514290, 626090, 720000 };
uint32_t mclks_in_khz[2] = { 333000, 800000 };
switch (clk_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
clks->num_levels = 6;
memmove(clks->clocks_in_khz, disp_clks_in_khz,
sizeof(disp_clks_in_khz));
break;
case DM_PP_CLOCK_TYPE_ENGINE_CLK:
clks->num_levels = 6;
memmove(clks->clocks_in_khz, sclks_in_khz,
sizeof(sclks_in_khz));
break;
case DM_PP_CLOCK_TYPE_MEMORY_CLK:
clks->num_levels = 2;
memmove(clks->clocks_in_khz, mclks_in_khz,
sizeof(mclks_in_khz));
break;
default:
clks->num_levels = 0;
break;
}
}
static enum amd_pp_clock_type dc_to_pp_clock_type(
enum dm_pp_clock_type dm_pp_clk_type)
{
enum amd_pp_clock_type amd_pp_clk_type = 0;
switch (dm_pp_clk_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
amd_pp_clk_type = amd_pp_disp_clock;
break;
case DM_PP_CLOCK_TYPE_ENGINE_CLK:
amd_pp_clk_type = amd_pp_sys_clock;
break;
case DM_PP_CLOCK_TYPE_MEMORY_CLK:
amd_pp_clk_type = amd_pp_mem_clock;
break;
case DM_PP_CLOCK_TYPE_DCEFCLK:
amd_pp_clk_type = amd_pp_dcef_clock;
break;
case DM_PP_CLOCK_TYPE_DCFCLK:
amd_pp_clk_type = amd_pp_dcf_clock;
break;
case DM_PP_CLOCK_TYPE_PIXELCLK:
amd_pp_clk_type = amd_pp_pixel_clock;
break;
case DM_PP_CLOCK_TYPE_FCLK:
amd_pp_clk_type = amd_pp_f_clock;
break;
case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
amd_pp_clk_type = amd_pp_phy_clock;
break;
case DM_PP_CLOCK_TYPE_DPPCLK:
amd_pp_clk_type = amd_pp_dpp_clock;
break;
default:
DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
dm_pp_clk_type);
break;
}
return amd_pp_clk_type;
}
static void pp_to_dc_clock_levels(
const struct amd_pp_clocks *pp_clks,
struct dm_pp_clock_levels *dc_clks,
enum dm_pp_clock_type dc_clk_type)
{
uint32_t i;
if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
pp_clks->count,
DM_PP_MAX_CLOCK_LEVELS);
dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
} else
dc_clks->num_levels = pp_clks->count;
DRM_INFO("DM_PPLIB: values for %s clock\n",
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
for (i = 0; i < dc_clks->num_levels; i++) {
DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
}
}
static void pp_to_dc_clock_levels_with_latency(
const struct pp_clock_levels_with_latency *pp_clks,
struct dm_pp_clock_levels_with_latency *clk_level_info,
enum dm_pp_clock_type dc_clk_type)
{
uint32_t i;
if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
pp_clks->num_levels,
DM_PP_MAX_CLOCK_LEVELS);
clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
} else
clk_level_info->num_levels = pp_clks->num_levels;
DRM_DEBUG("DM_PPLIB: values for %s clock\n",
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
for (i = 0; i < clk_level_info->num_levels; i++) {
DRM_DEBUG("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
}
}
static void pp_to_dc_clock_levels_with_voltage(
const struct pp_clock_levels_with_voltage *pp_clks,
struct dm_pp_clock_levels_with_voltage *clk_level_info,
enum dm_pp_clock_type dc_clk_type)
{
uint32_t i;
if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
pp_clks->num_levels,
DM_PP_MAX_CLOCK_LEVELS);
clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
} else
clk_level_info->num_levels = pp_clks->num_levels;
DRM_INFO("DM_PPLIB: values for %s clock\n",
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
for (i = 0; i < clk_level_info->num_levels; i++) {
DRM_INFO("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
}
}
bool dm_pp_get_clock_levels_by_type(
const struct dc_context *ctx,
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels *dc_clks)
{
struct amdgpu_device *adev = ctx->driver_context;
void *pp_handle = adev->powerplay.pp_handle;
struct amd_pp_clocks pp_clks = { 0 };
struct amd_pp_simple_clock_info validation_clks = { 0 };
uint32_t i;
if (adev->powerplay.pp_funcs->get_clock_by_type) {
if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
dc_to_pp_clock_type(clk_type), &pp_clks)) {
/* Error in pplib. Provide default values. */
get_default_clock_levels(clk_type, dc_clks);
return true;
}
}
pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
pp_handle, &validation_clks)) {
/* Error in pplib. Provide default values. */
DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
validation_clks.engine_max_clock = 72000;
validation_clks.memory_max_clock = 80000;
validation_clks.level = 0;
}
}
DRM_INFO("DM_PPLIB: Validation clocks:\n");
DRM_INFO("DM_PPLIB: engine_max_clock: %d\n",
validation_clks.engine_max_clock);
DRM_INFO("DM_PPLIB: memory_max_clock: %d\n",
validation_clks.memory_max_clock);
DRM_INFO("DM_PPLIB: level : %d\n",
validation_clks.level);
/* Translate 10 kHz to kHz. */
validation_clks.engine_max_clock *= 10;
validation_clks.memory_max_clock *= 10;
/* Determine the highest non-boosted level from the Validation Clocks */
if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
for (i = 0; i < dc_clks->num_levels; i++) {
if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
/* This clock is higher the validation clock.
* Than means the previous one is the highest
* non-boosted one. */
DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
dc_clks->num_levels, i);
dc_clks->num_levels = i > 0 ? i : 1;
break;
}
}
} else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
for (i = 0; i < dc_clks->num_levels; i++) {
if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
dc_clks->num_levels, i);
dc_clks->num_levels = i > 0 ? i : 1;
break;
}
}
}
return true;
}
bool dm_pp_get_clock_levels_by_type_with_latency(
const struct dc_context *ctx,
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels_with_latency *clk_level_info)
{
struct amdgpu_device *adev = ctx->driver_context;
void *pp_handle = adev->powerplay.pp_handle;
struct pp_clock_levels_with_latency pp_clks = { 0 };
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
if (!pp_funcs || !pp_funcs->get_clock_by_type_with_latency)
return false;
if (pp_funcs->get_clock_by_type_with_latency(pp_handle,
dc_to_pp_clock_type(clk_type),
&pp_clks))
return false;
pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
return true;
}
bool dm_pp_get_clock_levels_by_type_with_voltage(
const struct dc_context *ctx,
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels_with_voltage *clk_level_info)
{
struct amdgpu_device *adev = ctx->driver_context;
void *pp_handle = adev->powerplay.pp_handle;
struct pp_clock_levels_with_voltage pp_clk_info = {0};
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
if (pp_funcs->get_clock_by_type_with_voltage(pp_handle,
dc_to_pp_clock_type(clk_type),
&pp_clk_info))
return false;
pp_to_dc_clock_levels_with_voltage(&pp_clk_info, clk_level_info, clk_type);
return true;
}
bool dm_pp_notify_wm_clock_changes(
const struct dc_context *ctx,
struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
{
/* TODO: to be implemented */
return false;
}
bool dm_pp_apply_power_level_change_request(
const struct dc_context *ctx,
struct dm_pp_power_level_change_request *level_change_req)
{
/* TODO: to be implemented */
return false;
}
bool dm_pp_apply_clock_for_voltage_request(
const struct dc_context *ctx,
struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)
{
struct amdgpu_device *adev = ctx->driver_context;
struct pp_display_clock_request pp_clock_request = {0};
int ret = 0;
pp_clock_request.clock_type = dc_to_pp_clock_type(clock_for_voltage_req->clk_type);
pp_clock_request.clock_freq_in_khz = clock_for_voltage_req->clocks_in_khz;
if (!pp_clock_request.clock_type)
return false;
if (adev->powerplay.pp_funcs->display_clock_voltage_request)
ret = adev->powerplay.pp_funcs->display_clock_voltage_request(
adev->powerplay.pp_handle,
&pp_clock_request);
if (ret)
return false;
return true;
}
bool dm_pp_get_static_clocks(
const struct dc_context *ctx,
struct dm_pp_static_clock_info *static_clk_info)
{
struct amdgpu_device *adev = ctx->driver_context;
struct amd_pp_clock_info pp_clk_info = {0};
int ret = 0;
if (adev->powerplay.pp_funcs->get_current_clocks)
ret = adev->powerplay.pp_funcs->get_current_clocks(
adev->powerplay.pp_handle,
&pp_clk_info);
if (ret)
return false;
static_clk_info->max_clocks_state = pp_clk_info.max_clocks_state;
static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock;
static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock;
return true;
}
void pp_rv_set_display_requirement(struct pp_smu *pp,
struct pp_smu_display_requirement_rv *req)
{
struct dc_context *ctx = pp->ctx;
struct amdgpu_device *adev = ctx->driver_context;
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
if (!pp_funcs || !pp_funcs->display_configuration_changed)
return;
amdgpu_dpm_display_configuration_changed(adev);
}
void pp_rv_set_wm_ranges(struct pp_smu *pp,
struct pp_smu_wm_range_sets *ranges)
{
struct dc_context *ctx = pp->ctx;
struct amdgpu_device *adev = ctx->driver_context;
void *pp_handle = adev->powerplay.pp_handle;
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks = wm_with_clock_ranges.wm_dmif_clocks_ranges;
struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks = wm_with_clock_ranges.wm_mcif_clocks_ranges;
int32_t i;
wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
if (ranges->reader_wm_sets[i].wm_inst > 3)
wm_dce_clocks[i].wm_set_id = WM_SET_A;
else
wm_dce_clocks[i].wm_set_id =
ranges->reader_wm_sets[i].wm_inst;
wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
ranges->reader_wm_sets[i].max_drain_clk_khz;
wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
ranges->reader_wm_sets[i].min_drain_clk_khz;
wm_dce_clocks[i].wm_max_mem_clk_in_khz =
ranges->reader_wm_sets[i].max_fill_clk_khz;
wm_dce_clocks[i].wm_min_mem_clk_in_khz =
ranges->reader_wm_sets[i].min_fill_clk_khz;
}
for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
if (ranges->writer_wm_sets[i].wm_inst > 3)
wm_soc_clocks[i].wm_set_id = WM_SET_A;
else
wm_soc_clocks[i].wm_set_id =
ranges->writer_wm_sets[i].wm_inst;
wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
ranges->writer_wm_sets[i].max_fill_clk_khz;
wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
ranges->writer_wm_sets[i].min_fill_clk_khz;
wm_soc_clocks[i].wm_max_mem_clk_in_khz =
ranges->writer_wm_sets[i].max_drain_clk_khz;
wm_soc_clocks[i].wm_min_mem_clk_in_khz =
ranges->writer_wm_sets[i].min_drain_clk_khz;
}
pp_funcs->set_watermarks_for_clocks_ranges(pp_handle, &wm_with_clock_ranges);
}
void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
{
struct dc_context *ctx = pp->ctx;
struct amdgpu_device *adev = ctx->driver_context;
void *pp_handle = adev->powerplay.pp_handle;
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
if (!pp_funcs || !pp_funcs->notify_smu_enable_pwe)
return;
pp_funcs->notify_smu_enable_pwe(pp_handle);
}
void dm_pp_get_funcs_rv(
struct dc_context *ctx,
struct pp_smu_funcs_rv *funcs)
{
funcs->pp_smu.ctx = ctx;
funcs->set_display_requirement = pp_rv_set_display_requirement;
funcs->set_wm_ranges = pp_rv_set_wm_ranges;
funcs->set_pme_wa_enable = pp_rv_set_pme_wa_enable;
}

324
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
View File

@ -35,6 +35,8 @@
#include "amdgpu_dm_irq.h"
#include "amdgpu_pm.h"
unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
unsigned long long current_time_stamp,
unsigned long long last_time_stamp)
@ -72,326 +74,4 @@ bool dm_read_persistent_data(struct dc_context *ctx,
/**** power component interfaces ****/
bool dm_pp_apply_display_requirements(
const struct dc_context *ctx,
const struct dm_pp_display_configuration *pp_display_cfg)
{
struct amdgpu_device *adev = ctx->driver_context;
if (adev->pm.dpm_enabled) {
memset(&adev->pm.pm_display_cfg, 0,
sizeof(adev->pm.pm_display_cfg));
adev->pm.pm_display_cfg.cpu_cc6_disable =
pp_display_cfg->cpu_cc6_disable;
adev->pm.pm_display_cfg.cpu_pstate_disable =
pp_display_cfg->cpu_pstate_disable;
adev->pm.pm_display_cfg.cpu_pstate_separation_time =
pp_display_cfg->cpu_pstate_separation_time;
adev->pm.pm_display_cfg.nb_pstate_switch_disable =
pp_display_cfg->nb_pstate_switch_disable;
adev->pm.pm_display_cfg.num_display =
pp_display_cfg->display_count;
adev->pm.pm_display_cfg.num_path_including_non_display =
pp_display_cfg->display_count;
adev->pm.pm_display_cfg.min_core_set_clock =
pp_display_cfg->min_engine_clock_khz/10;
adev->pm.pm_display_cfg.min_core_set_clock_in_sr =
pp_display_cfg->min_engine_clock_deep_sleep_khz/10;
adev->pm.pm_display_cfg.min_mem_set_clock =
pp_display_cfg->min_memory_clock_khz/10;
adev->pm.pm_display_cfg.multi_monitor_in_sync =
pp_display_cfg->all_displays_in_sync;
adev->pm.pm_display_cfg.min_vblank_time =
pp_display_cfg->avail_mclk_switch_time_us;
adev->pm.pm_display_cfg.display_clk =
pp_display_cfg->disp_clk_khz/10;
adev->pm.pm_display_cfg.dce_tolerable_mclk_in_active_latency =
pp_display_cfg->avail_mclk_switch_time_in_disp_active_us;
adev->pm.pm_display_cfg.crtc_index = pp_display_cfg->crtc_index;
adev->pm.pm_display_cfg.line_time_in_us =
pp_display_cfg->line_time_in_us;
adev->pm.pm_display_cfg.vrefresh = pp_display_cfg->disp_configs[0].v_refresh;
adev->pm.pm_display_cfg.crossfire_display_index = -1;
adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
/* TODO: complete implementation of
* pp_display_configuration_change().
* Follow example of:
* PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
* PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
if (adev->powerplay.pp_funcs->display_configuration_change)
adev->powerplay.pp_funcs->display_configuration_change(
adev->powerplay.pp_handle,
&adev->pm.pm_display_cfg);
/* TODO: replace by a separate call to 'apply display cfg'? */
amdgpu_pm_compute_clocks(adev);
}
return true;
}
static void get_default_clock_levels(
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels *clks)
{
uint32_t disp_clks_in_khz[6] = {
300000, 400000, 496560, 626090, 685720, 757900 };
uint32_t sclks_in_khz[6] = {
300000, 360000, 423530, 514290, 626090, 720000 };
uint32_t mclks_in_khz[2] = { 333000, 800000 };
switch (clk_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
clks->num_levels = 6;
memmove(clks->clocks_in_khz, disp_clks_in_khz,
sizeof(disp_clks_in_khz));
break;
case DM_PP_CLOCK_TYPE_ENGINE_CLK:
clks->num_levels = 6;
memmove(clks->clocks_in_khz, sclks_in_khz,
sizeof(sclks_in_khz));
break;
case DM_PP_CLOCK_TYPE_MEMORY_CLK:
clks->num_levels = 2;
memmove(clks->clocks_in_khz, mclks_in_khz,
sizeof(mclks_in_khz));
break;
default:
clks->num_levels = 0;
break;
}
}
static enum amd_pp_clock_type dc_to_pp_clock_type(
enum dm_pp_clock_type dm_pp_clk_type)
{
enum amd_pp_clock_type amd_pp_clk_type = 0;
switch (dm_pp_clk_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
amd_pp_clk_type = amd_pp_disp_clock;
break;
case DM_PP_CLOCK_TYPE_ENGINE_CLK:
amd_pp_clk_type = amd_pp_sys_clock;
break;
case DM_PP_CLOCK_TYPE_MEMORY_CLK:
amd_pp_clk_type = amd_pp_mem_clock;
break;
default:
DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
dm_pp_clk_type);
break;
}
return amd_pp_clk_type;
}
static void pp_to_dc_clock_levels(
const struct amd_pp_clocks *pp_clks,
struct dm_pp_clock_levels *dc_clks,
enum dm_pp_clock_type dc_clk_type)
{
uint32_t i;
if (pp_clks->count > DM_PP_MAX_CLOCK_LEVELS) {
DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
pp_clks->count,
DM_PP_MAX_CLOCK_LEVELS);
dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS;
} else
dc_clks->num_levels = pp_clks->count;
DRM_INFO("DM_PPLIB: values for %s clock\n",
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
for (i = 0; i < dc_clks->num_levels; i++) {
DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
/* translate 10kHz to kHz */
dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10;
}
}
static void pp_to_dc_clock_levels_with_latency(
const struct pp_clock_levels_with_latency *pp_clks,
struct dm_pp_clock_levels_with_latency *clk_level_info,
enum dm_pp_clock_type dc_clk_type)
{
uint32_t i;
if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
pp_clks->num_levels,
DM_PP_MAX_CLOCK_LEVELS);
clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
} else
clk_level_info->num_levels = pp_clks->num_levels;
DRM_DEBUG("DM_PPLIB: values for %s clock\n",
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
for (i = 0; i < clk_level_info->num_levels; i++) {
DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
}
}
bool dm_pp_get_clock_levels_by_type(
const struct dc_context *ctx,
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels *dc_clks)
{
struct amdgpu_device *adev = ctx->driver_context;
void *pp_handle = adev->powerplay.pp_handle;
struct amd_pp_clocks pp_clks = { 0 };
struct amd_pp_simple_clock_info validation_clks = { 0 };
uint32_t i;
if (adev->powerplay.pp_funcs->get_clock_by_type) {
if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
dc_to_pp_clock_type(clk_type), &pp_clks)) {
/* Error in pplib. Provide default values. */
get_default_clock_levels(clk_type, dc_clks);
return true;
}
}
pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
pp_handle, &validation_clks)) {
/* Error in pplib. Provide default values. */
DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
validation_clks.engine_max_clock = 72000;
validation_clks.memory_max_clock = 80000;
validation_clks.level = 0;
}
}
DRM_INFO("DM_PPLIB: Validation clocks:\n");
DRM_INFO("DM_PPLIB: engine_max_clock: %d\n",
validation_clks.engine_max_clock);
DRM_INFO("DM_PPLIB: memory_max_clock: %d\n",
validation_clks.memory_max_clock);
DRM_INFO("DM_PPLIB: level : %d\n",
validation_clks.level);
/* Translate 10 kHz to kHz. */
validation_clks.engine_max_clock *= 10;
validation_clks.memory_max_clock *= 10;
/* Determine the highest non-boosted level from the Validation Clocks */
if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) {
for (i = 0; i < dc_clks->num_levels; i++) {
if (dc_clks->clocks_in_khz[i] > validation_clks.engine_max_clock) {
/* This clock is higher the validation clock.
* Than means the previous one is the highest
* non-boosted one. */
DRM_INFO("DM_PPLIB: reducing engine clock level from %d to %d\n",
dc_clks->num_levels, i);
dc_clks->num_levels = i > 0 ? i : 1;
break;
}
}
} else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) {
for (i = 0; i < dc_clks->num_levels; i++) {
if (dc_clks->clocks_in_khz[i] > validation_clks.memory_max_clock) {
DRM_INFO("DM_PPLIB: reducing memory clock level from %d to %d\n",
dc_clks->num_levels, i);
dc_clks->num_levels = i > 0 ? i : 1;
break;
}
}
}
return true;
}
bool dm_pp_get_clock_levels_by_type_with_latency(
const struct dc_context *ctx,
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels_with_latency *clk_level_info)
{
struct amdgpu_device *adev = ctx->driver_context;
void *pp_handle = adev->powerplay.pp_handle;
struct pp_clock_levels_with_latency pp_clks = { 0 };
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
if (!pp_funcs || !pp_funcs->get_clock_by_type_with_latency)
return false;
if (pp_funcs->get_clock_by_type_with_latency(pp_handle,
dc_to_pp_clock_type(clk_type),
&pp_clks))
return false;
pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
return true;
}
bool dm_pp_get_clock_levels_by_type_with_voltage(
const struct dc_context *ctx,
enum dm_pp_clock_type clk_type,
struct dm_pp_clock_levels_with_voltage *clk_level_info)
{
/* TODO: to be implemented */
return false;
}
bool dm_pp_notify_wm_clock_changes(
const struct dc_context *ctx,
struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
{
/* TODO: to be implemented */
return false;
}
bool dm_pp_apply_power_level_change_request(
const struct dc_context *ctx,
struct dm_pp_power_level_change_request *level_change_req)
{
/* TODO: to be implemented */
return false;
}
bool dm_pp_apply_clock_for_voltage_request(
const struct dc_context *ctx,
struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)
{
/* TODO: to be implemented */
return false;
}
bool dm_pp_get_static_clocks(
const struct dc_context *ctx,
struct dm_pp_static_clock_info *static_clk_info)
{
/* TODO: to be implemented */
return false;
}
void dm_pp_get_funcs_rv(
struct dc_context *ctx,
struct pp_smu_funcs_rv *funcs)
{}
/**** end of power component interfaces ****/

196
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
View File

@ -3762,6 +3762,200 @@ static struct integrated_info *bios_parser_create_integrated_info(
return NULL;
}
enum bp_result update_slot_layout_info(
struct dc_bios *dcb,
unsigned int i,
struct slot_layout_info *slot_layout_info,
unsigned int record_offset)
{
unsigned int j;
struct bios_parser *bp;
ATOM_BRACKET_LAYOUT_RECORD *record;
ATOM_COMMON_RECORD_HEADER *record_header;
enum bp_result result = BP_RESULT_NORECORD;
bp = BP_FROM_DCB(dcb);
record = NULL;
record_header = NULL;
for (;;) {
record_header = (ATOM_COMMON_RECORD_HEADER *)
GET_IMAGE(ATOM_COMMON_RECORD_HEADER, record_offset);
if (record_header == NULL) {
result = BP_RESULT_BADBIOSTABLE;
break;
}
/* the end of the list */
if (record_header->ucRecordType == 0xff ||
record_header->ucRecordSize == 0) {
break;
}
if (record_header->ucRecordType ==
ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
sizeof(ATOM_BRACKET_LAYOUT_RECORD)
<= record_header->ucRecordSize) {
record = (ATOM_BRACKET_LAYOUT_RECORD *)
(record_header);
result = BP_RESULT_OK;
break;
}
record_offset += record_header->ucRecordSize;
}
/* return if the record not found */
if (result != BP_RESULT_OK)
return result;
/* get slot sizes */
slot_layout_info->length = record->ucLength;
slot_layout_info->width = record->ucWidth;
/* get info for each connector in the slot */
slot_layout_info->num_of_connectors = record->ucConnNum;
for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
slot_layout_info->connectors[j].connector_type =
(enum connector_layout_type)
(record->asConnInfo[j].ucConnectorType);
switch (record->asConnInfo[j].ucConnectorType) {
case CONNECTOR_TYPE_DVI_D:
slot_layout_info->connectors[j].connector_type =
CONNECTOR_LAYOUT_TYPE_DVI_D;
slot_layout_info->connectors[j].length =
CONNECTOR_SIZE_DVI;
break;
case CONNECTOR_TYPE_HDMI:
slot_layout_info->connectors[j].connector_type =
CONNECTOR_LAYOUT_TYPE_HDMI;
slot_layout_info->connectors[j].length =
CONNECTOR_SIZE_HDMI;
break;
case CONNECTOR_TYPE_DISPLAY_PORT:
slot_layout_info->connectors[j].connector_type =
CONNECTOR_LAYOUT_TYPE_DP;
slot_layout_info->connectors[j].length =
CONNECTOR_SIZE_DP;
break;
case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
slot_layout_info->connectors[j].connector_type =
CONNECTOR_LAYOUT_TYPE_MINI_DP;
slot_layout_info->connectors[j].length =
CONNECTOR_SIZE_MINI_DP;
break;
default:
slot_layout_info->connectors[j].connector_type =
CONNECTOR_LAYOUT_TYPE_UNKNOWN;
slot_layout_info->connectors[j].length =
CONNECTOR_SIZE_UNKNOWN;
}
slot_layout_info->connectors[j].position =
record->asConnInfo[j].ucPosition;
slot_layout_info->connectors[j].connector_id =
object_id_from_bios_object_id(
record->asConnInfo[j].usConnectorObjectId);
}
return result;
}
enum bp_result get_bracket_layout_record(
struct dc_bios *dcb,
unsigned int bracket_layout_id,
struct slot_layout_info *slot_layout_info)
{
unsigned int i;
unsigned int record_offset;
struct bios_parser *bp;
enum bp_result result;
ATOM_OBJECT *object;
ATOM_OBJECT_TABLE *object_table;
unsigned int genericTableOffset;
bp = BP_FROM_DCB(dcb);
object = NULL;
if (slot_layout_info == NULL) {
DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
return BP_RESULT_BADINPUT;
}
genericTableOffset = bp->object_info_tbl_offset +
bp->object_info_tbl.v1_3->usMiscObjectTableOffset;
object_table = (ATOM_OBJECT_TABLE *)
GET_IMAGE(ATOM_OBJECT_TABLE, genericTableOffset);
if (!object_table)
return BP_RESULT_FAILURE;
result = BP_RESULT_NORECORD;
for (i = 0; i < object_table->ucNumberOfObjects; ++i) {
if (bracket_layout_id ==
object_table->asObjects[i].usObjectID) {
object = &object_table->asObjects[i];
record_offset = object->usRecordOffset +
bp->object_info_tbl_offset;
result = update_slot_layout_info(dcb, i,
slot_layout_info, record_offset);
break;
}
}
return result;
}
static enum bp_result bios_get_board_layout_info(
struct dc_bios *dcb,
struct board_layout_info *board_layout_info)
{
unsigned int i;
struct bios_parser *bp;
enum bp_result record_result;
const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
0, 0
};
bp = BP_FROM_DCB(dcb);
if (board_layout_info == NULL) {
DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
return BP_RESULT_BADINPUT;
}
board_layout_info->num_of_slots = 0;
for (i = 0; i < MAX_BOARD_SLOTS; ++i) {
record_result = get_bracket_layout_record(dcb,
slot_index_to_vbios_id[i],
&board_layout_info->slots[i]);
if (record_result == BP_RESULT_NORECORD && i > 0)
break; /* no more slots present in bios */
else if (record_result != BP_RESULT_OK)
return record_result; /* fail */
++board_layout_info->num_of_slots;
}
/* all data is valid */
board_layout_info->is_number_of_slots_valid = 1;
board_layout_info->is_slots_size_valid = 1;
board_layout_info->is_connector_offsets_valid = 1;
board_layout_info->is_connector_lengths_valid = 1;
return BP_RESULT_OK;
}
/******************************************************************************/
static const struct dc_vbios_funcs vbios_funcs = {
@ -3836,6 +4030,8 @@ static const struct dc_vbios_funcs vbios_funcs = {
.post_init = bios_parser_post_init, /* patch vbios table for mxm module by reading i2c */
.bios_parser_destroy = bios_parser_destroy,
.get_board_layout_info = bios_get_board_layout_info,
};
static bool bios_parser_construct(

218
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
View File

@ -43,6 +43,29 @@
#include "bios_parser_interface.h"
#include "bios_parser_common.h"
/* Temporarily add in defines until ObjectID.h patch is updated in a few days */
#ifndef GENERIC_OBJECT_ID_BRACKET_LAYOUT
#define GENERIC_OBJECT_ID_BRACKET_LAYOUT 0x05
#endif /* GENERIC_OBJECT_ID_BRACKET_LAYOUT */
#ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1
#define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 \
(GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
#endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1 */
#ifndef GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2
#define GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 \
(GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
GENERIC_OBJECT_ID_BRACKET_LAYOUT << OBJECT_ID_SHIFT)
#endif /* GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2 */
#define DC_LOGGER \
bp->base.ctx->logger
#define LAST_RECORD_TYPE 0xff
#define SMU9_SYSPLL0_ID 0
@ -86,7 +109,6 @@ static struct atom_encoder_caps_record *get_encoder_cap_record(
#define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
static void destruct(struct bios_parser *bp)
{
kfree(bp->base.bios_local_image);
@ -1854,6 +1876,198 @@ static struct integrated_info *bios_parser_create_integrated_info(
return NULL;
}
static enum bp_result update_slot_layout_info(
struct dc_bios *dcb,
unsigned int i,
struct slot_layout_info *slot_layout_info)
{
unsigned int record_offset;
unsigned int j;
struct atom_display_object_path_v2 *object;
struct atom_bracket_layout_record *record;
struct atom_common_record_header *record_header;
enum bp_result result;
struct bios_parser *bp;
struct object_info_table *tbl;
struct display_object_info_table_v1_4 *v1_4;
record = NULL;
record_header = NULL;
result = BP_RESULT_NORECORD;
bp = BP_FROM_DCB(dcb);
tbl = &bp->object_info_tbl;
v1_4 = tbl->v1_4;
object = &v1_4->display_path[i];
record_offset = (unsigned int)
(object->disp_recordoffset) +
(unsigned int)(bp->object_info_tbl_offset);
for (;;) {
record_header = (struct atom_common_record_header *)
GET_IMAGE(struct atom_common_record_header,
record_offset);
if (record_header == NULL) {
result = BP_RESULT_BADBIOSTABLE;
break;
}
/* the end of the list */
if (record_header->record_type == 0xff ||
record_header->record_size == 0) {
break;
}
if (record_header->record_type ==
ATOM_BRACKET_LAYOUT_RECORD_TYPE &&
sizeof(struct atom_bracket_layout_record)
<= record_header->record_size) {
record = (struct atom_bracket_layout_record *)
(record_header);
result = BP_RESULT_OK;
break;
}
record_offset += record_header->record_size;
}
/* return if the record not found */
if (result != BP_RESULT_OK)
return result;
/* get slot sizes */
slot_layout_info->length = record->bracketlen;
slot_layout_info->width = record->bracketwidth;
/* get info for each connector in the slot */
slot_layout_info->num_of_connectors = record->conn_num;
for (j = 0; j < slot_layout_info->num_of_connectors; ++j) {
slot_layout_info->connectors[j].connector_type =
(enum connector_layout_type)
(record->conn_info[j].connector_type);
switch (record->conn_info[j].connector_type) {
case CONNECTOR_TYPE_DVI_D:
slot_layout_info->connectors[j].connector_type =
CONNECTOR_LAYOUT_TYPE_DVI_D;
slot_layout_info->connectors[j].length =
CONNECTOR_SIZE_DVI;
break;
case CONNECTOR_TYPE_HDMI:
slot_layout_info->connectors[j].connector_type =
CONNECTOR_LAYOUT_TYPE_HDMI;
slot_layout_info->connectors[j].length =
CONNECTOR_SIZE_HDMI;
break;
case CONNECTOR_TYPE_DISPLAY_PORT:
slot_layout_info->connectors[j].connector_type =
CONNECTOR_LAYOUT_TYPE_DP;
slot_layout_info->connectors[j].length =
CONNECTOR_SIZE_DP;
break;
case CONNECTOR_TYPE_MINI_DISPLAY_PORT:
slot_layout_info->connectors[j].connector_type =
CONNECTOR_LAYOUT_TYPE_MINI_DP;
slot_layout_info->connectors[j].length =
CONNECTOR_SIZE_MINI_DP;
break;
default:
slot_layout_info->connectors[j].connector_type =
CONNECTOR_LAYOUT_TYPE_UNKNOWN;
slot_layout_info->connectors[j].length =
CONNECTOR_SIZE_UNKNOWN;
}
slot_layout_info->connectors[j].position =
record->conn_info[j].position;
slot_layout_info->connectors[j].connector_id =
object_id_from_bios_object_id(
record->conn_info[j].connectorobjid);
}
return result;
}
static enum bp_result get_bracket_layout_record(
struct dc_bios *dcb,
unsigned int bracket_layout_id,
struct slot_layout_info *slot_layout_info)
{
unsigned int i;
struct bios_parser *bp = BP_FROM_DCB(dcb);
enum bp_result result;
struct object_info_table *tbl;
struct display_object_info_table_v1_4 *v1_4;
if (slot_layout_info == NULL) {
DC_LOG_DETECTION_EDID_PARSER("Invalid slot_layout_info\n");
return BP_RESULT_BADINPUT;
}
tbl = &bp->object_info_tbl;
v1_4 = tbl->v1_4;
result = BP_RESULT_NORECORD;
for (i = 0; i < v1_4->number_of_path; ++i) {
if (bracket_layout_id ==
v1_4->display_path[i].display_objid) {
result = update_slot_layout_info(dcb, i,
slot_layout_info);
break;
}
}
return result;
}
static enum bp_result bios_get_board_layout_info(
struct dc_bios *dcb,
struct board_layout_info *board_layout_info)
{
unsigned int i;
struct bios_parser *bp;
enum bp_result record_result;
const unsigned int slot_index_to_vbios_id[MAX_BOARD_SLOTS] = {
GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID1,
GENERICOBJECT_BRACKET_LAYOUT_ENUM_ID2,
0, 0
};
bp = BP_FROM_DCB(dcb);
if (board_layout_info == NULL) {
DC_LOG_DETECTION_EDID_PARSER("Invalid board_layout_info\n");
return BP_RESULT_BADINPUT;
}
board_layout_info->num_of_slots = 0;
for (i = 0; i < MAX_BOARD_SLOTS; ++i) {
record_result = get_bracket_layout_record(dcb,
slot_index_to_vbios_id[i],
&board_layout_info->slots[i]);
if (record_result == BP_RESULT_NORECORD && i > 0)
break; /* no more slots present in bios */
else if (record_result != BP_RESULT_OK)
return record_result; /* fail */
++board_layout_info->num_of_slots;
}
/* all data is valid */
board_layout_info->is_number_of_slots_valid = 1;
board_layout_info->is_slots_size_valid = 1;
board_layout_info->is_connector_offsets_valid = 1;
board_layout_info->is_connector_lengths_valid = 1;
return BP_RESULT_OK;
}
static const struct dc_vbios_funcs vbios_funcs = {
.get_connectors_number = bios_parser_get_connectors_number,
@ -1925,6 +2139,8 @@ static const struct dc_vbios_funcs vbios_funcs = {
.bios_parser_destroy = firmware_parser_destroy,
.get_smu_clock_info = bios_parser_get_smu_clock_info,
.get_board_layout_info = bios_get_board_layout_info,
};
static bool bios_parser_construct(

46
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
View File

@ -59,36 +59,7 @@
bios_cmd_table_para_revision(bp->base.ctx->driver_context, \
GET_INDEX_INTO_MASTER_TABLE(command, fname))
static void init_dig_encoder_control(struct bios_parser *bp);
static void init_transmitter_control(struct bios_parser *bp);
static void init_set_pixel_clock(struct bios_parser *bp);
static void init_set_crtc_timing(struct bios_parser *bp);
static void init_select_crtc_source(struct bios_parser *bp);
static void init_enable_crtc(struct bios_parser *bp);
static void init_external_encoder_control(struct bios_parser *bp);
static void init_enable_disp_power_gating(struct bios_parser *bp);
static void init_set_dce_clock(struct bios_parser *bp);
static void init_get_smu_clock_info(struct bios_parser *bp);
void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
{
init_dig_encoder_control(bp);
init_transmitter_control(bp);
init_set_pixel_clock(bp);
init_set_crtc_timing(bp);
init_select_crtc_source(bp);
init_enable_crtc(bp);
init_external_encoder_control(bp);
init_enable_disp_power_gating(bp);
init_set_dce_clock(bp);
init_get_smu_clock_info(bp);
}
static uint32_t bios_cmd_table_para_revision(void *dev,
uint32_t index)
@ -829,3 +800,20 @@ static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id)
return 0;
}
void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
{
init_dig_encoder_control(bp);
init_transmitter_control(bp);
init_set_pixel_clock(bp);
init_set_crtc_timing(bp);
init_select_crtc_source(bp);
init_enable_crtc(bp);
init_external_encoder_control(bp);
init_enable_disp_power_gating(bp);
init_set_dce_clock(bp);
init_get_smu_clock_info(bp);
}

194
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
View File

@ -31,6 +31,8 @@
#include "resource.h"
#include "dcn10/dcn10_resource.h"
#include "dcn10/dcn10_hubbub.h"
#include "dcn_calc_math.h"
#define DC_LOGGER \
@ -423,6 +425,10 @@ static void dcn_bw_calc_rq_dlg_ttu(
int total_flip_bytes = 0;
int i;
memset(dlg_regs, 0, sizeof(*dlg_regs));
memset(ttu_regs, 0, sizeof(*ttu_regs));
memset(rq_regs, 0, sizeof(*rq_regs));
for (i = 0; i < number_of_planes; i++) {
total_active_bw += v->read_bandwidth[i];
total_prefetch_bw += v->prefetch_bandwidth[i];
@ -501,6 +507,7 @@ static void split_stream_across_pipes(
resource_build_scaling_params(secondary_pipe);
}
#if 0
static void calc_wm_sets_and_perf_params(
struct dc_state *context,
struct dcn_bw_internal_vars *v)
@ -582,6 +589,7 @@ static void calc_wm_sets_and_perf_params(
if (v->voltage_level >= 3)
context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
}
#endif
static bool dcn_bw_apply_registry_override(struct dc *dc)
{
@ -883,7 +891,26 @@ bool dcn_validate_bandwidth(
ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
|| v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
}
v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
if (dc->debug.optimized_watermark) {
/*
* this method requires us to always re-calculate watermark when dcc change
* between flip.
*/
v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
} else {
/*
* allow us to disable dcc on the fly without re-calculating WM
*
* extra overhead for DCC is quite small. for 1080p WM without
* DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
*/
unsigned int bpe;
v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(
pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
}
v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
pipe->plane_state->format);
v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
@ -976,43 +1003,60 @@ bool dcn_validate_bandwidth(
bw_consumed = v->fabric_and_dram_bandwidth;
display_pipe_configuration(v);
calc_wm_sets_and_perf_params(context, v);
context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 /
/*calc_wm_sets_and_perf_params(context, v);*/
/* Only 1 set is used by dcn since no noticeable
* performance improvement was measured and due to hw bug DEGVIDCN10-254
*/
dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
v->stutter_exit_watermark * 1000;
context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
v->stutter_enter_plus_exit_watermark * 1000;
context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
v->dram_clock_change_watermark * 1000;
context->bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
context->bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
context->bw.dcn.watermarks.b = context->bw.dcn.watermarks.a;
context->bw.dcn.watermarks.c = context->bw.dcn.watermarks.a;
context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
context->bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /
(ddr4_dram_factor_single_Channel * v->number_of_channels));
if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) {
context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
context->bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
}
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000);
context->bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
context->bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000);
context->bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
if (dc->debug.max_disp_clk == true)
context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
context->bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
if (context->bw.dcn.calc_clk.dispclk_khz <
if (context->bw.dcn.clk.dispclk_khz <
dc->debug.min_disp_clk_khz) {
context->bw.dcn.calc_clk.dispclk_khz =
context->bw.dcn.clk.dispclk_khz =
dc->debug.min_disp_clk_khz;
}
context->bw.dcn.calc_clk.dppclk_khz = context->bw.dcn.calc_clk.dispclk_khz / v->dispclk_dppclk_ratio;
context->bw.dcn.clk.dppclk_khz = context->bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio;
context->bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
switch (v->voltage_level) {
case 0:
context->bw.dcn.calc_clk.max_supported_dppclk_khz =
context->bw.dcn.clk.max_supported_dppclk_khz =
(int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);
break;
case 1:
context->bw.dcn.calc_clk.max_supported_dppclk_khz =
context->bw.dcn.clk.max_supported_dppclk_khz =
(int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);
break;
case 2:
context->bw.dcn.calc_clk.max_supported_dppclk_khz =
context->bw.dcn.clk.max_supported_dppclk_khz =
(int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);
break;
default:
context->bw.dcn.calc_clk.max_supported_dppclk_khz =
context->bw.dcn.clk.max_supported_dppclk_khz =
(int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);
break;
}
@ -1225,27 +1269,27 @@ static unsigned int dcn_find_normalized_clock_vdd_Level(
unsigned int dcn_find_dcfclk_suits_all(
const struct dc *dc,
struct clocks_value *clocks)
struct dc_clocks *clocks)
{
unsigned vdd_level, vdd_level_temp;
unsigned dcf_clk;
/*find a common supported voltage level*/
vdd_level = dcn_find_normalized_clock_vdd_Level(
dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_in_khz);
dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);
vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_in_khz);
dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);
vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_in_khz);
dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->dcfclock_in_khz);
dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);
vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclock_in_khz);
dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);
/*find that level conresponding dcfclk*/
vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
@ -1331,21 +1375,14 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
{
struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu;
struct pp_smu_wm_range_sets ranges = {0};
int max_fclk_khz, nom_fclk_khz, mid_fclk_khz, min_fclk_khz;
int max_dcfclk_khz, min_dcfclk_khz;
int socclk_khz;
int min_fclk_khz, min_dcfclk_khz, socclk_khz;
const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
if (!pp->set_wm_ranges)
return;
kernel_fpu_begin();
max_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000000 / factor;
nom_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000000 / factor;
mid_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000000 / factor;
min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
max_dcfclk_khz = dc->dcn_soc->dcfclkv_max0p9 * 1000;
min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
socclk_khz = dc->dcn_soc->socclk * 1000;
kernel_fpu_end();
@ -1353,105 +1390,46 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
/* Now notify PPLib/SMU about which Watermarks sets they should select
* depending on DPM state they are in. And update BW MGR GFX Engine and
* Memory clock member variables for Watermarks calculations for each
* Watermark Set
* Watermark Set. Only one watermark set for dcn1 due to hw bug DEGVIDCN10-254.
*/
/* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
* care what the value is, hence min to overdrive level
*/
ranges.num_reader_wm_sets = WM_COUNT;
ranges.num_writer_wm_sets = WM_COUNT;
ranges.num_reader_wm_sets = WM_SET_COUNT;
ranges.num_writer_wm_sets = WM_SET_COUNT;
ranges.reader_wm_sets[0].wm_inst = WM_A;
ranges.reader_wm_sets[0].min_drain_clk_khz = min_dcfclk_khz;
ranges.reader_wm_sets[0].max_drain_clk_khz = max_dcfclk_khz;
ranges.reader_wm_sets[0].max_drain_clk_khz = overdrive;
ranges.reader_wm_sets[0].min_fill_clk_khz = min_fclk_khz;
ranges.reader_wm_sets[0].max_fill_clk_khz = min_fclk_khz;
ranges.reader_wm_sets[0].max_fill_clk_khz = overdrive;
ranges.writer_wm_sets[0].wm_inst = WM_A;
ranges.writer_wm_sets[0].min_fill_clk_khz = socclk_khz;
ranges.writer_wm_sets[0].max_fill_clk_khz = overdrive;
ranges.writer_wm_sets[0].min_drain_clk_khz = min_fclk_khz;
ranges.writer_wm_sets[0].max_drain_clk_khz = min_fclk_khz;
ranges.reader_wm_sets[1].wm_inst = WM_B;
ranges.reader_wm_sets[1].min_drain_clk_khz = min_fclk_khz;
ranges.reader_wm_sets[1].max_drain_clk_khz = max_dcfclk_khz;
ranges.reader_wm_sets[1].min_fill_clk_khz = mid_fclk_khz;
ranges.reader_wm_sets[1].max_fill_clk_khz = mid_fclk_khz;
ranges.writer_wm_sets[1].wm_inst = WM_B;
ranges.writer_wm_sets[1].min_fill_clk_khz = socclk_khz;
ranges.writer_wm_sets[1].max_fill_clk_khz = overdrive;
ranges.writer_wm_sets[1].min_drain_clk_khz = mid_fclk_khz;
ranges.writer_wm_sets[1].max_drain_clk_khz = mid_fclk_khz;
ranges.reader_wm_sets[2].wm_inst = WM_C;
ranges.reader_wm_sets[2].min_drain_clk_khz = min_fclk_khz;
ranges.reader_wm_sets[2].max_drain_clk_khz = max_dcfclk_khz;
ranges.reader_wm_sets[2].min_fill_clk_khz = nom_fclk_khz;
ranges.reader_wm_sets[2].max_fill_clk_khz = nom_fclk_khz;
ranges.writer_wm_sets[2].wm_inst = WM_C;
ranges.writer_wm_sets[2].min_fill_clk_khz = socclk_khz;
ranges.writer_wm_sets[2].max_fill_clk_khz = overdrive;
ranges.writer_wm_sets[2].min_drain_clk_khz = nom_fclk_khz;
ranges.writer_wm_sets[2].max_drain_clk_khz = nom_fclk_khz;
ranges.reader_wm_sets[3].wm_inst = WM_D;
ranges.reader_wm_sets[3].min_drain_clk_khz = min_fclk_khz;
ranges.reader_wm_sets[3].max_drain_clk_khz = max_dcfclk_khz;
ranges.reader_wm_sets[3].min_fill_clk_khz = max_fclk_khz;
ranges.reader_wm_sets[3].max_fill_clk_khz = max_fclk_khz;
ranges.writer_wm_sets[3].wm_inst = WM_D;
ranges.writer_wm_sets[3].min_fill_clk_khz = socclk_khz;
ranges.writer_wm_sets[3].max_fill_clk_khz = overdrive;
ranges.writer_wm_sets[3].min_drain_clk_khz = max_fclk_khz;
ranges.writer_wm_sets[3].max_drain_clk_khz = max_fclk_khz;
ranges.writer_wm_sets[0].max_drain_clk_khz = overdrive;
if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
ranges.reader_wm_sets[0].wm_inst = WM_A;
ranges.reader_wm_sets[0].min_drain_clk_khz = 300000;
ranges.reader_wm_sets[0].max_drain_clk_khz = 654000;
ranges.reader_wm_sets[0].max_drain_clk_khz = 5000000;
ranges.reader_wm_sets[0].min_fill_clk_khz = 800000;
ranges.reader_wm_sets[0].max_fill_clk_khz = 800000;
ranges.reader_wm_sets[0].max_fill_clk_khz = 5000000;
ranges.writer_wm_sets[0].wm_inst = WM_A;
ranges.writer_wm_sets[0].min_fill_clk_khz = 200000;
ranges.writer_wm_sets[0].max_fill_clk_khz = 757000;
ranges.writer_wm_sets[0].max_fill_clk_khz = 5000000;
ranges.writer_wm_sets[0].min_drain_clk_khz = 800000;
ranges.writer_wm_sets[0].max_drain_clk_khz = 800000;
ranges.reader_wm_sets[1].wm_inst = WM_B;
ranges.reader_wm_sets[1].min_drain_clk_khz = 300000;
ranges.reader_wm_sets[1].max_drain_clk_khz = 654000;
ranges.reader_wm_sets[1].min_fill_clk_khz = 933000;
ranges.reader_wm_sets[1].max_fill_clk_khz = 933000;
ranges.writer_wm_sets[1].wm_inst = WM_B;
ranges.writer_wm_sets[1].min_fill_clk_khz = 200000;
ranges.writer_wm_sets[1].max_fill_clk_khz = 757000;
ranges.writer_wm_sets[1].min_drain_clk_khz = 933000;
ranges.writer_wm_sets[1].max_drain_clk_khz = 933000;
ranges.reader_wm_sets[2].wm_inst = WM_C;
ranges.reader_wm_sets[2].min_drain_clk_khz = 300000;
ranges.reader_wm_sets[2].max_drain_clk_khz = 654000;
ranges.reader_wm_sets[2].min_fill_clk_khz = 1067000;
ranges.reader_wm_sets[2].max_fill_clk_khz = 1067000;
ranges.writer_wm_sets[2].wm_inst = WM_C;
ranges.writer_wm_sets[2].min_fill_clk_khz = 200000;
ranges.writer_wm_sets[2].max_fill_clk_khz = 757000;
ranges.writer_wm_sets[2].min_drain_clk_khz = 1067000;
ranges.writer_wm_sets[2].max_drain_clk_khz = 1067000;
ranges.reader_wm_sets[3].wm_inst = WM_D;
ranges.reader_wm_sets[3].min_drain_clk_khz = 300000;
ranges.reader_wm_sets[3].max_drain_clk_khz = 654000;
ranges.reader_wm_sets[3].min_fill_clk_khz = 1200000;
ranges.reader_wm_sets[3].max_fill_clk_khz = 1200000;
ranges.writer_wm_sets[3].wm_inst = WM_D;
ranges.writer_wm_sets[3].min_fill_clk_khz = 200000;
ranges.writer_wm_sets[3].max_fill_clk_khz = 757000;
ranges.writer_wm_sets[3].min_drain_clk_khz = 1200000;
ranges.writer_wm_sets[3].max_drain_clk_khz = 1200000;
ranges.writer_wm_sets[0].max_drain_clk_khz = 5000000;
}
ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0];
ranges.reader_wm_sets[1].wm_inst = WM_B;
ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0];
ranges.reader_wm_sets[2].wm_inst = WM_C;
ranges.reader_wm_sets[3] = ranges.writer_wm_sets[0];
ranges.reader_wm_sets[3].wm_inst = WM_D;
/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
pp->set_wm_ranges(&pp->pp_smu, &ranges);
}

5
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -944,12 +944,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
dc->optimized_required = false;
/* 3rd param should be true, temp w/a for RV*/
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
dc->hwss.set_bandwidth(dc, context, dc->ctx->dce_version < DCN_VERSION_1_0);
#else
dc->hwss.set_bandwidth(dc, context, true);
#endif
return true;
}

24
drivers/gpu/drm/amd/display/dc/core/dc_debug.c
View File

@ -352,19 +352,19 @@ void context_clock_trace(
DC_LOGGER_INIT(dc->ctx->logger);
CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
"dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
context->bw.dcn.calc_clk.dispclk_khz,
context->bw.dcn.calc_clk.dppclk_khz,
context->bw.dcn.calc_clk.dcfclk_khz,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
context->bw.dcn.calc_clk.fclk_khz,
context->bw.dcn.calc_clk.socclk_khz);
context->bw.dcn.clk.dispclk_khz,
context->bw.dcn.clk.dppclk_khz,
context->bw.dcn.clk.dcfclk_khz,
context->bw.dcn.clk.dcfclk_deep_sleep_khz,
context->bw.dcn.clk.fclk_khz,
context->bw.dcn.clk.socclk_khz);
CLOCK_TRACE("Calculated: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
"dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
context->bw.dcn.calc_clk.dispclk_khz,
context->bw.dcn.calc_clk.dppclk_khz,
context->bw.dcn.calc_clk.dcfclk_khz,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
context->bw.dcn.calc_clk.fclk_khz,
context->bw.dcn.calc_clk.socclk_khz);
context->bw.dcn.clk.dispclk_khz,
context->bw.dcn.clk.dppclk_khz,
context->bw.dcn.clk.dcfclk_khz,
context->bw.dcn.clk.dcfclk_deep_sleep_khz,
context->bw.dcn.clk.fclk_khz,
context->bw.dcn.clk.socclk_khz);
#endif
}

36
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -33,6 +33,7 @@
#include "dc_link_dp.h"
#include "dc_link_ddc.h"
#include "link_hwss.h"
#include "opp.h"
#include "link_encoder.h"
#include "hw_sequencer.h"
@ -1284,29 +1285,15 @@ static enum dc_status enable_link_dp(
max_link_rate = LINK_RATE_HIGH3;
if (link_settings.link_rate == max_link_rate) {
if (state->dis_clk->funcs->set_min_clocks_state) {
if (state->dis_clk->cur_min_clks_state < DM_PP_CLOCKS_STATE_NOMINAL)
state->dis_clk->funcs->set_min_clocks_state(
state->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL);
} else {
uint32_t dp_phyclk_in_khz;
const struct clocks_value clocks_value =
state->dis_clk->cur_clocks_value;
struct dc_clocks clocks = state->bw.dcn.clk;
/* 27mhz = 27000000hz= 27000khz */
dp_phyclk_in_khz = link_settings.link_rate * 27000;
/* dce/dcn compat, do not update dispclk */
clocks.dispclk_khz = 0;
/* 27mhz = 27000000hz= 27000khz */
clocks.phyclk_khz = link_settings.link_rate * 27000;
if (((clocks_value.max_non_dp_phyclk_in_khz != 0) &&
(dp_phyclk_in_khz > clocks_value.max_non_dp_phyclk_in_khz)) ||
(dp_phyclk_in_khz > clocks_value.max_dp_phyclk_in_khz)) {
state->dis_clk->funcs->apply_clock_voltage_request(
state->dis_clk,
DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
dp_phyclk_in_khz,
false,
true);
}
}
state->dis_clk->funcs->update_clocks(
state->dis_clk, &clocks, false);
}
dp_enable_link_phy(
@ -2396,9 +2383,10 @@ void core_link_enable_stream(
core_dc->hwss.enable_audio_stream(pipe_ctx);
/* turn off otg test pattern if enable */
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
COLOR_DEPTH_UNDEFINED);
if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
COLOR_DEPTH_UNDEFINED);
core_dc->hwss.enable_stream(pipe_ctx);

11
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View File

@ -3,6 +3,7 @@
#include "dc.h"
#include "dc_link_dp.h"
#include "dm_helpers.h"
#include "opp.h"
#include "inc/core_types.h"
#include "link_hwss.h"
@ -1999,7 +2000,7 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
{
union hpd_irq_data hpd_irq_dpcd_data = {{{{0}}}};
union device_service_irq device_service_clear = { { 0 } };
enum dc_status result = DDC_RESULT_UNKNOWN;
enum dc_status result;
bool status = false;
/* For use cases related to down stream connection status change,
* PSR and device auto test, refer to function handle_sst_hpd_irq
@ -2511,8 +2512,8 @@ static void set_crtc_test_pattern(struct dc_link *link,
pipe_ctx->stream->bit_depth_params = params;
pipe_ctx->stream_res.opp->funcs->
opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
controller_test_pattern, color_depth);
}
break;
@ -2524,8 +2525,8 @@ static void set_crtc_test_pattern(struct dc_link *link,
pipe_ctx->stream->bit_depth_params = params;
pipe_ctx->stream_res.opp->funcs->
opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
color_depth);
}

2
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -1948,7 +1948,7 @@ void dc_resource_state_construct(
const struct dc *dc,
struct dc_state *dst_ctx)
{
dst_ctx->dis_clk = dc->res_pool->display_clock;
dst_ctx->dis_clk = dc->res_pool->dccg;
}
enum dc_status dc_validate_global_state(

8
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -38,7 +38,7 @@
#include "inc/compressor.h"
#include "dml/display_mode_lib.h"
#define DC_VER "3.1.47"
#define DC_VER "3.1.52"
#define MAX_SURFACES 3
#define MAX_STREAMS 6
@ -186,6 +186,10 @@ enum wm_report_mode {
WM_REPORT_OVERRIDE = 1,
};
/*
* For any clocks that may differ per pipe
* only the max is stored in this structure
*/
struct dc_clocks {
int dispclk_khz;
int max_supported_dppclk_khz;
@ -194,6 +198,7 @@ struct dc_clocks {
int socclk_khz;
int dcfclk_deep_sleep_khz;
int fclk_khz;
int phyclk_khz;
};
struct dc_debug {
@ -228,6 +233,7 @@ struct dc_debug {
int urgent_latency_ns;
int percent_of_ideal_drambw;
int dram_clock_change_latency_ns;
bool optimized_watermark;
int always_scale;
bool disable_pplib_clock_request;
bool disable_clock_gate;

4
drivers/gpu/drm/amd/display/dc/dc_bios_types.h
View File

@ -198,6 +198,10 @@ struct dc_vbios_funcs {
void (*post_init)(struct dc_bios *bios);
void (*bios_parser_destroy)(struct dc_bios **dcb);
enum bp_result (*get_board_layout_info)(
struct dc_bios *dcb,
struct board_layout_info *board_layout_info);
};
struct bios_registers {

1
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
View File

@ -199,6 +199,7 @@ enum surface_pixel_format {
SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb,
SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
SURFACE_PIXEL_FORMAT_INVALID
/*grow 444 video here if necessary */

10
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
View File

@ -133,7 +133,7 @@ static bool calculate_fb_and_fractional_fb_divider(
uint64_t feedback_divider;
feedback_divider =
(uint64_t)(target_pix_clk_khz * ref_divider * post_divider);
(uint64_t)target_pix_clk_khz * ref_divider * post_divider;
feedback_divider *= 10;
/* additional factor, since we divide by 10 afterwards */
feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
@ -145,8 +145,8 @@ static bool calculate_fb_and_fractional_fb_divider(
* of fractional feedback decimal point and the fractional FB Divider precision
* is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
feedback_divider += (uint64_t)
(5 * calc_pll_cs->fract_fb_divider_precision_factor);
feedback_divider += 5ULL *
calc_pll_cs->fract_fb_divider_precision_factor;
feedback_divider =
div_u64(feedback_divider,
calc_pll_cs->fract_fb_divider_precision_factor * 10);
@ -203,8 +203,8 @@ static bool calc_fb_divider_checking_tolerance(
&fract_feedback_divider);
/*Actual calculated value*/
actual_calc_clk_khz = (uint64_t)(feedback_divider *
calc_pll_cs->fract_fb_divider_factor) +
actual_calc_clk_khz = (uint64_t)feedback_divider *
calc_pll_cs->fract_fb_divider_factor +
fract_feedback_divider;
actual_calc_clk_khz *= calc_pll_cs->ref_freq_khz;
actual_calc_clk_khz =

738
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
View File

@ -38,7 +38,7 @@
#include "dal_asic_id.h"
#define TO_DCE_CLOCKS(clocks)\
container_of(clocks, struct dce_disp_clk, base)
container_of(clocks, struct dce_dccg, base)
#define REG(reg) \
(clk_dce->regs->reg)
@ -101,99 +101,78 @@ static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
/*ClocksStatePerformance*/
{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
/* Starting point for each divider range.*/
enum dce_divider_range_start {
DIVIDER_RANGE_01_START = 200, /* 2.00*/
DIVIDER_RANGE_02_START = 1600, /* 16.00*/
DIVIDER_RANGE_03_START = 3200, /* 32.00*/
DIVIDER_RANGE_SCALE_FACTOR = 100 /* Results are scaled up by 100.*/
/* Starting DID for each range */
enum dentist_base_divider_id {
DENTIST_BASE_DID_1 = 0x08,
DENTIST_BASE_DID_2 = 0x40,
DENTIST_BASE_DID_3 = 0x60,
DENTIST_MAX_DID = 0x80
};
/* Ranges for divider identifiers (Divider ID or DID)
mmDENTIST_DISPCLK_CNTL.DENTIST_DISPCLK_WDIVIDER*/
enum dce_divider_id_register_setting {
DIVIDER_RANGE_01_BASE_DIVIDER_ID = 0X08,
DIVIDER_RANGE_02_BASE_DIVIDER_ID = 0X40,
DIVIDER_RANGE_03_BASE_DIVIDER_ID = 0X60,
DIVIDER_RANGE_MAX_DIVIDER_ID = 0X80
/* Starting point and step size for each divider range.*/
enum dentist_divider_range {
DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */
DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */
DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */
DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */
DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */
DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
};
/* Step size between each divider within a range.
Incrementing the DENTIST_DISPCLK_WDIVIDER by one
will increment the divider by this much.*/
enum dce_divider_range_step_size {
DIVIDER_RANGE_01_STEP_SIZE = 25, /* 0.25*/
DIVIDER_RANGE_02_STEP_SIZE = 50, /* 0.50*/
DIVIDER_RANGE_03_STEP_SIZE = 100 /* 1.00 */
};
static bool dce_divider_range_construct(
struct dce_divider_range *div_range,
int range_start,
int range_step,
int did_min,
int did_max)
static int dentist_get_divider_from_did(int did)
{
div_range->div_range_start = range_start;
div_range->div_range_step = range_step;
div_range->did_min = did_min;
div_range->did_max = did_max;
if (did < DENTIST_BASE_DID_1)
did = DENTIST_BASE_DID_1;
if (did > DENTIST_MAX_DID)
did = DENTIST_MAX_DID;
if (div_range->div_range_step == 0) {
div_range->div_range_step = 1;
/*div_range_step cannot be zero*/
BREAK_TO_DEBUGGER();
if (did < DENTIST_BASE_DID_2) {
return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP
* (did - DENTIST_BASE_DID_1);
} else if (did < DENTIST_BASE_DID_3) {
return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP
* (did - DENTIST_BASE_DID_2);
} else {
return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP
* (did - DENTIST_BASE_DID_3);
}
/* Calculate this based on the other inputs.*/
/* See DividerRange.h for explanation of */
/* the relationship between divider id (DID) and a divider.*/
/* Number of Divider IDs = (Maximum Divider ID - Minimum Divider ID)*/
/* Maximum divider identified in this range =
* (Number of Divider IDs)*Step size between dividers
* + The start of this range.*/
div_range->div_range_end = (did_max - did_min) * range_step
+ range_start;
return true;
}
static int dce_divider_range_calc_divider(
struct dce_divider_range *div_range,
int did)
/* SW will adjust DP REF Clock average value for all purposes
* (DP DTO / DP Audio DTO and DP GTC)
if clock is spread for all cases:
-if SS enabled on DP Ref clock and HW de-spreading enabled with SW
calculations for DS_INCR/DS_MODULO (this is planned to be default case)
-if SS enabled on DP Ref clock and HW de-spreading enabled with HW
calculations (not planned to be used, but average clock should still
be valid)
-if SS enabled on DP Ref clock and HW de-spreading disabled
(should not be case with CIK) then SW should program all rates
generated according to average value (case as with previous ASICs)
*/
static int dccg_adjust_dp_ref_freq_for_ss(struct dce_dccg *clk_dce, int dp_ref_clk_khz)
{
/* Is this DID within our range?*/
if ((did < div_range->did_min) || (did >= div_range->did_max))
return INVALID_DIVIDER;
if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
struct fixed31_32 ss_percentage = dc_fixpt_div_int(
dc_fixpt_from_fraction(clk_dce->dprefclk_ss_percentage,
clk_dce->dprefclk_ss_divider), 200);
struct fixed31_32 adj_dp_ref_clk_khz;
return ((did - div_range->did_min) * div_range->div_range_step)
+ div_range->div_range_start;
}
static int dce_divider_range_get_divider(
struct dce_divider_range *div_range,
int ranges_num,
int did)
{
int div = INVALID_DIVIDER;
int i;
for (i = 0; i < ranges_num; i++) {
/* Calculate divider with given divider ID*/
div = dce_divider_range_calc_divider(&div_range[i], did);
/* Found a valid return divider*/
if (div != INVALID_DIVIDER)
break;
ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage);
adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz);
dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
}
return div;
return dp_ref_clk_khz;
}
static int dce_clocks_get_dp_ref_freq(struct display_clock *clk)
static int dce_get_dp_ref_freq_khz(struct dccg *clk)
{
struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
int dprefclk_wdivider;
int dprefclk_src_sel;
int dp_ref_clk_khz = 600000;
int target_div = INVALID_DIVIDER;
int target_div;
/* ASSERT DP Reference Clock source is from DFS*/
REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);
@ -204,80 +183,27 @@ static int dce_clocks_get_dp_ref_freq(struct display_clock *clk)
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
target_div = dce_divider_range_get_divider(
clk_dce->divider_ranges,
DIVIDER_RANGE_MAX,
dprefclk_wdivider);
target_div = dentist_get_divider_from_did(dprefclk_wdivider);
if (target_div != INVALID_DIVIDER) {
/* Calculate the current DFS clock, in kHz.*/
dp_ref_clk_khz = (DIVIDER_RANGE_SCALE_FACTOR
* clk_dce->dentist_vco_freq_khz) / target_div;
}
/* Calculate the current DFS clock, in kHz.*/
dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
* clk_dce->dentist_vco_freq_khz) / target_div;
/* SW will adjust DP REF Clock average value for all purposes
* (DP DTO / DP Audio DTO and DP GTC)
if clock is spread for all cases:
-if SS enabled on DP Ref clock and HW de-spreading enabled with SW
calculations for DS_INCR/DS_MODULO (this is planned to be default case)
-if SS enabled on DP Ref clock and HW de-spreading enabled with HW
calculations (not planned to be used, but average clock should still
be valid)
-if SS enabled on DP Ref clock and HW de-spreading disabled
(should not be case with CIK) then SW should program all rates
generated according to average value (case as with previous ASICs)
*/
if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
struct fixed31_32 ss_percentage = dc_fixpt_div_int(
dc_fixpt_from_fraction(
clk_dce->dprefclk_ss_percentage,
clk_dce->dprefclk_ss_divider), 200);
struct fixed31_32 adj_dp_ref_clk_khz;
ss_percentage = dc_fixpt_sub(dc_fixpt_one,
ss_percentage);
adj_dp_ref_clk_khz =
dc_fixpt_mul_int(
ss_percentage,
dp_ref_clk_khz);
dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
}
return dp_ref_clk_khz;
return dccg_adjust_dp_ref_freq_for_ss(clk_dce, dp_ref_clk_khz);
}
/* TODO: This is DCN DPREFCLK: it could be program by DENTIST by VBIOS
* or CLK0_CLK11 by SMU. For DCE120, it is wlays 600Mhz. Will re-visit
* clock implementation
*/
static int dce_clocks_get_dp_ref_freq_wrkaround(struct display_clock *clk)
static int dce12_get_dp_ref_freq_khz(struct dccg *clk)
{
struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
int dp_ref_clk_khz = 600000;
struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) {
struct fixed31_32 ss_percentage = dc_fixpt_div_int(
dc_fixpt_from_fraction(
clk_dce->dprefclk_ss_percentage,
clk_dce->dprefclk_ss_divider), 200);
struct fixed31_32 adj_dp_ref_clk_khz;
ss_percentage = dc_fixpt_sub(dc_fixpt_one,
ss_percentage);
adj_dp_ref_clk_khz =
dc_fixpt_mul_int(
ss_percentage,
dp_ref_clk_khz);
dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz);
}
return dp_ref_clk_khz;
return dccg_adjust_dp_ref_freq_for_ss(clk_dce, 600000);
}
static enum dm_pp_clocks_state dce_get_required_clocks_state(
struct display_clock *clk,
struct state_dependent_clocks *req_clocks)
struct dccg *clk,
struct dc_clocks *req_clocks)
{
struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
int i;
enum dm_pp_clocks_state low_req_clk;
@ -286,53 +212,30 @@ static enum dm_pp_clocks_state dce_get_required_clocks_state(
* all required clocks
*/
for (i = clk->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--)
if (req_clocks->display_clk_khz >
if (req_clocks->dispclk_khz >
clk_dce->max_clks_by_state[i].display_clk_khz
|| req_clocks->pixel_clk_khz >
|| req_clocks->phyclk_khz >
clk_dce->max_clks_by_state[i].pixel_clk_khz)
break;
low_req_clk = i + 1;
if (low_req_clk > clk->max_clks_state) {
DC_LOG_WARNING("%s: clocks unsupported disp_clk %d pix_clk %d",
__func__,
req_clocks->display_clk_khz,
req_clocks->pixel_clk_khz);
low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
/* set max clock state for high phyclock, invalid on exceeding display clock */
if (clk_dce->max_clks_by_state[clk->max_clks_state].display_clk_khz
< req_clocks->dispclk_khz)
low_req_clk = DM_PP_CLOCKS_STATE_INVALID;
else
low_req_clk = clk->max_clks_state;
}
return low_req_clk;
}
static bool dce_clock_set_min_clocks_state(
struct display_clock *clk,
enum dm_pp_clocks_state clocks_state)
{
struct dm_pp_power_level_change_request level_change_req = {
clocks_state };
if (clocks_state > clk->max_clks_state) {
/*Requested state exceeds max supported state.*/
DC_LOG_WARNING("Requested state exceeds max supported state");
return false;
} else if (clocks_state == clk->cur_min_clks_state) {
/*if we're trying to set the same state, we can just return
* since nothing needs to be done*/
return true;
}
/* get max clock state from PPLIB */
if (dm_pp_apply_power_level_change_request(clk->ctx, &level_change_req))
clk->cur_min_clks_state = clocks_state;
return true;
}
static int dce_set_clock(
struct display_clock *clk,
struct dccg *clk,
int requested_clk_khz)
{
struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
struct bp_pixel_clock_parameters pxl_clk_params = { 0 };
struct dc_bios *bp = clk->ctx->dc_bios;
int actual_clock = requested_clk_khz;
@ -364,10 +267,10 @@ static int dce_set_clock(
}
static int dce_psr_set_clock(
struct display_clock *clk,
struct dccg *clk,
int requested_clk_khz)
{
struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
struct dc_context *ctx = clk_dce->base.ctx;
struct dc *core_dc = ctx->dc;
struct dmcu *dmcu = core_dc->res_pool->dmcu;
@ -380,10 +283,10 @@ static int dce_psr_set_clock(
}
static int dce112_set_clock(
struct display_clock *clk,
struct dccg *clk,
int requested_clk_khz)
{
struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk);
struct bp_set_dce_clock_parameters dce_clk_params;
struct dc_bios *bp = clk->ctx->dc_bios;
struct dc *core_dc = clk->ctx->dc;
@ -432,7 +335,7 @@ static int dce112_set_clock(
return actual_clock;
}
static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)
static void dce_clock_read_integrated_info(struct dce_dccg *clk_dce)
{
struct dc_debug *debug = &clk_dce->base.ctx->dc->debug;
struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
@ -488,11 +391,9 @@ static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce)
if (!debug->disable_dfs_bypass && bp->integrated_info)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
clk_dce->dfs_bypass_enabled = true;
clk_dce->use_max_disp_clk = debug->max_disp_clk;
}
static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
static void dce_clock_read_ss_info(struct dce_dccg *clk_dce)
{
struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
int ss_info_num = bp->funcs->get_ss_entry_number(
@ -548,139 +449,263 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
}
}
static bool dce_apply_clock_voltage_request(
struct display_clock *clk,
enum dm_pp_clock_type clocks_type,
int clocks_in_khz,
bool pre_mode_set,
bool update_dp_phyclk)
static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk)
{
bool send_request = false;
struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
switch (clocks_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
case DM_PP_CLOCK_TYPE_PIXELCLK:
case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
break;
default:
BREAK_TO_DEBUGGER();
return false;
}
clock_voltage_req.clk_type = clocks_type;
clock_voltage_req.clocks_in_khz = clocks_in_khz;
/* to pplib */
if (pre_mode_set) {
switch (clocks_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
if (clocks_in_khz > clk->cur_clocks_value.dispclk_in_khz) {
clk->cur_clocks_value.dispclk_notify_pplib_done = true;
send_request = true;
} else
clk->cur_clocks_value.dispclk_notify_pplib_done = false;
/* no matter incrase or decrase clock, update current clock value */
clk->cur_clocks_value.dispclk_in_khz = clocks_in_khz;
break;
case DM_PP_CLOCK_TYPE_PIXELCLK:
if (clocks_in_khz > clk->cur_clocks_value.max_pixelclk_in_khz) {
clk->cur_clocks_value.pixelclk_notify_pplib_done = true;
send_request = true;
} else
clk->cur_clocks_value.pixelclk_notify_pplib_done = false;
/* no matter incrase or decrase clock, update current clock value */
clk->cur_clocks_value.max_pixelclk_in_khz = clocks_in_khz;
break;
case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
if (clocks_in_khz > clk->cur_clocks_value.max_non_dp_phyclk_in_khz) {
clk->cur_clocks_value.phyclk_notigy_pplib_done = true;
send_request = true;
} else
clk->cur_clocks_value.phyclk_notigy_pplib_done = false;
/* no matter incrase or decrase clock, update current clock value */
clk->cur_clocks_value.max_non_dp_phyclk_in_khz = clocks_in_khz;
break;
default:
ASSERT(0);
break;
}
} else {
switch (clocks_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
if (!clk->cur_clocks_value.dispclk_notify_pplib_done)
send_request = true;
break;
case DM_PP_CLOCK_TYPE_PIXELCLK:
if (!clk->cur_clocks_value.pixelclk_notify_pplib_done)
send_request = true;
break;
case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
if (!clk->cur_clocks_value.phyclk_notigy_pplib_done)
send_request = true;
break;
default:
ASSERT(0);
break;
}
}
if (send_request) {
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (clk->ctx->dce_version >= DCN_VERSION_1_0) {
struct dc *core_dc = clk->ctx->dc;
/*use dcfclk request voltage*/
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
clock_voltage_req.clocks_in_khz =
dcn_find_dcfclk_suits_all(core_dc, &clk->cur_clocks_value);
}
#endif
dm_pp_apply_clock_for_voltage_request(
clk->ctx, &clock_voltage_req);
}
if (update_dp_phyclk && (clocks_in_khz >
clk->cur_clocks_value.max_dp_phyclk_in_khz))
clk->cur_clocks_value.max_dp_phyclk_in_khz = clocks_in_khz;
return true;
return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
}
static void dce12_update_clocks(struct dccg *dccg,
struct dc_clocks *new_clocks,
bool safe_to_lower)
{
struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
clock_voltage_req.clocks_in_khz = new_clocks->dispclk_khz;
dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);
dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);
}
if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, dccg->clks.phyclk_khz)) {
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;
clock_voltage_req.clocks_in_khz = new_clocks->phyclk_khz;
dccg->clks.phyclk_khz = new_clocks->phyclk_khz;
dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);
}
}
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
static int dcn1_determine_dppclk_threshold(struct dccg *dccg, struct dc_clocks *new_clocks)
{
bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
bool dispclk_increase = new_clocks->dispclk_khz > dccg->clks.dispclk_khz;
int disp_clk_threshold = new_clocks->max_supported_dppclk_khz;
bool cur_dpp_div = dccg->clks.dispclk_khz > dccg->clks.dppclk_khz;
/* increase clock, looking for div is 0 for current, request div is 1*/
if (dispclk_increase) {
/* already divided by 2, no need to reach target clk with 2 steps*/
if (cur_dpp_div)
return new_clocks->dispclk_khz;
/* request disp clk is lower than maximum supported dpp clk,
* no need to reach target clk with two steps.
*/
if (new_clocks->dispclk_khz <= disp_clk_threshold)
return new_clocks->dispclk_khz;
/* target dpp clk not request divided by 2, still within threshold */
if (!request_dpp_div)
return new_clocks->dispclk_khz;
} else {
/* decrease clock, looking for current dppclk divided by 2,
* request dppclk not divided by 2.
*/
/* current dpp clk not divided by 2, no need to ramp*/
if (!cur_dpp_div)
return new_clocks->dispclk_khz;
/* current disp clk is lower than current maximum dpp clk,
* no need to ramp
*/
if (dccg->clks.dispclk_khz <= disp_clk_threshold)
return new_clocks->dispclk_khz;
/* request dpp clk need to be divided by 2 */
if (request_dpp_div)
return new_clocks->dispclk_khz;
}
return disp_clk_threshold;
}
static void dcn1_ramp_up_dispclk_with_dpp(struct dccg *dccg, struct dc_clocks *new_clocks)
{
struct dc *dc = dccg->ctx->dc;
int dispclk_to_dpp_threshold = dcn1_determine_dppclk_threshold(dccg, new_clocks);
bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
int i;
/* set disp clk to dpp clk threshold */
dccg->funcs->set_dispclk(dccg, dispclk_to_dpp_threshold);
/* update request dpp clk division option */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
if (!pipe_ctx->plane_state)
continue;
pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(
pipe_ctx->plane_res.dpp,
request_dpp_div,
true);
}
/* If target clk not same as dppclk threshold, set to target clock */
if (dispclk_to_dpp_threshold != new_clocks->dispclk_khz)
dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);
dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
dccg->clks.dppclk_khz = new_clocks->dppclk_khz;
dccg->clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
}
static void dcn1_update_clocks(struct dccg *dccg,
struct dc_clocks *new_clocks,
bool safe_to_lower)
{
struct dc *dc = dccg->ctx->dc;
struct pp_smu_display_requirement_rv *smu_req_cur =
&dc->res_pool->pp_smu_req;
struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
bool send_request_to_increase = false;
bool send_request_to_lower = false;
if (new_clocks->phyclk_khz)
smu_req.display_count = 1;
else
smu_req.display_count = 0;
if (new_clocks->dispclk_khz > dccg->clks.dispclk_khz
|| new_clocks->phyclk_khz > dccg->clks.phyclk_khz
|| new_clocks->fclk_khz > dccg->clks.fclk_khz
|| new_clocks->dcfclk_khz > dccg->clks.dcfclk_khz)
send_request_to_increase = true;
if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, dccg->clks.phyclk_khz)) {
dccg->clks.phyclk_khz = new_clocks->phyclk_khz;
send_request_to_lower = true;
}
if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, dccg->clks.fclk_khz)) {
dccg->clks.fclk_khz = new_clocks->fclk_khz;
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_FCLK;
clock_voltage_req.clocks_in_khz = new_clocks->fclk_khz;
smu_req.hard_min_fclk_khz = new_clocks->fclk_khz;
dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);
send_request_to_lower = true;
}
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, dccg->clks.dcfclk_khz)) {
dccg->clks.dcfclk_khz = new_clocks->dcfclk_khz;
smu_req.hard_min_dcefclk_khz = new_clocks->dcfclk_khz;
send_request_to_lower = true;
}
if (should_set_clock(safe_to_lower,
new_clocks->dcfclk_deep_sleep_khz, dccg->clks.dcfclk_deep_sleep_khz)) {
dccg->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
smu_req.min_deep_sleep_dcefclk_mhz = new_clocks->dcfclk_deep_sleep_khz;
send_request_to_lower = true;
}
/* make sure dcf clk is before dpp clk to
* make sure we have enough voltage to run dpp clk
*/
if (send_request_to_increase) {
/*use dcfclk to request voltage*/
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);
if (pp_smu->set_display_requirement)
pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
}
/* dcn1 dppclk is tied to dispclk */
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {
dcn1_ramp_up_dispclk_with_dpp(dccg, new_clocks);
dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
send_request_to_lower = true;
}
if (!send_request_to_increase && send_request_to_lower) {
/*use dcfclk to request voltage*/
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks);
dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);
if (pp_smu->set_display_requirement)
pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
}
*smu_req_cur = smu_req;
}
#endif
static void dce_update_clocks(struct dccg *dccg,
struct dc_clocks *new_clocks,
bool safe_to_lower)
{
struct dm_pp_power_level_change_request level_change_req;
level_change_req.power_level = dce_get_required_clocks_state(dccg, new_clocks);
/* get max clock state from PPLIB */
if ((level_change_req.power_level < dccg->cur_min_clks_state && safe_to_lower)
|| level_change_req.power_level > dccg->cur_min_clks_state) {
if (dm_pp_apply_power_level_change_request(dccg->ctx, &level_change_req))
dccg->cur_min_clks_state = level_change_req.power_level;
}
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {
dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);
dccg->clks.dispclk_khz = new_clocks->dispclk_khz;
}
}
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
static const struct display_clock_funcs dcn1_funcs = {
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
.set_dispclk = dce112_set_clock,
.update_clocks = dcn1_update_clocks
};
#endif
static const struct display_clock_funcs dce120_funcs = {
.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq_wrkaround,
.apply_clock_voltage_request = dce_apply_clock_voltage_request,
.set_clock = dce112_set_clock
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
.set_dispclk = dce112_set_clock,
.update_clocks = dce12_update_clocks
};
static const struct display_clock_funcs dce112_funcs = {
.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
.get_required_clocks_state = dce_get_required_clocks_state,
.set_min_clocks_state = dce_clock_set_min_clocks_state,
.set_clock = dce112_set_clock
.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
.set_dispclk = dce112_set_clock,
.update_clocks = dce_update_clocks
};
static const struct display_clock_funcs dce110_funcs = {
.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
.get_required_clocks_state = dce_get_required_clocks_state,
.set_min_clocks_state = dce_clock_set_min_clocks_state,
.set_clock = dce_psr_set_clock
.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
.set_dispclk = dce_psr_set_clock,
.update_clocks = dce_update_clocks
};
static const struct display_clock_funcs dce_funcs = {
.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
.get_required_clocks_state = dce_get_required_clocks_state,
.set_min_clocks_state = dce_clock_set_min_clocks_state,
.set_clock = dce_set_clock
.get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
.set_dispclk = dce_set_clock,
.update_clocks = dce_update_clocks
};
static void dce_disp_clk_construct(
struct dce_disp_clk *clk_dce,
static void dce_dccg_construct(
struct dce_dccg *clk_dce,
struct dc_context *ctx,
const struct dce_disp_clk_registers *regs,
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask)
const struct dccg_registers *regs,
const struct dccg_shift *clk_shift,
const struct dccg_mask *clk_mask)
{
struct display_clock *base = &clk_dce->base;
struct dccg *base = &clk_dce->base;
base->ctx = ctx;
base->funcs = &dce_funcs;
@ -700,34 +725,15 @@ static void dce_disp_clk_construct(
dce_clock_read_integrated_info(clk_dce);
dce_clock_read_ss_info(clk_dce);
dce_divider_range_construct(
&clk_dce->divider_ranges[DIVIDER_RANGE_01],
DIVIDER_RANGE_01_START,
DIVIDER_RANGE_01_STEP_SIZE,
DIVIDER_RANGE_01_BASE_DIVIDER_ID,
DIVIDER_RANGE_02_BASE_DIVIDER_ID);
dce_divider_range_construct(
&clk_dce->divider_ranges[DIVIDER_RANGE_02],
DIVIDER_RANGE_02_START,
DIVIDER_RANGE_02_STEP_SIZE,
DIVIDER_RANGE_02_BASE_DIVIDER_ID,
DIVIDER_RANGE_03_BASE_DIVIDER_ID);
dce_divider_range_construct(
&clk_dce->divider_ranges[DIVIDER_RANGE_03],
DIVIDER_RANGE_03_START,
DIVIDER_RANGE_03_STEP_SIZE,
DIVIDER_RANGE_03_BASE_DIVIDER_ID,
DIVIDER_RANGE_MAX_DIVIDER_ID);
}
struct display_clock *dce_disp_clk_create(
struct dccg *dce_dccg_create(
struct dc_context *ctx,
const struct dce_disp_clk_registers *regs,
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask)
const struct dccg_registers *regs,
const struct dccg_shift *clk_shift,
const struct dccg_mask *clk_mask)
{
struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
if (clk_dce == NULL) {
BREAK_TO_DEBUGGER();
@ -738,19 +744,19 @@ struct display_clock *dce_disp_clk_create(
dce80_max_clks_by_state,
sizeof(dce80_max_clks_by_state));
dce_disp_clk_construct(
dce_dccg_construct(
clk_dce, ctx, regs, clk_shift, clk_mask);
return &clk_dce->base;
}
struct display_clock *dce110_disp_clk_create(
struct dccg *dce110_dccg_create(
struct dc_context *ctx,
const struct dce_disp_clk_registers *regs,
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask)
const struct dccg_registers *regs,
const struct dccg_shift *clk_shift,
const struct dccg_mask *clk_mask)
{
struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
if (clk_dce == NULL) {
BREAK_TO_DEBUGGER();
@ -761,7 +767,7 @@ struct display_clock *dce110_disp_clk_create(
dce110_max_clks_by_state,
sizeof(dce110_max_clks_by_state));
dce_disp_clk_construct(
dce_dccg_construct(
clk_dce, ctx, regs, clk_shift, clk_mask);
clk_dce->base.funcs = &dce110_funcs;
@ -769,13 +775,13 @@ struct display_clock *dce110_disp_clk_create(
return &clk_dce->base;
}
struct display_clock *dce112_disp_clk_create(
struct dccg *dce112_dccg_create(
struct dc_context *ctx,
const struct dce_disp_clk_registers *regs,
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask)
const struct dccg_registers *regs,
const struct dccg_shift *clk_shift,
const struct dccg_mask *clk_mask)
{
struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
if (clk_dce == NULL) {
BREAK_TO_DEBUGGER();
@ -786,7 +792,7 @@ struct display_clock *dce112_disp_clk_create(
dce112_max_clks_by_state,
sizeof(dce112_max_clks_by_state));
dce_disp_clk_construct(
dce_dccg_construct(
clk_dce, ctx, regs, clk_shift, clk_mask);
clk_dce->base.funcs = &dce112_funcs;
@ -794,10 +800,9 @@ struct display_clock *dce112_disp_clk_create(
return &clk_dce->base;
}
struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)
struct dccg *dce120_dccg_create(struct dc_context *ctx)
{
struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
struct dm_pp_clock_levels_with_voltage clk_level_info = {0};
struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
if (clk_dce == NULL) {
BREAK_TO_DEBUGGER();
@ -808,28 +813,59 @@ struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)
dce120_max_clks_by_state,
sizeof(dce120_max_clks_by_state));
dce_disp_clk_construct(
dce_dccg_construct(
clk_dce, ctx, NULL, NULL, NULL);
clk_dce->base.funcs = &dce120_funcs;
/* new in dce120 */
if (!ctx->dc->debug.disable_pplib_clock_request &&
dm_pp_get_clock_levels_by_type_with_voltage(
ctx, DM_PP_CLOCK_TYPE_DISPLAY_CLK, &clk_level_info)
&& clk_level_info.num_levels)
clk_dce->max_displ_clk_in_khz =
clk_level_info.data[clk_level_info.num_levels - 1].clocks_in_khz;
else
clk_dce->max_displ_clk_in_khz = 1133000;
return &clk_dce->base;
}
void dce_disp_clk_destroy(struct display_clock **disp_clk)
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct dccg *dcn1_dccg_create(struct dc_context *ctx)
{
struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk);
struct dc_debug *debug = &ctx->dc->debug;
struct dc_bios *bp = ctx->dc_bios;
struct dc_firmware_info fw_info = { { 0 } };
struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);
if (clk_dce == NULL) {
BREAK_TO_DEBUGGER();
return NULL;
}
clk_dce->base.ctx = ctx;
clk_dce->base.funcs = &dcn1_funcs;
clk_dce->dfs_bypass_disp_clk = 0;
clk_dce->dprefclk_ss_percentage = 0;
clk_dce->dprefclk_ss_divider = 1000;
clk_dce->ss_on_dprefclk = false;
if (bp->integrated_info)
clk_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
if (clk_dce->dentist_vco_freq_khz == 0) {
bp->funcs->get_firmware_info(bp, &fw_info);
clk_dce->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq;
if (clk_dce->dentist_vco_freq_khz == 0)
clk_dce->dentist_vco_freq_khz = 3600000;
}
if (!debug->disable_dfs_bypass && bp->integrated_info)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
clk_dce->dfs_bypass_enabled = true;
dce_clock_read_ss_info(clk_dce);
return &clk_dce->base;
}
#endif
void dce_dccg_destroy(struct dccg **dccg)
{
struct dce_dccg *clk_dce = TO_DCE_CLOCKS(*dccg);
kfree(clk_dce);
*disp_clk = NULL;
*dccg = NULL;
}

93
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
View File

@ -33,6 +33,9 @@
.DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
.DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
#define CLK_COMMON_REG_LIST_DCN_BASE() \
SR(DENTIST_DISPCLK_CNTL)
#define CLK_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@ -40,58 +43,41 @@
CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
#define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh),\
CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh)
#define CLK_REG_FIELD_LIST(type) \
type DPREFCLK_SRC_SEL; \
type DENTIST_DPREFCLK_WDIVIDER;
type DENTIST_DPREFCLK_WDIVIDER; \
type DENTIST_DISPCLK_WDIVIDER; \
type DENTIST_DPPCLK_WDIVIDER; \
type DENTIST_DISPCLK_CHG_DONE; \
type DENTIST_DPPCLK_CHG_DONE;
struct dce_disp_clk_shift {
struct dccg_shift {
CLK_REG_FIELD_LIST(uint8_t)
};
struct dce_disp_clk_mask {
struct dccg_mask {
CLK_REG_FIELD_LIST(uint32_t)
};
struct dce_disp_clk_registers {
struct dccg_registers {
uint32_t DPREFCLK_CNTL;
uint32_t DENTIST_DISPCLK_CNTL;
};
/* Array identifiers and count for the divider ranges.*/
enum dce_divider_range_count {
DIVIDER_RANGE_01 = 0,
DIVIDER_RANGE_02,
DIVIDER_RANGE_03,
DIVIDER_RANGE_MAX /* == 3*/
};
enum dce_divider_error_types {
INVALID_DID = 0,
INVALID_DIVIDER = 1
};
struct dce_divider_range {
int div_range_start;
/* The end of this range of dividers.*/
int div_range_end;
/* The distance between each divider in this range.*/
int div_range_step;
/* The divider id for the lowest divider.*/
int did_min;
/* The divider id for the highest divider.*/
int did_max;
};
struct dce_disp_clk {
struct display_clock base;
const struct dce_disp_clk_registers *regs;
const struct dce_disp_clk_shift *clk_shift;
const struct dce_disp_clk_mask *clk_mask;
struct dce_dccg {
struct dccg base;
const struct dccg_registers *regs;
const struct dccg_shift *clk_shift;
const struct dccg_mask *clk_mask;
struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
struct dce_divider_range divider_ranges[DIVIDER_RANGE_MAX];
bool use_max_disp_clk;
int dentist_vco_freq_khz;
/* Cache the status of DFS-bypass feature*/
@ -106,32 +92,33 @@ struct dce_disp_clk {
int dprefclk_ss_percentage;
/* DPREFCLK SS percentage Divider (100 or 1000) */
int dprefclk_ss_divider;
/* max disp_clk from PPLIB for max validation display clock*/
int max_displ_clk_in_khz;
};
struct display_clock *dce_disp_clk_create(
struct dccg *dce_dccg_create(
struct dc_context *ctx,
const struct dce_disp_clk_registers *regs,
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask);
const struct dccg_registers *regs,
const struct dccg_shift *clk_shift,
const struct dccg_mask *clk_mask);
struct display_clock *dce110_disp_clk_create(
struct dccg *dce110_dccg_create(
struct dc_context *ctx,
const struct dce_disp_clk_registers *regs,
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask);
const struct dccg_registers *regs,
const struct dccg_shift *clk_shift,
const struct dccg_mask *clk_mask);
struct display_clock *dce112_disp_clk_create(
struct dccg *dce112_dccg_create(
struct dc_context *ctx,
const struct dce_disp_clk_registers *regs,
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask);
const struct dccg_registers *regs,
const struct dccg_shift *clk_shift,
const struct dccg_mask *clk_mask);
struct display_clock *dce120_disp_clk_create(struct dc_context *ctx);
struct dccg *dce120_dccg_create(struct dc_context *ctx);
void dce_disp_clk_destroy(struct display_clock **disp_clk);
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct dccg *dcn1_dccg_create(struct dc_context *ctx);
#endif
void dce_dccg_destroy(struct dccg **dccg);
#endif /* _DCE_CLOCKS_H_ */

3
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
View File

@ -249,7 +249,6 @@ struct dce_hwseq_registers {
uint32_t DISPCLK_FREQ_CHANGE_CNTL;
uint32_t RBBMIF_TIMEOUT_DIS;
uint32_t RBBMIF_TIMEOUT_DIS_2;
uint32_t DENTIST_DISPCLK_CNTL;
uint32_t DCHUBBUB_CRC_CTRL;
uint32_t DPP_TOP0_DPP_CRC_CTRL;
uint32_t DPP_TOP0_DPP_CRC_VAL_R_G;
@ -496,8 +495,6 @@ struct dce_hwseq_registers {
type DOMAIN7_PGFSM_PWR_STATUS; \
type DCFCLK_GATE_DIS; \
type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
type DENTIST_DPPCLK_WDIVIDER; \
type DENTIST_DISPCLK_WDIVIDER; \
type VGA_TEST_ENABLE; \
type VGA_TEST_RENDER_START; \
type D1VGA_MODE_ENABLE; \

49
drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
View File

@ -125,17 +125,54 @@ static void dce100_pplib_apply_display_requirements(
dc->prev_display_config = *pp_display_cfg;
}
/* unit: in_khz before mode set, get pixel clock from context. ASIC register
* may not be programmed yet
*/
static uint32_t get_max_pixel_clock_for_all_paths(
struct dc *dc,
struct dc_state *context)
{
uint32_t max_pix_clk = 0;
int i;
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream == NULL)
continue;
/* do not check under lay */
if (pipe_ctx->top_pipe)
continue;
if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk > max_pix_clk)
max_pix_clk =
pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
}
if (max_pix_clk == 0)
ASSERT(0);
return max_pix_clk;
}
void dce100_set_bandwidth(
struct dc *dc,
struct dc_state *context,
bool decrease_allowed)
{
if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) {
dc->res_pool->display_clock->funcs->set_clock(
dc->res_pool->display_clock,
context->bw.dce.dispclk_khz * 115 / 100);
dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
}
struct dc_clocks req_clks;
req_clks.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context);
dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
dc->res_pool->dccg->funcs->update_clocks(
dc->res_pool->dccg,
&req_clks,
decrease_allowed);
dce100_pplib_apply_display_requirements(dc, context);
}

16
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
View File

@ -135,15 +135,15 @@ static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
.reg_name = mm ## block ## id ## _ ## reg_name
static const struct dce_disp_clk_registers disp_clk_regs = {
static const struct dccg_registers disp_clk_regs = {
CLK_COMMON_REG_LIST_DCE_BASE()
};
static const struct dce_disp_clk_shift disp_clk_shift = {
static const struct dccg_shift disp_clk_shift = {
CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
};
static const struct dce_disp_clk_mask disp_clk_mask = {
static const struct dccg_mask disp_clk_mask = {
CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
@ -644,8 +644,8 @@ static void destruct(struct dce110_resource_pool *pool)
dce_aud_destroy(&pool->base.audios[i]);
}
if (pool->base.display_clock != NULL)
dce_disp_clk_destroy(&pool->base.display_clock);
if (pool->base.dccg != NULL)
dce_dccg_destroy(&pool->base.dccg);
if (pool->base.abm != NULL)
dce_abm_destroy(&pool->base.abm);
@ -817,11 +817,11 @@ static bool construct(
}
}
pool->base.display_clock = dce_disp_clk_create(ctx,
pool->base.dccg = dce_dccg_create(ctx,
&disp_clk_regs,
&disp_clk_shift,
&disp_clk_mask);
if (pool->base.display_clock == NULL) {
if (pool->base.dccg == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
goto res_create_fail;
@ -851,7 +851,7 @@ static bool construct(
* max_clock_state
*/
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
pool->base.display_clock->max_clks_state =
pool->base.dccg->max_clks_state =
static_clk_info.max_clocks_state;
{
struct irq_service_init_data init_data;

4
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
View File

@ -143,7 +143,7 @@ static void wait_for_fbc_state_changed(
struct dce110_compressor *cp110,
bool enabled)
{
uint16_t counter = 0;
uint32_t counter = 0;
uint32_t addr = mmFBC_STATUS;
uint32_t value;
@ -158,7 +158,7 @@ static void wait_for_fbc_state_changed(
counter++;
}
if (counter == 10) {
if (counter == 1000) {
DC_LOG_WARNING("%s: wait counter exceeded, changes to HW not applied",
__func__);
} else {

175
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -1475,7 +1475,7 @@ static void power_down_controllers(struct dc *dc)
{
int i;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
dc->res_pool->timing_generators[i]->funcs->disable_crtc(
dc->res_pool->timing_generators[i]);
}
@ -1515,12 +1515,13 @@ static void disable_vga_and_power_gate_all_controllers(
struct timing_generator *tg;
struct dc_context *ctx = dc->ctx;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
tg = dc->res_pool->timing_generators[i];
if (tg->funcs->disable_vga)
tg->funcs->disable_vga(tg);
}
for (i = 0; i < dc->res_pool->pipe_count; i++) {
/* Enable CLOCK gating for each pipe BEFORE controller
* powergating. */
enable_display_pipe_clock_gating(ctx,
@ -1663,7 +1664,7 @@ static void dce110_set_displaymarks(
}
}
static void set_safe_displaymarks(
void dce110_set_safe_displaymarks(
struct resource_context *res_ctx,
const struct resource_pool *pool)
{
@ -1755,23 +1756,15 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
}
/* unit: in_khz before mode set, get pixel clock from context. ASIC register
* may not be programmed yet.
* TODO: after mode set, pre_mode_set = false,
* may read PLL register to get pixel clock
* may not be programmed yet
*/
static uint32_t get_max_pixel_clock_for_all_paths(
struct dc *dc,
struct dc_state *context,
bool pre_mode_set)
struct dc_state *context)
{
uint32_t max_pix_clk = 0;
int i;
if (!pre_mode_set) {
/* TODO: read ASIC register to get pixel clock */
ASSERT(0);
}
for (i = 0; i < MAX_PIPES; i++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
@ -1787,94 +1780,9 @@ static uint32_t get_max_pixel_clock_for_all_paths(
pipe_ctx->stream_res.pix_clk_params.requested_pix_clk;
}
if (max_pix_clk == 0)
ASSERT(0);
return max_pix_clk;
}
/*
* Find clock state based on clock requested. if clock value is 0, simply
* set clock state as requested without finding clock state by clock value
*/
static void apply_min_clocks(
struct dc *dc,
struct dc_state *context,
enum dm_pp_clocks_state *clocks_state,
bool pre_mode_set)
{
struct state_dependent_clocks req_clocks = {0};
if (!pre_mode_set) {
/* set clock_state without verification */
if (context->dis_clk->funcs->set_min_clocks_state) {
context->dis_clk->funcs->set_min_clocks_state(
context->dis_clk, *clocks_state);
return;
}
/* TODO: This is incorrect. Figure out how to fix. */
context->dis_clk->funcs->apply_clock_voltage_request(
context->dis_clk,
DM_PP_CLOCK_TYPE_DISPLAY_CLK,
context->dis_clk->cur_clocks_value.dispclk_in_khz,
pre_mode_set,
false);
context->dis_clk->funcs->apply_clock_voltage_request(
context->dis_clk,
DM_PP_CLOCK_TYPE_PIXELCLK,
context->dis_clk->cur_clocks_value.max_pixelclk_in_khz,
pre_mode_set,
false);
context->dis_clk->funcs->apply_clock_voltage_request(
context->dis_clk,
DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
context->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz,
pre_mode_set,
false);
return;
}
/* get the required state based on state dependent clocks:
* display clock and pixel clock
*/
req_clocks.display_clk_khz = context->bw.dce.dispclk_khz;
req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths(
dc, context, true);
if (context->dis_clk->funcs->get_required_clocks_state) {
*clocks_state = context->dis_clk->funcs->get_required_clocks_state(
context->dis_clk, &req_clocks);
context->dis_clk->funcs->set_min_clocks_state(
context->dis_clk, *clocks_state);
} else {
context->dis_clk->funcs->apply_clock_voltage_request(
context->dis_clk,
DM_PP_CLOCK_TYPE_DISPLAY_CLK,
req_clocks.display_clk_khz,
pre_mode_set,
false);
context->dis_clk->funcs->apply_clock_voltage_request(
context->dis_clk,
DM_PP_CLOCK_TYPE_PIXELCLK,
req_clocks.pixel_clk_khz,
pre_mode_set,
false);
context->dis_clk->funcs->apply_clock_voltage_request(
context->dis_clk,
DM_PP_CLOCK_TYPE_DISPLAYPHYCLK,
req_clocks.pixel_clk_khz,
pre_mode_set,
false);
}
}
/*
* Check if FBC can be enabled
*/
@ -2093,7 +2001,6 @@ enum dc_status dce110_apply_ctx_to_hw(
struct dc_bios *dcb = dc->ctx->dc_bios;
enum dc_status status;
int i;
enum dm_pp_clocks_state clocks_state = DM_PP_CLOCKS_STATE_INVALID;
/* Reset old context */
/* look up the targets that have been removed since last commit */
@ -2127,55 +2034,9 @@ enum dc_status dce110_apply_ctx_to_hw(
PIPE_GATING_CONTROL_DISABLE);
}
set_safe_displaymarks(&context->res_ctx, dc->res_pool);
if (dc->fbc_compressor)
dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
/*TODO: when pplib works*/
apply_min_clocks(dc, context, &clocks_state, true);
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
if (context->bw.dcn.calc_clk.fclk_khz
> dc->current_state->bw.dcn.cur_clk.fclk_khz) {
struct dm_pp_clock_for_voltage_req clock;
clock.clk_type = DM_PP_CLOCK_TYPE_FCLK;
clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz;
dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz;
}
if (context->bw.dcn.calc_clk.dcfclk_khz
> dc->current_state->bw.dcn.cur_clk.dcfclk_khz) {
struct dm_pp_clock_for_voltage_req clock;
clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz;
dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock);
dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz;
}
if (context->bw.dcn.calc_clk.dispclk_khz
> dc->current_state->bw.dcn.cur_clk.dispclk_khz) {
dc->res_pool->display_clock->funcs->set_clock(
dc->res_pool->display_clock,
context->bw.dcn.calc_clk.dispclk_khz);
dc->current_state->bw.dcn.cur_clk.dispclk_khz =
context->bw.dcn.calc_clk.dispclk_khz;
context->bw.dcn.cur_clk.dispclk_khz =
context->bw.dcn.calc_clk.dispclk_khz;
}
} else
#endif
if (context->bw.dce.dispclk_khz
> dc->current_state->bw.dce.dispclk_khz) {
dc->res_pool->display_clock->funcs->set_clock(
dc->res_pool->display_clock,
context->bw.dce.dispclk_khz * 115 / 100);
}
dce110_setup_audio_dto(dc, context);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
@ -2204,9 +2065,6 @@ enum dc_status dce110_apply_ctx_to_hw(
return status;
}
/* to save power */
apply_min_clocks(dc, context, &clocks_state, false);
dcb->funcs->set_scratch_critical_state(dcb, false);
if (dc->fbc_compressor)
@ -2694,15 +2552,20 @@ static void dce110_set_bandwidth(
struct dc_state *context,
bool decrease_allowed)
{
dce110_set_displaymarks(dc, context);
struct dc_clocks req_clks;
if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) {
dc->res_pool->display_clock->funcs->set_clock(
dc->res_pool->display_clock,
context->bw.dce.dispclk_khz * 115 / 100);
dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz;
}
req_clks.dispclk_khz = context->bw.dce.dispclk_khz * 115 / 100;
req_clks.phyclk_khz = get_max_pixel_clock_for_all_paths(dc, context);
if (decrease_allowed)
dce110_set_displaymarks(dc, context);
else
dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
dc->res_pool->dccg->funcs->update_clocks(
dc->res_pool->dccg,
&req_clks,
decrease_allowed);
pplib_apply_display_requirements(dc, context);
}

4
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
View File

@ -60,6 +60,10 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);
void dce110_power_down(struct dc *dc);
void dce110_set_safe_displaymarks(
struct resource_context *res_ctx,
const struct resource_pool *pool);
void dce110_fill_display_configs(
const struct dc_state *context,
struct dm_pp_display_configuration *pp_display_cfg);

16
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
View File

@ -146,15 +146,15 @@ static const struct dce110_timing_generator_offsets dce110_tg_offsets[] = {
#define SRI(reg_name, block, id)\
.reg_name = mm ## block ## id ## _ ## reg_name
static const struct dce_disp_clk_registers disp_clk_regs = {
static const struct dccg_registers disp_clk_regs = {
CLK_COMMON_REG_LIST_DCE_BASE()
};
static const struct dce_disp_clk_shift disp_clk_shift = {
static const struct dccg_shift disp_clk_shift = {
CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
};
static const struct dce_disp_clk_mask disp_clk_mask = {
static const struct dccg_mask disp_clk_mask = {
CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
@ -679,8 +679,8 @@ static void destruct(struct dce110_resource_pool *pool)
if (pool->base.dmcu != NULL)
dce_dmcu_destroy(&pool->base.dmcu);
if (pool->base.display_clock != NULL)
dce_disp_clk_destroy(&pool->base.display_clock);
if (pool->base.dccg != NULL)
dce_dccg_destroy(&pool->base.dccg);
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
@ -1179,11 +1179,11 @@ static bool construct(
}
}
pool->base.display_clock = dce110_disp_clk_create(ctx,
pool->base.dccg = dce110_dccg_create(ctx,
&disp_clk_regs,
&disp_clk_shift,
&disp_clk_mask);
if (pool->base.display_clock == NULL) {
if (pool->base.dccg == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
goto res_create_fail;
@ -1213,7 +1213,7 @@ static bool construct(
* max_clock_state
*/
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
pool->base.display_clock->max_clks_state =
pool->base.dccg->max_clks_state =
static_clk_info.max_clocks_state;
{

24
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View File

@ -146,15 +146,15 @@ static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
.reg_name = mm ## block ## id ## _ ## reg_name
static const struct dce_disp_clk_registers disp_clk_regs = {
static const struct dccg_registers disp_clk_regs = {
CLK_COMMON_REG_LIST_DCE_BASE()
};
static const struct dce_disp_clk_shift disp_clk_shift = {
static const struct dccg_shift disp_clk_shift = {
CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
};
static const struct dce_disp_clk_mask disp_clk_mask = {
static const struct dccg_mask disp_clk_mask = {
CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
@ -668,8 +668,8 @@ static void destruct(struct dce110_resource_pool *pool)
if (pool->base.dmcu != NULL)
dce_dmcu_destroy(&pool->base.dmcu);
if (pool->base.display_clock != NULL)
dce_disp_clk_destroy(&pool->base.display_clock);
if (pool->base.dccg != NULL)
dce_dccg_destroy(&pool->base.dccg);
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
@ -1000,7 +1000,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
eng_clks.data[0].clocks_in_khz;
clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz =
clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
mem_clks.data[0].clocks_in_khz;
clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
@ -1010,7 +1010,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz =
clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
mem_clks.data[0].clocks_in_khz;
clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
@ -1020,7 +1020,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
eng_clks.data[0].clocks_in_khz;
clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz =
clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
@ -1030,7 +1030,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz =
clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
@ -1124,11 +1124,11 @@ static bool construct(
}
}
pool->base.display_clock = dce112_disp_clk_create(ctx,
pool->base.dccg = dce112_dccg_create(ctx,
&disp_clk_regs,
&disp_clk_shift,
&disp_clk_mask);
if (pool->base.display_clock == NULL) {
if (pool->base.dccg == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
goto res_create_fail;
@ -1158,7 +1158,7 @@ static bool construct(
* max_clock_state
*/
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
pool->base.display_clock->max_clks_state =
pool->base.dccg->max_clks_state =
static_clk_info.max_clocks_state;
{

20
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
View File

@ -494,8 +494,8 @@ static void destruct(struct dce110_resource_pool *pool)
if (pool->base.dmcu != NULL)
dce_dmcu_destroy(&pool->base.dmcu);
if (pool->base.display_clock != NULL)
dce_disp_clk_destroy(&pool->base.display_clock);
if (pool->base.dccg != NULL)
dce_dccg_destroy(&pool->base.dccg);
}
static void read_dce_straps(
@ -775,7 +775,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
eng_clks.data[0].clocks_in_khz;
clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
clk_ranges.wm_clk_ranges[0].wm_min_memg_clk_in_khz =
clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
mem_clks.data[0].clocks_in_khz;
clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
@ -785,7 +785,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
clk_ranges.wm_clk_ranges[1].wm_min_memg_clk_in_khz =
clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
mem_clks.data[0].clocks_in_khz;
clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
@ -795,7 +795,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
eng_clks.data[0].clocks_in_khz;
clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
clk_ranges.wm_clk_ranges[2].wm_min_memg_clk_in_khz =
clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
@ -805,7 +805,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
/* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
clk_ranges.wm_clk_ranges[3].wm_min_memg_clk_in_khz =
clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
/* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
@ -894,11 +894,11 @@ static bool construct(
}
}
pool->base.display_clock = dce120_disp_clk_create(ctx);
if (pool->base.display_clock == NULL) {
pool->base.dccg = dce120_dccg_create(ctx);
if (pool->base.dccg == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
goto disp_clk_create_fail;
goto dccg_create_fail;
}
pool->base.dmcu = dce_dmcu_create(ctx,
@ -1011,7 +1011,7 @@ static bool construct(
irqs_create_fail:
controller_create_fail:
disp_clk_create_fail:
dccg_create_fail:
clk_src_create_fail:
res_create_fail:

28
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
View File

@ -153,15 +153,15 @@ static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
.reg_name = mm ## block ## id ## _ ## reg_name
static const struct dce_disp_clk_registers disp_clk_regs = {
static const struct dccg_registers disp_clk_regs = {
CLK_COMMON_REG_LIST_DCE_BASE()
};
static const struct dce_disp_clk_shift disp_clk_shift = {
static const struct dccg_shift disp_clk_shift = {
CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
};
static const struct dce_disp_clk_mask disp_clk_mask = {
static const struct dccg_mask disp_clk_mask = {
CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
};
@ -683,8 +683,8 @@ static void destruct(struct dce110_resource_pool *pool)
}
}
if (pool->base.display_clock != NULL)
dce_disp_clk_destroy(&pool->base.display_clock);
if (pool->base.dccg != NULL)
dce_dccg_destroy(&pool->base.dccg);
if (pool->base.irqs != NULL) {
dal_irq_service_destroy(&pool->base.irqs);
@ -822,11 +822,11 @@ static bool dce80_construct(
}
}
pool->base.display_clock = dce_disp_clk_create(ctx,
pool->base.dccg = dce_dccg_create(ctx,
&disp_clk_regs,
&disp_clk_shift,
&disp_clk_mask);
if (pool->base.display_clock == NULL) {
if (pool->base.dccg == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
goto res_create_fail;
@ -852,7 +852,7 @@ static bool dce80_construct(
goto res_create_fail;
}
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
pool->base.display_clock->max_clks_state =
pool->base.dccg->max_clks_state =
static_clk_info.max_clocks_state;
{
@ -1006,11 +1006,11 @@ static bool dce81_construct(
}
}
pool->base.display_clock = dce_disp_clk_create(ctx,
pool->base.dccg = dce_dccg_create(ctx,
&disp_clk_regs,
&disp_clk_shift,
&disp_clk_mask);
if (pool->base.display_clock == NULL) {
if (pool->base.dccg == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
goto res_create_fail;
@ -1037,7 +1037,7 @@ static bool dce81_construct(
}
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
pool->base.display_clock->max_clks_state =
pool->base.dccg->max_clks_state =
static_clk_info.max_clocks_state;
{
@ -1187,11 +1187,11 @@ static bool dce83_construct(
}
}
pool->base.display_clock = dce_disp_clk_create(ctx,
pool->base.dccg = dce_dccg_create(ctx,
&disp_clk_regs,
&disp_clk_shift,
&disp_clk_mask);
if (pool->base.display_clock == NULL) {
if (pool->base.dccg == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
goto res_create_fail;
@ -1218,7 +1218,7 @@ static bool dce83_construct(
}
if (dm_pp_get_static_clocks(ctx, &static_clk_info))
pool->base.display_clock->max_clks_state =
pool->base.dccg->max_clks_state =
static_clk_info.max_clocks_state;
{

6
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
View File

@ -145,10 +145,10 @@ static bool dpp_get_optimal_number_of_taps(
pixel_width = scl_data->viewport.width;
/* Some ASICs does not support FP16 scaling, so we reject modes require this*/
if (scl_data->viewport.width != scl_data->h_active &&
scl_data->viewport.height != scl_data->v_active &&
if (scl_data->format == PIXEL_FORMAT_FP16 &&
dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
scl_data->format == PIXEL_FORMAT_FP16)
scl_data->ratios.horz.value != dc_fixpt_one.value &&
scl_data->ratios.vert.value != dc_fixpt_one.value)
return false;
if (scl_data->viewport.width > scl_data->h_active &&

378
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
View File

@ -190,10 +190,17 @@ static uint32_t convert_and_clamp(
}
void hubbub1_wm_change_req_wa(struct hubbub *hubbub)
{
REG_UPDATE_SEQ(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0, 1);
}
void hubbub1_program_watermarks(
struct hubbub *hubbub,
struct dcn_watermark_set *watermarks,
unsigned int refclk_mhz)
unsigned int refclk_mhz,
bool safe_to_lower)
{
uint32_t force_en = hubbub->ctx->dc->debug.disable_stutter ? 1 : 0;
/*
@ -202,191 +209,259 @@ void hubbub1_program_watermarks(
*/
uint32_t prog_wm_value;
REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0);
/* Repeat for water mark set A, B, C and D. */
/* clock state A */
prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
if (safe_to_lower || watermarks->a.urgent_ns > hubbub->watermarks.a.urgent_ns) {
hubbub->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->a.urgent_ns, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->a.urgent_ns, prog_wm_value);
}
prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->a.pte_meta_urgent_ns, prog_wm_value);
if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub->watermarks.a.pte_meta_urgent_ns) {
hubbub->watermarks.a.pte_meta_urgent_ns = watermarks->a.pte_meta_urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->a.pte_meta_urgent_ns, prog_wm_value);
}
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
prog_wm_value = convert_and_clamp(
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
> hubbub->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {
hubbub->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
}
prog_wm_value = convert_and_clamp(
watermarks->a.cstate_pstate.cstate_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns
> hubbub->watermarks.a.cstate_pstate.cstate_exit_ns) {
hubbub->watermarks.a.cstate_pstate.cstate_exit_ns =
watermarks->a.cstate_pstate.cstate_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->a.cstate_pstate.cstate_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
}
}
prog_wm_value = convert_and_clamp(
watermarks->a.cstate_pstate.pstate_change_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n\n",
watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns
> hubbub->watermarks.a.cstate_pstate.pstate_change_ns) {
hubbub->watermarks.a.cstate_pstate.pstate_change_ns =
watermarks->a.cstate_pstate.pstate_change_ns;
prog_wm_value = convert_and_clamp(
watermarks->a.cstate_pstate.pstate_change_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
"HW register value = 0x%x\n\n",
watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
}
/* clock state B */
prog_wm_value = convert_and_clamp(
watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->b.urgent_ns, prog_wm_value);
if (safe_to_lower || watermarks->b.urgent_ns > hubbub->watermarks.b.urgent_ns) {
hubbub->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->b.urgent_ns, prog_wm_value);
}
prog_wm_value = convert_and_clamp(
watermarks->b.pte_meta_urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->b.pte_meta_urgent_ns, prog_wm_value);
if (safe_to_lower || watermarks->b.pte_meta_urgent_ns > hubbub->watermarks.b.pte_meta_urgent_ns) {
hubbub->watermarks.b.pte_meta_urgent_ns = watermarks->b.pte_meta_urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->b.pte_meta_urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->b.pte_meta_urgent_ns, prog_wm_value);
}
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
prog_wm_value = convert_and_clamp(
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
> hubbub->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {
hubbub->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
}
prog_wm_value = convert_and_clamp(
watermarks->b.cstate_pstate.cstate_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns
> hubbub->watermarks.b.cstate_pstate.cstate_exit_ns) {
hubbub->watermarks.b.cstate_pstate.cstate_exit_ns =
watermarks->b.cstate_pstate.cstate_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->b.cstate_pstate.cstate_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
}
}
prog_wm_value = convert_and_clamp(
watermarks->b.cstate_pstate.pstate_change_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
"HW register value = 0x%x\n",
watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns
> hubbub->watermarks.b.cstate_pstate.pstate_change_ns) {
hubbub->watermarks.b.cstate_pstate.pstate_change_ns =
watermarks->b.cstate_pstate.pstate_change_ns;
prog_wm_value = convert_and_clamp(
watermarks->b.cstate_pstate.pstate_change_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n"
"HW register value = 0x%x\n\n",
watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
}
/* clock state C */
prog_wm_value = convert_and_clamp(
watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->c.urgent_ns, prog_wm_value);
if (safe_to_lower || watermarks->c.urgent_ns > hubbub->watermarks.c.urgent_ns) {
hubbub->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->c.urgent_ns, prog_wm_value);
}
prog_wm_value = convert_and_clamp(
watermarks->c.pte_meta_urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->c.pte_meta_urgent_ns, prog_wm_value);
if (safe_to_lower || watermarks->c.pte_meta_urgent_ns > hubbub->watermarks.c.pte_meta_urgent_ns) {
hubbub->watermarks.c.pte_meta_urgent_ns = watermarks->c.pte_meta_urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->c.pte_meta_urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->c.pte_meta_urgent_ns, prog_wm_value);
}
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
prog_wm_value = convert_and_clamp(
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
> hubbub->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {
hubbub->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
}
prog_wm_value = convert_and_clamp(
watermarks->c.cstate_pstate.cstate_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns
> hubbub->watermarks.c.cstate_pstate.cstate_exit_ns) {
hubbub->watermarks.c.cstate_pstate.cstate_exit_ns =
watermarks->c.cstate_pstate.cstate_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->c.cstate_pstate.cstate_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
}
}
prog_wm_value = convert_and_clamp(
watermarks->c.cstate_pstate.pstate_change_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
"HW register value = 0x%x\n",
watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns
> hubbub->watermarks.c.cstate_pstate.pstate_change_ns) {
hubbub->watermarks.c.cstate_pstate.pstate_change_ns =
watermarks->c.cstate_pstate.pstate_change_ns;
prog_wm_value = convert_and_clamp(
watermarks->c.cstate_pstate.pstate_change_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n"
"HW register value = 0x%x\n\n",
watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
}
/* clock state D */
prog_wm_value = convert_and_clamp(
watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->d.urgent_ns, prog_wm_value);
prog_wm_value = convert_and_clamp(
watermarks->d.pte_meta_urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->d.pte_meta_urgent_ns, prog_wm_value);
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
prog_wm_value = convert_and_clamp(
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
if (safe_to_lower || watermarks->d.urgent_ns > hubbub->watermarks.d.urgent_ns) {
hubbub->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
prog_wm_value = convert_and_clamp(
watermarks->d.cstate_pstate.cstate_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"
DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
watermarks->d.urgent_ns, prog_wm_value);
}
if (safe_to_lower || watermarks->d.pte_meta_urgent_ns > hubbub->watermarks.d.pte_meta_urgent_ns) {
hubbub->watermarks.d.pte_meta_urgent_ns = watermarks->d.pte_meta_urgent_ns;
prog_wm_value = convert_and_clamp(watermarks->d.pte_meta_urgent_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->d.pte_meta_urgent_ns, prog_wm_value);
}
prog_wm_value = convert_and_clamp(
watermarks->d.cstate_pstate.pstate_change_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n\n",
watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
> hubbub->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {
hubbub->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
}
REG_UPDATE(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns
> hubbub->watermarks.d.cstate_pstate.cstate_exit_ns) {
hubbub->watermarks.d.cstate_pstate.cstate_exit_ns =
watermarks->d.cstate_pstate.cstate_exit_ns;
prog_wm_value = convert_and_clamp(
watermarks->d.cstate_pstate.cstate_exit_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n",
watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
}
}
if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns
> hubbub->watermarks.d.cstate_pstate.pstate_change_ns) {
hubbub->watermarks.d.cstate_pstate.pstate_change_ns =
watermarks->d.cstate_pstate.pstate_change_ns;
prog_wm_value = convert_and_clamp(
watermarks->d.cstate_pstate.pstate_change_ns,
refclk_mhz, 0x1fffff);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
"HW register value = 0x%x\n\n",
watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
}
REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
@ -408,6 +483,11 @@ void hubbub1_update_dchub(
struct hubbub *hubbub,
struct dchub_init_data *dh_data)
{
if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {
ASSERT(false);
/*should not come here*/
return;
}
/* TODO: port code from dal2 */
switch (dh_data->fb_mode) {
case FRAME_BUFFER_MODE_ZFB_ONLY:

6
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
View File

@ -185,6 +185,7 @@ struct hubbub {
const struct dcn_hubbub_shift *shifts;
const struct dcn_hubbub_mask *masks;
unsigned int debug_test_index_pstate;
struct dcn_watermark_set watermarks;
};
void hubbub1_update_dchub(
@ -194,10 +195,13 @@ void hubbub1_update_dchub(
bool hubbub1_verify_allow_pstate_change_high(
struct hubbub *hubbub);
void hubbub1_wm_change_req_wa(struct hubbub *hubbub);
void hubbub1_program_watermarks(
struct hubbub *hubbub,
struct dcn_watermark_set *watermarks,
unsigned int refclk_mhz);
unsigned int refclk_mhz,
bool safe_to_lower);
void hubbub1_toggle_watermark_change_req(
struct hubbub *hubbub);

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
View File

@ -166,7 +166,7 @@ void hubp1_program_size_and_rotation(
/* Program data and meta surface pitch (calculation from addrlib)
* 444 or 420 luma
*/
if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) {
ASSERT(plane_size->video.chroma_pitch != 0);
/* Chroma pitch zero can cause system hang! */

321
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -337,13 +337,13 @@ void dcn10_log_hw_state(struct dc *dc)
DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n"
"dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
dc->current_state->bw.dcn.calc_clk.dcfclk_khz,
dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
dc->current_state->bw.dcn.calc_clk.dispclk_khz,
dc->current_state->bw.dcn.calc_clk.dppclk_khz,
dc->current_state->bw.dcn.calc_clk.max_supported_dppclk_khz,
dc->current_state->bw.dcn.calc_clk.fclk_khz,
dc->current_state->bw.dcn.calc_clk.socclk_khz);
dc->current_state->bw.dcn.clk.dcfclk_khz,
dc->current_state->bw.dcn.clk.dcfclk_deep_sleep_khz,
dc->current_state->bw.dcn.clk.dispclk_khz,
dc->current_state->bw.dcn.clk.dppclk_khz,
dc->current_state->bw.dcn.clk.max_supported_dppclk_khz,
dc->current_state->bw.dcn.clk.fclk_khz,
dc->current_state->bw.dcn.clk.socclk_khz);
log_mpc_crc(dc);
@ -415,6 +415,8 @@ static void dpp_pg_control(
if (hws->ctx->dc->debug.disable_dpp_power_gate)
return;
if (REG(DOMAIN1_PG_CONFIG) == 0)
return;
switch (dpp_inst) {
case 0: /* DPP0 */
@ -465,6 +467,8 @@ static void hubp_pg_control(
if (hws->ctx->dc->debug.disable_hubp_power_gate)
return;
if (REG(DOMAIN0_PG_CONFIG) == 0)
return;
switch (hubp_inst) {
case 0: /* DCHUBP0 */
@ -865,7 +869,8 @@ void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
return;
mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
if (opp != NULL)
opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
dc->optimized_required = true;
@ -1010,7 +1015,7 @@ static void dcn10_init_hw(struct dc *dc)
/* Reset all MPCC muxes */
dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
struct timing_generator *tg = dc->res_pool->timing_generators[i];
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
struct hubp *hubp = dc->res_pool->hubps[i];
@ -1343,10 +1348,11 @@ static void dcn10_enable_per_frame_crtc_position_reset(
DC_SYNC_INFO("Setting up\n");
for (i = 0; i < group_size; i++)
grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
grouped_pipes[i]->stream_res.tg,
grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
&grouped_pipes[i]->stream->triggered_crtc_reset);
if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
grouped_pipes[i]->stream_res.tg,
grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
&grouped_pipes[i]->stream->triggered_crtc_reset);
DC_SYNC_INFO("Waiting for trigger\n");
@ -1952,18 +1958,17 @@ static void update_dchubp_dpp(
* divided by 2
*/
if (plane_state->update_flags.bits.full_update) {
bool should_divided_by_2 = context->bw.dcn.calc_clk.dppclk_khz <=
context->bw.dcn.cur_clk.dispclk_khz / 2;
bool should_divided_by_2 = context->bw.dcn.clk.dppclk_khz <=
dc->res_pool->dccg->clks.dispclk_khz / 2;
dpp->funcs->dpp_dppclk_control(
dpp,
should_divided_by_2,
true);
dc->current_state->bw.dcn.cur_clk.dppclk_khz =
should_divided_by_2 ?
context->bw.dcn.cur_clk.dispclk_khz / 2 :
context->bw.dcn.cur_clk.dispclk_khz;
dc->res_pool->dccg->clks.dppclk_khz = should_divided_by_2 ?
dc->res_pool->dccg->clks.dispclk_khz / 2 :
dc->res_pool->dccg->clks.dispclk_khz;
}
/* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
@ -2153,12 +2158,12 @@ static void dcn10_pplib_apply_display_requirements(
{
struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
pp_display_cfg->min_engine_clock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
pp_display_cfg->min_memory_clock_khz = context->bw.dcn.cur_clk.fclk_khz;
pp_display_cfg->min_engine_clock_deep_sleep_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
pp_display_cfg->min_dcfc_deep_sleep_clock_khz = context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz;
pp_display_cfg->min_dcfclock_khz = context->bw.dcn.cur_clk.dcfclk_khz;
pp_display_cfg->disp_clk_khz = context->bw.dcn.cur_clk.dispclk_khz;
pp_display_cfg->min_engine_clock_khz = dc->res_pool->dccg->clks.dcfclk_khz;
pp_display_cfg->min_memory_clock_khz = dc->res_pool->dccg->clks.fclk_khz;
pp_display_cfg->min_engine_clock_deep_sleep_khz = dc->res_pool->dccg->clks.dcfclk_deep_sleep_khz;
pp_display_cfg->min_dcfc_deep_sleep_clock_khz = dc->res_pool->dccg->clks.dcfclk_deep_sleep_khz;
pp_display_cfg->min_dcfclock_khz = dc->res_pool->dccg->clks.dcfclk_khz;
pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz;
dce110_fill_display_configs(context, pp_display_cfg);
if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
@ -2220,8 +2225,6 @@ static void dcn10_apply_ctx_for_surface(
int i;
struct timing_generator *tg;
bool removed_pipe[4] = { false };
unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
bool program_water_mark = false;
struct pipe_ctx *top_pipe_to_program =
find_top_pipe_for_stream(dc, context, stream);
DC_LOGGER_INIT(dc->ctx->logger);
@ -2269,8 +2272,7 @@ static void dcn10_apply_ctx_for_surface(
hwss1_plane_atomic_disconnect(dc, old_pipe_ctx);
removed_pipe[i] = true;
DC_LOG_DC(
"Reset mpcc for pipe %d\n",
DC_LOG_DC("Reset mpcc for pipe %d\n",
old_pipe_ctx->pipe_idx);
}
}
@ -2283,248 +2285,41 @@ static void dcn10_apply_ctx_for_surface(
if (num_planes == 0)
false_optc_underflow_wa(dc, stream, tg);
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *old_pipe_ctx =
&dc->current_state->res_ctx.pipe_ctx[i];
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream == stream &&
pipe_ctx->plane_state &&
pipe_ctx->plane_state->update_flags.bits.full_update)
program_water_mark = true;
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (removed_pipe[i])
dcn10_disable_plane(dc, old_pipe_ctx);
}
dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
if (program_water_mark) {
if (dc->debug.sanity_checks) {
/* pstate stuck check after watermark update */
dcn10_verify_allow_pstate_change_high(dc);
}
/* watermark is for all pipes */
hubbub1_program_watermarks(dc->res_pool->hubbub,
&context->bw.dcn.watermarks, ref_clk_mhz);
if (dc->debug.sanity_checks) {
/* pstate stuck check after watermark update */
dcn10_verify_allow_pstate_change_high(dc);
}
}
/* DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
"\n============== Watermark parameters ==============\n"
"a.urgent_ns: %d \n"
"a.cstate_enter_plus_exit: %d \n"
"a.cstate_exit: %d \n"
"a.pstate_change: %d \n"
"a.pte_meta_urgent: %d \n"
"b.urgent_ns: %d \n"
"b.cstate_enter_plus_exit: %d \n"
"b.cstate_exit: %d \n"
"b.pstate_change: %d \n"
"b.pte_meta_urgent: %d \n",
context->bw.dcn.watermarks.a.urgent_ns,
context->bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns,
context->bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns,
context->bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns,
context->bw.dcn.watermarks.a.pte_meta_urgent_ns,
context->bw.dcn.watermarks.b.urgent_ns,
context->bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns,
context->bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns,
context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
context->bw.dcn.watermarks.b.pte_meta_urgent_ns
);
DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
"\nc.urgent_ns: %d \n"
"c.cstate_enter_plus_exit: %d \n"
"c.cstate_exit: %d \n"
"c.pstate_change: %d \n"
"c.pte_meta_urgent: %d \n"
"d.urgent_ns: %d \n"
"d.cstate_enter_plus_exit: %d \n"
"d.cstate_exit: %d \n"
"d.pstate_change: %d \n"
"d.pte_meta_urgent: %d \n"
"========================================================\n",
context->bw.dcn.watermarks.c.urgent_ns,
context->bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns,
context->bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns,
context->bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns,
context->bw.dcn.watermarks.c.pte_meta_urgent_ns,
context->bw.dcn.watermarks.d.urgent_ns,
context->bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns,
context->bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns,
context->bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns,
context->bw.dcn.watermarks.d.pte_meta_urgent_ns
);
*/
}
static inline bool should_set_clock(bool decrease_allowed, int calc_clk, int cur_clk)
{
return ((decrease_allowed && calc_clk < cur_clk) || calc_clk > cur_clk);
}
static int determine_dppclk_threshold(struct dc *dc, struct dc_state *context)
{
bool request_dpp_div = context->bw.dcn.calc_clk.dispclk_khz >
context->bw.dcn.calc_clk.dppclk_khz;
bool dispclk_increase = context->bw.dcn.calc_clk.dispclk_khz >
context->bw.dcn.cur_clk.dispclk_khz;
int disp_clk_threshold = context->bw.dcn.calc_clk.max_supported_dppclk_khz;
bool cur_dpp_div = context->bw.dcn.cur_clk.dispclk_khz >
context->bw.dcn.cur_clk.dppclk_khz;
/* increase clock, looking for div is 0 for current, request div is 1*/
if (dispclk_increase) {
/* already divided by 2, no need to reach target clk with 2 steps*/
if (cur_dpp_div)
return context->bw.dcn.calc_clk.dispclk_khz;
/* request disp clk is lower than maximum supported dpp clk,
* no need to reach target clk with two steps.
*/
if (context->bw.dcn.calc_clk.dispclk_khz <= disp_clk_threshold)
return context->bw.dcn.calc_clk.dispclk_khz;
/* target dpp clk not request divided by 2, still within threshold */
if (!request_dpp_div)
return context->bw.dcn.calc_clk.dispclk_khz;
} else {
/* decrease clock, looking for current dppclk divided by 2,
* request dppclk not divided by 2.
*/
/* current dpp clk not divided by 2, no need to ramp*/
if (!cur_dpp_div)
return context->bw.dcn.calc_clk.dispclk_khz;
/* current disp clk is lower than current maximum dpp clk,
* no need to ramp
*/
if (context->bw.dcn.cur_clk.dispclk_khz <= disp_clk_threshold)
return context->bw.dcn.calc_clk.dispclk_khz;
/* request dpp clk need to be divided by 2 */
if (request_dpp_div)
return context->bw.dcn.calc_clk.dispclk_khz;
}
return disp_clk_threshold;
}
static void ramp_up_dispclk_with_dpp(struct dc *dc, struct dc_state *context)
{
int i;
bool request_dpp_div = context->bw.dcn.calc_clk.dispclk_khz >
context->bw.dcn.calc_clk.dppclk_khz;
int dispclk_to_dpp_threshold = determine_dppclk_threshold(dc, context);
/* set disp clk to dpp clk threshold */
dc->res_pool->display_clock->funcs->set_clock(
dc->res_pool->display_clock,
dispclk_to_dpp_threshold);
/* update request dpp clk division option */
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
if (!pipe_ctx->plane_state)
continue;
pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(
pipe_ctx->plane_res.dpp,
request_dpp_div,
true);
}
/* If target clk not same as dppclk threshold, set to target clock */
if (dispclk_to_dpp_threshold != context->bw.dcn.calc_clk.dispclk_khz) {
dc->res_pool->display_clock->funcs->set_clock(
dc->res_pool->display_clock,
context->bw.dcn.calc_clk.dispclk_khz);
}
context->bw.dcn.cur_clk.dispclk_khz =
context->bw.dcn.calc_clk.dispclk_khz;
context->bw.dcn.cur_clk.dppclk_khz =
context->bw.dcn.calc_clk.dppclk_khz;
context->bw.dcn.cur_clk.max_supported_dppclk_khz =
context->bw.dcn.calc_clk.max_supported_dppclk_khz;
if (dc->hwseq->wa.DEGVIDCN10_254)
hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
}
static void dcn10_set_bandwidth(
struct dc *dc,
struct dc_state *context,
bool decrease_allowed)
bool safe_to_lower)
{
struct pp_smu_display_requirement_rv *smu_req_cur =
&dc->res_pool->pp_smu_req;
struct pp_smu_display_requirement_rv smu_req = *smu_req_cur;
struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;
if (dc->debug.sanity_checks) {
if (dc->debug.sanity_checks)
dcn10_verify_allow_pstate_change_high(dc);
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (context->stream_count == 0)
context->bw.dcn.clk.phyclk_khz = 0;
dc->res_pool->dccg->funcs->update_clocks(
dc->res_pool->dccg,
&context->bw.dcn.clk,
safe_to_lower);
dcn10_pplib_apply_display_requirements(dc, context);
}
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
return;
hubbub1_program_watermarks(dc->res_pool->hubbub,
&context->bw.dcn.watermarks,
dc->res_pool->ref_clock_inKhz / 1000,
true);
if (should_set_clock(
decrease_allowed,
context->bw.dcn.calc_clk.dcfclk_khz,
dc->current_state->bw.dcn.cur_clk.dcfclk_khz)) {
context->bw.dcn.cur_clk.dcfclk_khz =
context->bw.dcn.calc_clk.dcfclk_khz;
smu_req.hard_min_dcefclk_khz =
context->bw.dcn.calc_clk.dcfclk_khz;
}
if (should_set_clock(
decrease_allowed,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz)) {
context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz =
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz;
}
if (should_set_clock(
decrease_allowed,
context->bw.dcn.calc_clk.fclk_khz,
dc->current_state->bw.dcn.cur_clk.fclk_khz)) {
context->bw.dcn.cur_clk.fclk_khz =
context->bw.dcn.calc_clk.fclk_khz;
smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz;
}
smu_req.display_count = context->stream_count;
if (pp_smu->set_display_requirement)
pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);
*smu_req_cur = smu_req;
/* make sure dcf clk is before dpp clk to
* make sure we have enough voltage to run dpp clk
*/
if (should_set_clock(
decrease_allowed,
context->bw.dcn.calc_clk.dispclk_khz,
dc->current_state->bw.dcn.cur_clk.dispclk_khz)) {
ramp_up_dispclk_with_dpp(dc, context);
}
dcn10_pplib_apply_display_requirements(dc, context);
if (dc->debug.sanity_checks) {
if (dc->debug.sanity_checks)
dcn10_verify_allow_pstate_change_high(dc);
}
/* need to fix this function. not doing the right thing here */
}
static void set_drr(struct pipe_ctx **pipe_ctx,
@ -2707,8 +2502,14 @@ static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
{
if (hws->ctx->dc->res_pool->hubbub != NULL)
hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
if (hws->ctx->dc->res_pool->hubbub != NULL) {
struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];
if (hubp->funcs->hubp_update_dchub)
hubp->funcs->hubp_update_dchub(hubp, dh_data);
else
hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
}
}
static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
View File

@ -995,6 +995,8 @@ void dcn10_link_encoder_disable_output(
if (!dcn10_is_dig_enabled(enc)) {
/* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
/*in DP_Alt_No_Connect case, we turn off the dig already,
after excuation the PHY w/a sequence, not allow touch PHY any more*/
return;
}
/* Power-down RX and disable GPU PHY should be paired.

76
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View File

@ -65,6 +65,68 @@
#include "dce/dce_abm.h"
#include "dce/dce_dmcu.h"
const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
.rob_buffer_size_kbytes = 64,
.det_buffer_size_kbytes = 164,
.dpte_buffer_size_in_pte_reqs = 42,
.dpp_output_buffer_pixels = 2560,
.opp_output_buffer_lines = 1,
.pixel_chunk_size_kbytes = 8,
.pte_enable = 1,
.pte_chunk_size_kbytes = 2,
.meta_chunk_size_kbytes = 2,
.writeback_chunk_size_kbytes = 2,
.line_buffer_size_bits = 589824,
.max_line_buffer_lines = 12,
.IsLineBufferBppFixed = 0,
.LineBufferFixedBpp = -1,
.writeback_luma_buffer_size_kbytes = 12,
.writeback_chroma_buffer_size_kbytes = 8,
.max_num_dpp = 4,
.max_num_wb = 2,
.max_dchub_pscl_bw_pix_per_clk = 4,
.max_pscl_lb_bw_pix_per_clk = 2,
.max_lb_vscl_bw_pix_per_clk = 4,
.max_vscl_hscl_bw_pix_per_clk = 4,
.max_hscl_ratio = 4,
.max_vscl_ratio = 4,
.hscl_mults = 4,
.vscl_mults = 4,
.max_hscl_taps = 8,
.max_vscl_taps = 8,
.dispclk_ramp_margin_percent = 1,
.underscan_factor = 1.10,
.min_vblank_lines = 14,
.dppclk_delay_subtotal = 90,
.dispclk_delay_subtotal = 42,
.dcfclk_cstate_latency = 10,
.max_inter_dcn_tile_repeaters = 8,
.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,
.bug_forcing_LC_req_same_size_fixed = 0,
};
const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {
.sr_exit_time_us = 9.0,
.sr_enter_plus_exit_time_us = 11.0,
.urgent_latency_us = 4.0,
.writeback_latency_us = 12.0,
.ideal_dram_bw_after_urgent_percent = 80.0,
.max_request_size_bytes = 256,
.downspread_percent = 0.5,
.dram_page_open_time_ns = 50.0,
.dram_rw_turnaround_time_ns = 17.5,
.dram_return_buffer_per_channel_bytes = 8192,
.round_trip_ping_latency_dcfclk_cycles = 128,
.urgent_out_of_order_return_per_channel_bytes = 256,
.channel_interleave_bytes = 256,
.num_banks = 8,
.num_chans = 2,
.vmm_page_size_bytes = 4096,
.dram_clock_change_latency_us = 17.0,
.writeback_dram_clock_change_latency_us = 23.0,
.return_bus_width_bytes = 64,
};
#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
@ -437,7 +499,7 @@ static const struct dc_debug debug_defaults_drv = {
*/
.min_disp_clk_khz = 100000,
.disable_pplib_clock_request = true,
.disable_pplib_clock_request = false,
.disable_pplib_wm_range = false,
.pplib_wm_report_mode = WM_REPORT_DEFAULT,
.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
@ -681,6 +743,7 @@ static struct dce_hwseq *dcn10_hwseq_create(
hws->masks = &hwseq_mask;
hws->wa.DEGVIDCN10_253 = true;
hws->wa.false_optc_underflow = true;
hws->wa.DEGVIDCN10_254 = true;
}
return hws;
}
@ -791,8 +854,8 @@ static void destruct(struct dcn10_resource_pool *pool)
if (pool->base.dmcu != NULL)
dce_dmcu_destroy(&pool->base.dmcu);
if (pool->base.display_clock != NULL)
dce_disp_clk_destroy(&pool->base.display_clock);
if (pool->base.dccg != NULL)
dce_dccg_destroy(&pool->base.dccg);
kfree(pool->base.pp_smu);
}
@ -1005,8 +1068,7 @@ static bool construct(
ctx->dc_bios->regs = &bios_regs;
pool->base.res_cap = &res_cap;
pool->base.res_cap = &res_cap;
pool->base.funcs = &dcn10_res_pool_funcs;
/*
@ -1072,8 +1134,8 @@ static bool construct(
}
}
pool->base.display_clock = dce120_disp_clk_create(ctx);
if (pool->base.display_clock == NULL) {
pool->base.dccg = dcn1_dccg_create(ctx);
if (pool->base.dccg == NULL) {
dm_error("DC: failed to create display clock!\n");
BREAK_TO_DEBUGGER();
goto fail;

6
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
View File

@ -40,7 +40,7 @@ enum wm_set_id {
WM_B,
WM_C,
WM_D,
WM_COUNT,
WM_SET_COUNT,
};
struct pp_smu_wm_set_range {
@ -53,10 +53,10 @@ struct pp_smu_wm_set_range {
struct pp_smu_wm_range_sets {
uint32_t num_reader_wm_sets;
struct pp_smu_wm_set_range reader_wm_sets[WM_COUNT];
struct pp_smu_wm_set_range reader_wm_sets[WM_SET_COUNT];
uint32_t num_writer_wm_sets;
struct pp_smu_wm_set_range writer_wm_sets[WM_COUNT];
struct pp_smu_wm_set_range writer_wm_sets[WM_SET_COUNT];
};
struct pp_smu_display_requirement_rv {

6
drivers/gpu/drm/amd/display/dc/dm_services_types.h
View File

@ -137,7 +137,7 @@ struct dm_pp_clock_range_for_wm_set {
enum dm_pp_wm_set_id wm_set_id;
uint32_t wm_min_eng_clk_in_khz;
uint32_t wm_max_eng_clk_in_khz;
uint32_t wm_min_memg_clk_in_khz;
uint32_t wm_min_mem_clk_in_khz;
uint32_t wm_max_mem_clk_in_khz;
};
@ -150,7 +150,7 @@ struct dm_pp_clock_range_for_dmif_wm_set_soc15 {
enum dm_pp_wm_set_id wm_set_id;
uint32_t wm_min_dcfclk_clk_in_khz;
uint32_t wm_max_dcfclk_clk_in_khz;
uint32_t wm_min_memg_clk_in_khz;
uint32_t wm_min_mem_clk_in_khz;
uint32_t wm_max_mem_clk_in_khz;
};
@ -158,7 +158,7 @@ struct dm_pp_clock_range_for_mcif_wm_set_soc15 {
enum dm_pp_wm_set_id wm_set_id;
uint32_t wm_min_socclk_clk_in_khz;
uint32_t wm_max_socclk_clk_in_khz;
uint32_t wm_min_memg_clk_in_khz;
uint32_t wm_min_mem_clk_in_khz;
uint32_t wm_max_mem_clk_in_khz;
};

3
drivers/gpu/drm/amd/display/dc/dml/Makefile
View File

@ -36,11 +36,10 @@ CFLAGS_display_mode_lib.o := $(dml_ccflags)
CFLAGS_display_pipe_clocks.o := $(dml_ccflags)
CFLAGS_dml1_display_rq_dlg_calc.o := $(dml_ccflags)
CFLAGS_display_rq_dlg_helpers.o := $(dml_ccflags)
CFLAGS_soc_bounding_box.o := $(dml_ccflags)
CFLAGS_dml_common_defs.o := $(dml_ccflags)
DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
soc_bounding_box.o dml_common_defs.o
dml_common_defs.o
AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))

63
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
View File

@ -26,67 +26,8 @@
#include "display_mode_lib.h"
#include "dc_features.h"
static const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
.rob_buffer_size_kbytes = 64,
.det_buffer_size_kbytes = 164,
.dpte_buffer_size_in_pte_reqs = 42,
.dpp_output_buffer_pixels = 2560,
.opp_output_buffer_lines = 1,
.pixel_chunk_size_kbytes = 8,
.pte_enable = 1,
.pte_chunk_size_kbytes = 2,
.meta_chunk_size_kbytes = 2,
.writeback_chunk_size_kbytes = 2,
.line_buffer_size_bits = 589824,
.max_line_buffer_lines = 12,
.IsLineBufferBppFixed = 0,
.LineBufferFixedBpp = -1,
.writeback_luma_buffer_size_kbytes = 12,
.writeback_chroma_buffer_size_kbytes = 8,
.max_num_dpp = 4,
.max_num_wb = 2,
.max_dchub_pscl_bw_pix_per_clk = 4,
.max_pscl_lb_bw_pix_per_clk = 2,
.max_lb_vscl_bw_pix_per_clk = 4,
.max_vscl_hscl_bw_pix_per_clk = 4,
.max_hscl_ratio = 4,
.max_vscl_ratio = 4,
.hscl_mults = 4,
.vscl_mults = 4,
.max_hscl_taps = 8,
.max_vscl_taps = 8,
.dispclk_ramp_margin_percent = 1,
.underscan_factor = 1.10,
.min_vblank_lines = 14,
.dppclk_delay_subtotal = 90,
.dispclk_delay_subtotal = 42,
.dcfclk_cstate_latency = 10,
.max_inter_dcn_tile_repeaters = 8,
.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,
.bug_forcing_LC_req_same_size_fixed = 0,
};
static const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {
.sr_exit_time_us = 9.0,
.sr_enter_plus_exit_time_us = 11.0,
.urgent_latency_us = 4.0,
.writeback_latency_us = 12.0,
.ideal_dram_bw_after_urgent_percent = 80.0,
.max_request_size_bytes = 256,
.downspread_percent = 0.5,
.dram_page_open_time_ns = 50.0,
.dram_rw_turnaround_time_ns = 17.5,
.dram_return_buffer_per_channel_bytes = 8192,
.round_trip_ping_latency_dcfclk_cycles = 128,
.urgent_out_of_order_return_per_channel_bytes = 256,
.channel_interleave_bytes = 256,
.num_banks = 8,
.num_chans = 2,
.vmm_page_size_bytes = 4096,
.dram_clock_change_latency_us = 17.0,
.writeback_dram_clock_change_latency_us = 23.0,
.return_bus_width_bytes = 64,
};
extern const struct _vcs_dpi_ip_params_st dcn1_0_ip;
extern const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc;
static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project)
{

1
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
View File

@ -27,7 +27,6 @@
#include "dml_common_defs.h"
#include "soc_bounding_box.h"
#include "dml1_display_rq_dlg_calc.h"
enum dml_project {

3
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
View File

@ -64,10 +64,9 @@ struct _vcs_dpi_voltage_scaling_st {
double dscclk_mhz;
double dcfclk_mhz;
double socclk_mhz;
double dram_speed_mhz;
double dram_speed_mts;
double fabricclk_mhz;
double dispclk_mhz;
double dram_bw_per_chan_gbps;
double phyclk_mhz;
double dppclk_mhz;
};

79
drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c
View File

@ -1,79 +0,0 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "soc_bounding_box.h"
#include "display_mode_lib.h"
#include "dc_features.h"
#include "dml_inline_defs.h"
/*
* NOTE:
* This file is gcc-parseable HW gospel, coming straight from HW engineers.
*
* It doesn't adhere to Linux kernel style and sometimes will do things in odd
* ways. Unless there is something clearly wrong with it the code should
* remain as-is as it provides us with a guarantee from HW that it is correct.
*/
void dml_socbb_set_latencies(soc_bounding_box_st *to_box, soc_bounding_box_st *from_box)
{
to_box->dram_clock_change_latency_us = from_box->dram_clock_change_latency_us;
to_box->sr_exit_time_us = from_box->sr_exit_time_us;
to_box->sr_enter_plus_exit_time_us = from_box->sr_enter_plus_exit_time_us;
to_box->urgent_latency_us = from_box->urgent_latency_us;
to_box->writeback_latency_us = from_box->writeback_latency_us;
}
voltage_scaling_st dml_socbb_voltage_scaling(
const soc_bounding_box_st *soc,
enum voltage_state voltage)
{
const voltage_scaling_st *voltage_state;
const voltage_scaling_st * const voltage_end = soc->clock_limits + DC__VOLTAGE_STATES;
for (voltage_state = soc->clock_limits;
voltage_state < voltage_end && voltage_state->state != voltage;
voltage_state++) {
}
if (voltage_state < voltage_end)
return *voltage_state;
return soc->clock_limits[DC__VOLTAGE_STATES - 1];
}
double dml_socbb_return_bw_mhz(soc_bounding_box_st *box, enum voltage_state voltage)
{
double return_bw;
voltage_scaling_st state = dml_socbb_voltage_scaling(box, voltage);
return_bw = dml_min((double) box->return_bus_width_bytes * state.dcfclk_mhz,
state.dram_bw_per_chan_gbps * 1000.0 * (double) box->num_chans
* box->ideal_dram_bw_after_urgent_percent / 100.0);
return_bw = dml_min((double) box->return_bus_width_bytes * state.fabricclk_mhz, return_bw);
return return_bw;
}

7
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View File

@ -163,7 +163,7 @@ struct resource_pool {
unsigned int audio_count;
struct audio_support audio_support;
struct display_clock *display_clock;
struct dccg *dccg;
struct irq_service *irqs;
struct abm *abm;
@ -256,8 +256,7 @@ struct dce_bw_output {
};
struct dcn_bw_output {
struct dc_clocks cur_clk;
struct dc_clocks calc_clk;
struct dc_clocks clk;
struct dcn_watermark_set watermarks;
};
@ -282,7 +281,7 @@ struct dc_state {
struct dcn_bw_internal_vars dcn_bw_vars;
#endif
struct display_clock *dis_clk;
struct dccg *dis_clk;
struct kref refcount;
};

2
drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
View File

@ -625,7 +625,7 @@ bool dcn_validate_bandwidth(
unsigned int dcn_find_dcfclk_suits_all(
const struct dc *dc,
struct clocks_value *clocks);
struct dc_clocks *clocks);
void dcn_bw_update_from_pplib(struct dc *dc);
void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc);

43
drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h
View File

@ -27,23 +27,7 @@
#define __DISPLAY_CLOCK_H__
#include "dm_services_types.h"
struct clocks_value {
int dispclk_in_khz;
int max_pixelclk_in_khz;
int max_non_dp_phyclk_in_khz;
int max_dp_phyclk_in_khz;
bool dispclk_notify_pplib_done;
bool pixelclk_notify_pplib_done;
bool phyclk_notigy_pplib_done;
int dcfclock_in_khz;
int dppclk_in_khz;
int mclk_in_khz;
int phyclk_in_khz;
int common_vdd_level;
};
#include "dc.h"
/* Structure containing all state-dependent clocks
* (dependent on "enum clocks_state") */
@ -52,34 +36,23 @@ struct state_dependent_clocks {
int pixel_clk_khz;
};
struct display_clock {
struct dccg {
struct dc_context *ctx;
const struct display_clock_funcs *funcs;
enum dm_pp_clocks_state max_clks_state;
enum dm_pp_clocks_state cur_min_clks_state;
struct clocks_value cur_clocks_value;
struct dc_clocks clks;
};
struct display_clock_funcs {
int (*set_clock)(struct display_clock *disp_clk,
void (*update_clocks)(struct dccg *dccg,
struct dc_clocks *new_clocks,
bool safe_to_lower);
int (*set_dispclk)(struct dccg *dccg,
int requested_clock_khz);
enum dm_pp_clocks_state (*get_required_clocks_state)(
struct display_clock *disp_clk,
struct state_dependent_clocks *req_clocks);
bool (*set_min_clocks_state)(struct display_clock *disp_clk,
enum dm_pp_clocks_state dm_pp_clocks_state);
int (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
bool (*apply_clock_voltage_request)(
struct display_clock *disp_clk,
enum dm_pp_clock_type clocks_type,
int clocks_in_khz,
bool pre_mode_set,
bool update_dp_phyclk);
int (*get_dp_ref_clk_frequency)(struct dccg *dccg);
};
#endif /* __DISPLAY_CLOCK_H__ */

3
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
View File

@ -44,6 +44,7 @@ struct dce_hwseq_wa {
bool blnd_crtc_trigger;
bool DEGVIDCN10_253;
bool false_optc_underflow;
bool DEGVIDCN10_254;
};
struct hwseq_wa_state {
@ -171,7 +172,7 @@ struct hw_sequencer_funcs {
void (*set_bandwidth)(
struct dc *dc,
struct dc_state *context,
bool decrease_allowed);
bool safe_to_lower);
void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
int vmin, int vmax);

2
drivers/gpu/drm/amd/display/dc/irq/irq_service.c
View File

@ -78,7 +78,7 @@ const struct irq_source_info *find_irq_source_info(
struct irq_service *irq_service,
enum dc_irq_source source)
{
if (source > DAL_IRQ_SOURCES_NUMBER || source < DC_IRQ_SOURCE_INVALID)
if (source >= DAL_IRQ_SOURCES_NUMBER || source < DC_IRQ_SOURCE_INVALID)
return NULL;
return &irq_service->info[source];

46
drivers/gpu/drm/amd/display/include/grph_object_defs.h
View File

@ -37,6 +37,10 @@
* ********************************************************************
*/
#define MAX_CONNECTOR_NUMBER_PER_SLOT (16)
#define MAX_BOARD_SLOTS (4)
#define INVALID_CONNECTOR_INDEX ((unsigned int)(-1))
/* HPD unit id - HW direct translation */
enum hpd_source_id {
HPD_SOURCEID1 = 0,
@ -136,5 +140,47 @@ enum sync_source {
SYNC_SOURCE_DUAL_GPU_PIN
};
/* connector sizes in millimeters - from BiosParserTypes.hpp */
#define CONNECTOR_SIZE_DVI 40
#define CONNECTOR_SIZE_VGA 32
#define CONNECTOR_SIZE_HDMI 16
#define CONNECTOR_SIZE_DP 16
#define CONNECTOR_SIZE_MINI_DP 9
#define CONNECTOR_SIZE_UNKNOWN 30
enum connector_layout_type {
CONNECTOR_LAYOUT_TYPE_UNKNOWN,
CONNECTOR_LAYOUT_TYPE_DVI_D,
CONNECTOR_LAYOUT_TYPE_DVI_I,
CONNECTOR_LAYOUT_TYPE_VGA,
CONNECTOR_LAYOUT_TYPE_HDMI,
CONNECTOR_LAYOUT_TYPE_DP,
CONNECTOR_LAYOUT_TYPE_MINI_DP,
};
struct connector_layout_info {
struct graphics_object_id connector_id;
enum connector_layout_type connector_type;
unsigned int length;
unsigned int position; /* offset in mm from right side of the board */
};
/* length and width in mm */
struct slot_layout_info {
unsigned int length;
unsigned int width;
unsigned int num_of_connectors;
struct connector_layout_info connectors[MAX_CONNECTOR_NUMBER_PER_SLOT];
};
struct board_layout_info {
unsigned int num_of_slots;
/* indicates valid information in bracket layout structure. */
unsigned int is_number_of_slots_valid : 1;
unsigned int is_slots_size_valid : 1;
unsigned int is_connector_offsets_valid : 1;
unsigned int is_connector_lengths_valid : 1;
struct slot_layout_info slots[MAX_BOARD_SLOTS];
};
#endif

16
drivers/gpu/drm/amd/display/include/grph_object_id.h
View File

@ -197,6 +197,11 @@ enum transmitter_color_depth {
TRANSMITTER_COLOR_DEPTH_48 /* 16 bits */
};
enum dp_alt_mode {
DP_Alt_mode__Unknown = 0,
DP_Alt_mode__Connect,
DP_Alt_mode__NoConnect,
};
/*
*****************************************************************************
* graphics_object_id struct
@ -287,4 +292,15 @@ static inline enum engine_id dal_graphics_object_id_get_engine_id(
return (enum engine_id) id.id;
return ENGINE_ID_UNKNOWN;
}
static inline bool dal_graphics_object_id_equal(
struct graphics_object_id id_1,
struct graphics_object_id id_2)
{
if ((id_1.id == id_2.id) && (id_1.enum_id == id_2.enum_id) &&
(id_1.type == id_2.type)) {
return true;
}
return false;
}
#endif

8
drivers/gpu/drm/amd/display/modules/color/color_gamma.c
View File

@ -1723,8 +1723,8 @@ bool mod_color_calculate_curve(enum dc_transfer_func_predefined trans,
kvfree(rgb_regamma);
} else if (trans == TRANSFER_FUNCTION_HLG ||
trans == TRANSFER_FUNCTION_HLG12) {
rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
(MAX_HW_POINTS + _EXTRA_POINTS),
rgb_regamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
sizeof(*rgb_regamma),
GFP_KERNEL);
if (!rgb_regamma)
goto rgb_regamma_alloc_fail;
@ -1802,8 +1802,8 @@ bool mod_color_calculate_degamma_curve(enum dc_transfer_func_predefined trans,
kvfree(rgb_degamma);
} else if (trans == TRANSFER_FUNCTION_HLG ||
trans == TRANSFER_FUNCTION_HLG12) {
rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
(MAX_HW_POINTS + _EXTRA_POINTS),
rgb_degamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
sizeof(*rgb_degamma),
GFP_KERNEL);
if (!rgb_degamma)
goto rgb_degamma_alloc_fail;

2
drivers/gpu/drm/amd/include/amd_pcie.h
View File

@ -27,6 +27,7 @@
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000
#define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16
@ -34,6 +35,7 @@
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF
#define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0

46
drivers/gpu/drm/amd/include/amd_shared.h
View File

@ -128,47 +128,57 @@ enum PP_FEATURE_MASK {
PP_OVERDRIVE_MASK = 0x4000,
PP_GFXOFF_MASK = 0x8000,
PP_ACG_MASK = 0x10000,
PP_STUTTER_MODE = 0x20000,
};
/**
* struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
*/
struct amd_ip_funcs {
/* Name of IP block */
/** @name: Name of IP block */
char *name;
/* sets up early driver state (pre sw_init), does not configure hw - Optional */
/**
* @early_init:
*
* sets up early driver state (pre sw_init),
* does not configure hw - Optional
*/
int (*early_init)(void *handle);
/* sets up late driver/hw state (post hw_init) - Optional */
/** @late_init: sets up late driver/hw state (post hw_init) - Optional */
int (*late_init)(void *handle);
/* sets up driver state, does not configure hw */
/** @sw_init: sets up driver state, does not configure hw */
int (*sw_init)(void *handle);
/* tears down driver state, does not configure hw */
/** @sw_fini: tears down driver state, does not configure hw */
int (*sw_fini)(void *handle);
/* sets up the hw state */
/** @hw_init: sets up the hw state */
int (*hw_init)(void *handle);
/* tears down the hw state */
/** @hw_fini: tears down the hw state */
int (*hw_fini)(void *handle);
/** @late_fini: final cleanup */
void (*late_fini)(void *handle);
/* handles IP specific hw/sw changes for suspend */
/** @suspend: handles IP specific hw/sw changes for suspend */
int (*suspend)(void *handle);
/* handles IP specific hw/sw changes for resume */
/** @resume: handles IP specific hw/sw changes for resume */
int (*resume)(void *handle);
/* returns current IP block idle status */
/** @is_idle: returns current IP block idle status */
bool (*is_idle)(void *handle);
/* poll for idle */
/** @wait_for_idle: poll for idle */
int (*wait_for_idle)(void *handle);
/* check soft reset the IP block */
/** @check_soft_reset: check soft reset the IP block */
bool (*check_soft_reset)(void *handle);
/* pre soft reset the IP block */
/** @pre_soft_reset: pre soft reset the IP block */
int (*pre_soft_reset)(void *handle);
/* soft reset the IP block */
/** @soft_reset: soft reset the IP block */
int (*soft_reset)(void *handle);
/* post soft reset the IP block */
/** @post_soft_reset: post soft reset the IP block */
int (*post_soft_reset)(void *handle);
/* enable/disable cg for the IP block */
/** @set_clockgating_state: enable/disable cg for the IP block */
int (*set_clockgating_state)(void *handle,
enum amd_clockgating_state state);
/* enable/disable pg for the IP block */
/** @set_powergating_state: enable/disable pg for the IP block */
int (*set_powergating_state)(void *handle,
enum amd_powergating_state state);
/* get current clockgating status */
/** @get_clockgating_state: get current clockgating status */
void (*get_clockgating_state)(void *handle, u32 *flags);
};

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