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ASoC: rt5677: Set ADC clock to use PLL and enable ASRC

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Use the PLL to kept the correct 24M clock rate so frequency shift does
not occur when using the DSP VAD.

Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20191106011335.223061-11-cujomalainey@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Curtis Malainey 2019-11-05 17:13:35 -08:00 committed by Mark Brown
parent 55229597a9
commit ba0b3a977e
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
3 changed files with 41 additions and 0 deletions
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6
sound/soc/codecs/rt5677.c
View File

@ -5046,6 +5046,11 @@ static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
.set_tdm_slot = rt5677_set_tdm_slot,
};
static const struct snd_soc_dai_ops rt5677_dsp_dai_ops = {
.set_sysclk = rt5677_set_dai_sysclk,
.set_pll = rt5677_set_dai_pll,
};
static struct snd_soc_dai_driver rt5677_dai[] = {
{
.name = "rt5677-aif1",
@ -5152,6 +5157,7 @@ static struct snd_soc_dai_driver rt5677_dai[] = {
.rates = SNDRV_PCM_RATE_16000,
.formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &rt5677_dsp_dai_ops,
},
};

2
sound/soc/codecs/rt5677.h
View File

@ -1336,6 +1336,8 @@
#define RT5677_PLL_M_SFT 12
#define RT5677_PLL_M_BP (0x1 << 11)
#define RT5677_PLL_M_BP_SFT 11
#define RT5677_PLL_UPDATE_PLL1 (0x1 << 1)
#define RT5677_PLL_UPDATE_PLL1_SFT 1
/* Global Clock Control 1 (0x80) */
#define RT5677_SCLK_SRC_MASK (0x3 << 14)

33
sound/soc/intel/boards/bdw-rt5677.c
View File

@ -170,10 +170,37 @@ static int bdw_rt5677_hw_params(struct snd_pcm_substream *substream,
return ret;
}
static int bdw_rt5677_dsp_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
int ret;
ret = snd_soc_dai_set_sysclk(codec_dai, RT5677_SCLK_S_PLL1, 24576000,
SND_SOC_CLOCK_IN);
if (ret < 0) {
dev_err(rtd->dev, "can't set codec sysclk configuration\n");
return ret;
}
ret = snd_soc_dai_set_pll(codec_dai, 0, RT5677_PLL1_S_MCLK,
24000000, 24576000);
if (ret < 0) {
dev_err(rtd->dev, "can't set codec pll configuration\n");
return ret;
}
return 0;
}
static const struct snd_soc_ops bdw_rt5677_ops = {
.hw_params = bdw_rt5677_hw_params,
};
static const struct snd_soc_ops bdw_rt5677_dsp_ops = {
.hw_params = bdw_rt5677_dsp_hw_params,
};
#if !IS_ENABLED(CONFIG_SND_SOC_SOF_BROADWELL)
static int bdw_rt5677_rtd_init(struct snd_soc_pcm_runtime *rtd)
{
@ -213,6 +240,11 @@ static int bdw_rt5677_init(struct snd_soc_pcm_runtime *rtd)
rt5677_sel_asrc_clk_src(component, RT5677_DA_STEREO_FILTER |
RT5677_AD_STEREO1_FILTER | RT5677_I2S1_SOURCE,
RT5677_CLK_SEL_I2S1_ASRC);
/* Enable codec ASRC function for Mono ADC L.
* The ASRC clock source is clk_sys2_asrc.
*/
rt5677_sel_asrc_clk_src(component, RT5677_AD_MONO_L_FILTER,
RT5677_CLK_SEL_SYS2);
/* Request rt5677 GPIO for headphone amp control */
bdw_rt5677->gpio_hp_en = devm_gpiod_get(component->dev, "headphone-enable",
@ -291,6 +323,7 @@ static struct snd_soc_dai_link bdw_rt5677_dais[] = {
{
.name = "Codec DSP",
.stream_name = "Wake on Voice",
.ops = &bdw_rt5677_dsp_ops,
SND_SOC_DAILINK_REG(dsp),
},