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ARM: dts: imx: Add missing OPP properties for CPUs
The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing properties (like clocks, supply, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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77cf8a009d
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@ -51,6 +51,29 @@
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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996000 1250000
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792000 1175000
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396000 1150000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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996000 1175000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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};
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@ -187,6 +187,72 @@
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>;
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};
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&cpu1 {
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/*
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* Although the imx6q fuse indicates that 1.2GHz operation is possible,
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* the module behaves unstable at this frequency. Hence, remove the
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* 1.2GHz operation point here.
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*/
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operating-points = <
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/* kHz uV */
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996000 1250000
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852000 1250000
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792000 1175000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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996000 1250000
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852000 1250000
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792000 1175000
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396000 1175000
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>;
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};
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&cpu2 {
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/*
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* Although the imx6q fuse indicates that 1.2GHz operation is possible,
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* the module behaves unstable at this frequency. Hence, remove the
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* 1.2GHz operation point here.
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*/
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operating-points = <
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/* kHz uV */
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996000 1250000
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852000 1250000
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792000 1175000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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996000 1250000
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852000 1250000
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792000 1175000
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396000 1175000
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>;
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};
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&cpu3 {
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/*
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* Although the imx6q fuse indicates that 1.2GHz operation is possible,
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* the module behaves unstable at this frequency. Hence, remove the
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* 1.2GHz operation point here.
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*/
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operating-points = <
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/* kHz uV */
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996000 1250000
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852000 1250000
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792000 1175000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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996000 1250000
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852000 1250000
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792000 1175000
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396000 1175000
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>;
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};
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&ecspi1 {
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cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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@ -51,25 +51,106 @@
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soc-supply = <®_soc>;
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};
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cpu@1 {
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cpu1: cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu@2 {
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cpu2: cpu@2 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu@3 {
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cpu3: cpu@3 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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};
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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operating-points = <
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/* KHz uV */
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996000 1075000
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792000 975000
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>;
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clock-frequency = <996000000>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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