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Merge branch 'parisc-4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux
Pull parisc fixes from Helge Deller: "We have one important patch from Dave Anglin and myself which fixes PTE/TLB race conditions which caused random segmentation faults on our debian buildd servers, and one patch from Alex Ivanov which speeds up the graphical text console on the STI framebuffer driver" * 'parisc-4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: Fix some PTE/TLB race conditions and optimize __flush_tlb_range based on timing results stifb: Implement hardware accelerated copyarea
This commit is contained in:
Linus Torvalds
commit
b9243b5a5d
@ -16,7 +16,7 @@
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#include <asm/processor.h>
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#include <asm/cache.h>
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extern spinlock_t pa_dbit_lock;
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extern spinlock_t pa_tlb_lock;
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/*
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* kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
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@ -33,6 +33,19 @@ extern spinlock_t pa_dbit_lock;
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*/
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#define kern_addr_valid(addr) (1)
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/* Purge data and instruction TLB entries. Must be called holding
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* the pa_tlb_lock. The TLB purge instructions are slow on SMP
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* machines since the purge must be broadcast to all CPUs.
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*/
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static inline void purge_tlb_entries(struct mm_struct *mm, unsigned long addr)
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{
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mtsp(mm->context, 1);
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pdtlb(addr);
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if (unlikely(split_tlb))
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pitlb(addr);
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}
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/* Certain architectures need to do special things when PTEs
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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@ -42,15 +55,20 @@ extern spinlock_t pa_dbit_lock;
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*(pteptr) = (pteval); \
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} while(0)
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extern void purge_tlb_entries(struct mm_struct *, unsigned long);
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#define pte_inserted(x) \
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((pte_val(x) & (_PAGE_PRESENT|_PAGE_ACCESSED)) \
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== (_PAGE_PRESENT|_PAGE_ACCESSED))
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#define set_pte_at(mm, addr, ptep, pteval) \
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do { \
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#define set_pte_at(mm, addr, ptep, pteval) \
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do { \
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pte_t old_pte; \
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unsigned long flags; \
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spin_lock_irqsave(&pa_dbit_lock, flags); \
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set_pte(ptep, pteval); \
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purge_tlb_entries(mm, addr); \
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spin_unlock_irqrestore(&pa_dbit_lock, flags); \
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spin_lock_irqsave(&pa_tlb_lock, flags); \
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old_pte = *ptep; \
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set_pte(ptep, pteval); \
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if (pte_inserted(old_pte)) \
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purge_tlb_entries(mm, addr); \
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spin_unlock_irqrestore(&pa_tlb_lock, flags); \
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} while (0)
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#endif /* !__ASSEMBLY__ */
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@ -268,7 +286,7 @@ extern unsigned long *empty_zero_page;
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#define pte_none(x) (pte_val(x) == 0)
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#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
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#define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0)
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#define pte_clear(mm, addr, xp) set_pte_at(mm, addr, xp, __pte(0))
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#define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK)
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#define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
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@ -435,15 +453,15 @@ static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned
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if (!pte_young(*ptep))
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return 0;
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spin_lock_irqsave(&pa_dbit_lock, flags);
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spin_lock_irqsave(&pa_tlb_lock, flags);
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pte = *ptep;
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if (!pte_young(pte)) {
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spin_unlock_irqrestore(&pa_dbit_lock, flags);
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spin_unlock_irqrestore(&pa_tlb_lock, flags);
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return 0;
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}
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set_pte(ptep, pte_mkold(pte));
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purge_tlb_entries(vma->vm_mm, addr);
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spin_unlock_irqrestore(&pa_dbit_lock, flags);
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spin_unlock_irqrestore(&pa_tlb_lock, flags);
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return 1;
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}
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@ -453,11 +471,12 @@ static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
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pte_t old_pte;
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unsigned long flags;
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spin_lock_irqsave(&pa_dbit_lock, flags);
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spin_lock_irqsave(&pa_tlb_lock, flags);
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old_pte = *ptep;
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pte_clear(mm,addr,ptep);
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purge_tlb_entries(mm, addr);
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spin_unlock_irqrestore(&pa_dbit_lock, flags);
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set_pte(ptep, __pte(0));
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if (pte_inserted(old_pte))
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purge_tlb_entries(mm, addr);
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spin_unlock_irqrestore(&pa_tlb_lock, flags);
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return old_pte;
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}
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@ -465,10 +484,10 @@ static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
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static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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unsigned long flags;
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spin_lock_irqsave(&pa_dbit_lock, flags);
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spin_lock_irqsave(&pa_tlb_lock, flags);
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set_pte(ptep, pte_wrprotect(*ptep));
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purge_tlb_entries(mm, addr);
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spin_unlock_irqrestore(&pa_dbit_lock, flags);
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spin_unlock_irqrestore(&pa_tlb_lock, flags);
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}
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#define pte_same(A,B) (pte_val(A) == pte_val(B))
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@ -13,6 +13,9 @@
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* active at any one time on the Merced bus. This tlb purge
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* synchronisation is fairly lightweight and harmless so we activate
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* it on all systems not just the N class.
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* It is also used to ensure PTE updates are atomic and consistent
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* with the TLB.
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*/
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extern spinlock_t pa_tlb_lock;
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@ -24,20 +27,24 @@ extern void flush_tlb_all_local(void *);
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#define smp_flush_tlb_all() flush_tlb_all()
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int __flush_tlb_range(unsigned long sid,
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unsigned long start, unsigned long end);
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#define flush_tlb_range(vma, start, end) \
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__flush_tlb_range((vma)->vm_mm->context, start, end)
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#define flush_tlb_kernel_range(start, end) \
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__flush_tlb_range(0, start, end)
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/*
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* flush_tlb_mm()
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*
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* XXX This code is NOT valid for HP-UX compatibility processes,
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* (although it will probably work 99% of the time). HP-UX
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* processes are free to play with the space id's and save them
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* over long periods of time, etc. so we have to preserve the
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* space and just flush the entire tlb. We need to check the
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* personality in order to do that, but the personality is not
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* currently being set correctly.
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*
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* Of course, Linux processes could do the same thing, but
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* we don't support that (and the compilers, dynamic linker,
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* etc. do not do that).
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* The code to switch to a new context is NOT valid for processes
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* which play with the space id's. Thus, we have to preserve the
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* space and just flush the entire tlb. However, the compilers,
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* dynamic linker, etc, do not manipulate space id's, so there
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* could be a significant performance benefit in switching contexts
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* and not flushing the whole tlb.
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*/
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static inline void flush_tlb_mm(struct mm_struct *mm)
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@ -45,10 +52,18 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
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BUG_ON(mm == &init_mm); /* Should never happen */
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#if 1 || defined(CONFIG_SMP)
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/* Except for very small threads, flushing the whole TLB is
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* faster than using __flush_tlb_range. The pdtlb and pitlb
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* instructions are very slow because of the TLB broadcast.
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* It might be faster to do local range flushes on all CPUs
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* on PA 2.0 systems.
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*/
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flush_tlb_all();
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#else
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/* FIXME: currently broken, causing space id and protection ids
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* to go out of sync, resulting in faults on userspace accesses.
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* to go out of sync, resulting in faults on userspace accesses.
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* This approach needs further investigation since running many
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* small applications (e.g., GCC testsuite) is faster on HP-UX.
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*/
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if (mm) {
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if (mm->context != 0)
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@ -65,22 +80,12 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
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{
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unsigned long flags, sid;
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/* For one page, it's not worth testing the split_tlb variable */
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mb();
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sid = vma->vm_mm->context;
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purge_tlb_start(flags);
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mtsp(sid, 1);
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pdtlb(addr);
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pitlb(addr);
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if (unlikely(split_tlb))
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pitlb(addr);
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purge_tlb_end(flags);
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}
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void __flush_tlb_range(unsigned long sid,
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unsigned long start, unsigned long end);
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#define flush_tlb_range(vma,start,end) __flush_tlb_range((vma)->vm_mm->context,start,end)
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#define flush_tlb_kernel_range(start, end) __flush_tlb_range(0,start,end)
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#endif
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@ -342,12 +342,15 @@ EXPORT_SYMBOL(flush_data_cache_local);
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EXPORT_SYMBOL(flush_kernel_icache_range_asm);
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#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
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int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
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static unsigned long parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
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#define FLUSH_TLB_THRESHOLD (2*1024*1024) /* 2MB initial TLB threshold */
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static unsigned long parisc_tlb_flush_threshold __read_mostly = FLUSH_TLB_THRESHOLD;
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void __init parisc_setup_cache_timing(void)
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{
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unsigned long rangetime, alltime;
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unsigned long size;
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unsigned long size, start;
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alltime = mfctl(16);
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flush_data_cache();
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@ -364,14 +367,43 @@ void __init parisc_setup_cache_timing(void)
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/* Racy, but if we see an intermediate value, it's ok too... */
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parisc_cache_flush_threshold = size * alltime / rangetime;
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parisc_cache_flush_threshold = (parisc_cache_flush_threshold + L1_CACHE_BYTES - 1) &~ (L1_CACHE_BYTES - 1);
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parisc_cache_flush_threshold = L1_CACHE_ALIGN(parisc_cache_flush_threshold);
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if (!parisc_cache_flush_threshold)
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parisc_cache_flush_threshold = FLUSH_THRESHOLD;
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if (parisc_cache_flush_threshold > cache_info.dc_size)
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parisc_cache_flush_threshold = cache_info.dc_size;
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printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
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printk(KERN_INFO "Setting cache flush threshold to %lu kB\n",
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parisc_cache_flush_threshold/1024);
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/* calculate TLB flush threshold */
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alltime = mfctl(16);
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flush_tlb_all();
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alltime = mfctl(16) - alltime;
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size = PAGE_SIZE;
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start = (unsigned long) _text;
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rangetime = mfctl(16);
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while (start < (unsigned long) _end) {
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flush_tlb_kernel_range(start, start + PAGE_SIZE);
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start += PAGE_SIZE;
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size += PAGE_SIZE;
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}
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rangetime = mfctl(16) - rangetime;
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printk(KERN_DEBUG "Whole TLB flush %lu cycles, flushing %lu bytes %lu cycles\n",
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alltime, size, rangetime);
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parisc_tlb_flush_threshold = size * alltime / rangetime;
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parisc_tlb_flush_threshold *= num_online_cpus();
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parisc_tlb_flush_threshold = PAGE_ALIGN(parisc_tlb_flush_threshold);
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if (!parisc_tlb_flush_threshold)
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parisc_tlb_flush_threshold = FLUSH_TLB_THRESHOLD;
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printk(KERN_INFO "Setting TLB flush threshold to %lu kB\n",
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parisc_tlb_flush_threshold/1024);
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}
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extern void purge_kernel_dcache_page_asm(unsigned long);
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@ -403,48 +435,45 @@ void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
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}
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EXPORT_SYMBOL(copy_user_page);
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void purge_tlb_entries(struct mm_struct *mm, unsigned long addr)
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/* __flush_tlb_range()
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*
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* returns 1 if all TLBs were flushed.
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*/
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int __flush_tlb_range(unsigned long sid, unsigned long start,
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unsigned long end)
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{
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unsigned long flags;
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unsigned long flags, size;
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/* Note: purge_tlb_entries can be called at startup with
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no context. */
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purge_tlb_start(flags);
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mtsp(mm->context, 1);
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pdtlb(addr);
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pitlb(addr);
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purge_tlb_end(flags);
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}
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EXPORT_SYMBOL(purge_tlb_entries);
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void __flush_tlb_range(unsigned long sid, unsigned long start,
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unsigned long end)
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{
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unsigned long npages;
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npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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if (npages >= 512) /* 2MB of space: arbitrary, should be tuned */
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size = (end - start);
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if (size >= parisc_tlb_flush_threshold) {
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flush_tlb_all();
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else {
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unsigned long flags;
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return 1;
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}
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/* Purge TLB entries for small ranges using the pdtlb and
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pitlb instructions. These instructions execute locally
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but cause a purge request to be broadcast to other TLBs. */
|
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if (likely(!split_tlb)) {
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while (start < end) {
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purge_tlb_start(flags);
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mtsp(sid, 1);
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pdtlb(start);
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purge_tlb_end(flags);
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start += PAGE_SIZE;
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}
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return 0;
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}
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|
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/* split TLB case */
|
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while (start < end) {
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purge_tlb_start(flags);
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mtsp(sid, 1);
|
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if (split_tlb) {
|
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while (npages--) {
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pdtlb(start);
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pitlb(start);
|
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start += PAGE_SIZE;
|
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}
|
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} else {
|
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while (npages--) {
|
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pdtlb(start);
|
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start += PAGE_SIZE;
|
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}
|
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}
|
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pdtlb(start);
|
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pitlb(start);
|
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purge_tlb_end(flags);
|
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start += PAGE_SIZE;
|
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}
|
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return 0;
|
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}
|
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static void cacheflush_h_tmp_function(void *dummy)
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@ -45,7 +45,7 @@
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.level 2.0
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#endif
|
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.import pa_dbit_lock,data
|
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.import pa_tlb_lock,data
|
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|
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/* space_to_prot macro creates a prot id from a space id */
|
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|
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@ -420,8 +420,8 @@
|
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SHLREG %r9,PxD_VALUE_SHIFT,\pmd
|
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extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
|
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dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
|
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shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd
|
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LDREG %r0(\pmd),\pte /* pmd is now pte */
|
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shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd /* pmd is now pte */
|
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LDREG %r0(\pmd),\pte
|
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bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
|
||||
.endm
|
||||
|
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@ -453,57 +453,53 @@
|
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L2_ptep \pgd,\pte,\index,\va,\fault
|
||||
.endm
|
||||
|
||||
/* Acquire pa_dbit_lock lock. */
|
||||
.macro dbit_lock spc,tmp,tmp1
|
||||
/* Acquire pa_tlb_lock lock and recheck page is still present. */
|
||||
.macro tlb_lock spc,ptp,pte,tmp,tmp1,fault
|
||||
#ifdef CONFIG_SMP
|
||||
cmpib,COND(=),n 0,\spc,2f
|
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load32 PA(pa_dbit_lock),\tmp
|
||||
load32 PA(pa_tlb_lock),\tmp
|
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1: LDCW 0(\tmp),\tmp1
|
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cmpib,COND(=) 0,\tmp1,1b
|
||||
nop
|
||||
LDREG 0(\ptp),\pte
|
||||
bb,<,n \pte,_PAGE_PRESENT_BIT,2f
|
||||
b \fault
|
||||
stw \spc,0(\tmp)
|
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2:
|
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#endif
|
||||
.endm
|
||||
|
||||
/* Release pa_dbit_lock lock without reloading lock address. */
|
||||
.macro dbit_unlock0 spc,tmp
|
||||
/* Release pa_tlb_lock lock without reloading lock address. */
|
||||
.macro tlb_unlock0 spc,tmp
|
||||
#ifdef CONFIG_SMP
|
||||
or,COND(=) %r0,\spc,%r0
|
||||
stw \spc,0(\tmp)
|
||||
#endif
|
||||
.endm
|
||||
|
||||
/* Release pa_dbit_lock lock. */
|
||||
.macro dbit_unlock1 spc,tmp
|
||||
/* Release pa_tlb_lock lock. */
|
||||
.macro tlb_unlock1 spc,tmp
|
||||
#ifdef CONFIG_SMP
|
||||
load32 PA(pa_dbit_lock),\tmp
|
||||
dbit_unlock0 \spc,\tmp
|
||||
load32 PA(pa_tlb_lock),\tmp
|
||||
tlb_unlock0 \spc,\tmp
|
||||
#endif
|
||||
.endm
|
||||
|
||||
/* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
|
||||
* don't needlessly dirty the cache line if it was already set */
|
||||
.macro update_ptep spc,ptep,pte,tmp,tmp1
|
||||
#ifdef CONFIG_SMP
|
||||
or,COND(=) %r0,\spc,%r0
|
||||
LDREG 0(\ptep),\pte
|
||||
#endif
|
||||
.macro update_accessed ptp,pte,tmp,tmp1
|
||||
ldi _PAGE_ACCESSED,\tmp1
|
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or \tmp1,\pte,\tmp
|
||||
and,COND(<>) \tmp1,\pte,%r0
|
||||
STREG \tmp,0(\ptep)
|
||||
STREG \tmp,0(\ptp)
|
||||
.endm
|
||||
|
||||
/* Set the dirty bit (and accessed bit). No need to be
|
||||
* clever, this is only used from the dirty fault */
|
||||
.macro update_dirty spc,ptep,pte,tmp
|
||||
#ifdef CONFIG_SMP
|
||||
or,COND(=) %r0,\spc,%r0
|
||||
LDREG 0(\ptep),\pte
|
||||
#endif
|
||||
.macro update_dirty ptp,pte,tmp
|
||||
ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
|
||||
or \tmp,\pte,\pte
|
||||
STREG \pte,0(\ptep)
|
||||
STREG \pte,0(\ptp)
|
||||
.endm
|
||||
|
||||
/* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
|
||||
@ -1148,14 +1144,14 @@ dtlb_miss_20w:
|
||||
|
||||
L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_ptep spc,ptp,pte,t0,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20w
|
||||
update_accessed ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb spc,pte,prot
|
||||
|
||||
idtlbt pte,prot
|
||||
dbit_unlock1 spc,t0
|
||||
|
||||
tlb_unlock1 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1174,14 +1170,14 @@ nadtlb_miss_20w:
|
||||
|
||||
L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_ptep spc,ptp,pte,t0,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20w
|
||||
update_accessed ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb spc,pte,prot
|
||||
|
||||
idtlbt pte,prot
|
||||
dbit_unlock1 spc,t0
|
||||
|
||||
tlb_unlock1 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1202,20 +1198,20 @@ dtlb_miss_11:
|
||||
|
||||
L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_ptep spc,ptp,pte,t0,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_11
|
||||
update_accessed ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb_11 spc,pte,prot
|
||||
|
||||
mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
|
||||
mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
|
||||
mtsp spc,%sr1
|
||||
|
||||
idtlba pte,(%sr1,va)
|
||||
idtlbp prot,(%sr1,va)
|
||||
|
||||
mtsp t0, %sr1 /* Restore sr1 */
|
||||
dbit_unlock1 spc,t0
|
||||
mtsp t1, %sr1 /* Restore sr1 */
|
||||
|
||||
tlb_unlock1 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1235,21 +1231,20 @@ nadtlb_miss_11:
|
||||
|
||||
L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_ptep spc,ptp,pte,t0,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_11
|
||||
update_accessed ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb_11 spc,pte,prot
|
||||
|
||||
|
||||
mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
|
||||
mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
|
||||
mtsp spc,%sr1
|
||||
|
||||
idtlba pte,(%sr1,va)
|
||||
idtlbp prot,(%sr1,va)
|
||||
|
||||
mtsp t0, %sr1 /* Restore sr1 */
|
||||
dbit_unlock1 spc,t0
|
||||
mtsp t1, %sr1 /* Restore sr1 */
|
||||
|
||||
tlb_unlock1 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1269,16 +1264,16 @@ dtlb_miss_20:
|
||||
|
||||
L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_ptep spc,ptp,pte,t0,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20
|
||||
update_accessed ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb spc,pte,prot
|
||||
|
||||
f_extend pte,t0
|
||||
f_extend pte,t1
|
||||
|
||||
idtlbt pte,prot
|
||||
dbit_unlock1 spc,t0
|
||||
|
||||
tlb_unlock1 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1297,16 +1292,16 @@ nadtlb_miss_20:
|
||||
|
||||
L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_ptep spc,ptp,pte,t0,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20
|
||||
update_accessed ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb spc,pte,prot
|
||||
|
||||
f_extend pte,t0
|
||||
f_extend pte,t1
|
||||
|
||||
idtlbt pte,prot
|
||||
dbit_unlock1 spc,t0
|
||||
idtlbt pte,prot
|
||||
|
||||
tlb_unlock1 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1406,14 +1401,14 @@ itlb_miss_20w:
|
||||
|
||||
L3_ptep ptp,pte,t0,va,itlb_fault
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_ptep spc,ptp,pte,t0,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,itlb_fault
|
||||
update_accessed ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb spc,pte,prot
|
||||
|
||||
iitlbt pte,prot
|
||||
dbit_unlock1 spc,t0
|
||||
|
||||
tlb_unlock1 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1430,14 +1425,14 @@ naitlb_miss_20w:
|
||||
|
||||
L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_ptep spc,ptp,pte,t0,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20w
|
||||
update_accessed ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb spc,pte,prot
|
||||
|
||||
iitlbt pte,prot
|
||||
dbit_unlock1 spc,t0
|
||||
|
||||
tlb_unlock1 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1458,20 +1453,20 @@ itlb_miss_11:
|
||||
|
||||
L2_ptep ptp,pte,t0,va,itlb_fault
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_ptep spc,ptp,pte,t0,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,itlb_fault
|
||||
update_accessed ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb_11 spc,pte,prot
|
||||
|
||||
mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
|
||||
mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
|
||||
mtsp spc,%sr1
|
||||
|
||||
iitlba pte,(%sr1,va)
|
||||
iitlbp prot,(%sr1,va)
|
||||
|
||||
mtsp t0, %sr1 /* Restore sr1 */
|
||||
dbit_unlock1 spc,t0
|
||||
mtsp t1, %sr1 /* Restore sr1 */
|
||||
|
||||
tlb_unlock1 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1482,20 +1477,20 @@ naitlb_miss_11:
|
||||
|
||||
L2_ptep ptp,pte,t0,va,naitlb_check_alias_11
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_ptep spc,ptp,pte,t0,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_11
|
||||
update_accessed ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb_11 spc,pte,prot
|
||||
|
||||
mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
|
||||
mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
|
||||
mtsp spc,%sr1
|
||||
|
||||
iitlba pte,(%sr1,va)
|
||||
iitlbp prot,(%sr1,va)
|
||||
|
||||
mtsp t0, %sr1 /* Restore sr1 */
|
||||
dbit_unlock1 spc,t0
|
||||
mtsp t1, %sr1 /* Restore sr1 */
|
||||
|
||||
tlb_unlock1 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1516,16 +1511,16 @@ itlb_miss_20:
|
||||
|
||||
L2_ptep ptp,pte,t0,va,itlb_fault
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_ptep spc,ptp,pte,t0,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,itlb_fault
|
||||
update_accessed ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb spc,pte,prot
|
||||
|
||||
f_extend pte,t0
|
||||
f_extend pte,t1
|
||||
|
||||
iitlbt pte,prot
|
||||
dbit_unlock1 spc,t0
|
||||
|
||||
tlb_unlock1 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1536,16 +1531,16 @@ naitlb_miss_20:
|
||||
|
||||
L2_ptep ptp,pte,t0,va,naitlb_check_alias_20
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_ptep spc,ptp,pte,t0,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20
|
||||
update_accessed ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb spc,pte,prot
|
||||
|
||||
f_extend pte,t0
|
||||
f_extend pte,t1
|
||||
|
||||
iitlbt pte,prot
|
||||
dbit_unlock1 spc,t0
|
||||
|
||||
tlb_unlock1 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1568,14 +1563,14 @@ dbit_trap_20w:
|
||||
|
||||
L3_ptep ptp,pte,t0,va,dbit_fault
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_dirty spc,ptp,pte,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,dbit_fault
|
||||
update_dirty ptp,pte,t1
|
||||
|
||||
make_insert_tlb spc,pte,prot
|
||||
|
||||
idtlbt pte,prot
|
||||
dbit_unlock0 spc,t0
|
||||
|
||||
tlb_unlock0 spc,t0
|
||||
rfir
|
||||
nop
|
||||
#else
|
||||
@ -1588,8 +1583,8 @@ dbit_trap_11:
|
||||
|
||||
L2_ptep ptp,pte,t0,va,dbit_fault
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_dirty spc,ptp,pte,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,dbit_fault
|
||||
update_dirty ptp,pte,t1
|
||||
|
||||
make_insert_tlb_11 spc,pte,prot
|
||||
|
||||
@ -1600,8 +1595,8 @@ dbit_trap_11:
|
||||
idtlbp prot,(%sr1,va)
|
||||
|
||||
mtsp t1, %sr1 /* Restore sr1 */
|
||||
dbit_unlock0 spc,t0
|
||||
|
||||
tlb_unlock0 spc,t0
|
||||
rfir
|
||||
nop
|
||||
|
||||
@ -1612,16 +1607,16 @@ dbit_trap_20:
|
||||
|
||||
L2_ptep ptp,pte,t0,va,dbit_fault
|
||||
|
||||
dbit_lock spc,t0,t1
|
||||
update_dirty spc,ptp,pte,t1
|
||||
tlb_lock spc,ptp,pte,t0,t1,dbit_fault
|
||||
update_dirty ptp,pte,t1
|
||||
|
||||
make_insert_tlb spc,pte,prot
|
||||
|
||||
f_extend pte,t1
|
||||
|
||||
idtlbt pte,prot
|
||||
dbit_unlock0 spc,t0
|
||||
idtlbt pte,prot
|
||||
|
||||
tlb_unlock0 spc,t0
|
||||
rfir
|
||||
nop
|
||||
#endif
|
||||
|
||||
@ -43,10 +43,6 @@
|
||||
|
||||
#include "../math-emu/math-emu.h" /* for handle_fpe() */
|
||||
|
||||
#if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_SPINLOCK)
|
||||
DEFINE_SPINLOCK(pa_dbit_lock);
|
||||
#endif
|
||||
|
||||
static void parisc_show_stack(struct task_struct *task, unsigned long *sp,
|
||||
struct pt_regs *regs);
|
||||
|
||||
|
||||
@ -121,6 +121,7 @@ static int __initdata stifb_bpp_pref[MAX_STI_ROMS];
|
||||
#define REG_3 0x0004a0
|
||||
#define REG_4 0x000600
|
||||
#define REG_6 0x000800
|
||||
#define REG_7 0x000804
|
||||
#define REG_8 0x000820
|
||||
#define REG_9 0x000a04
|
||||
#define REG_10 0x018000
|
||||
@ -135,6 +136,8 @@ static int __initdata stifb_bpp_pref[MAX_STI_ROMS];
|
||||
#define REG_21 0x200218
|
||||
#define REG_22 0x0005a0
|
||||
#define REG_23 0x0005c0
|
||||
#define REG_24 0x000808
|
||||
#define REG_25 0x000b00
|
||||
#define REG_26 0x200118
|
||||
#define REG_27 0x200308
|
||||
#define REG_32 0x21003c
|
||||
@ -429,6 +432,9 @@ ARTIST_ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
|
||||
#define SET_LENXY_START_RECFILL(fb, lenxy) \
|
||||
WRITE_WORD(lenxy, fb, REG_9)
|
||||
|
||||
#define SETUP_COPYAREA(fb) \
|
||||
WRITE_BYTE(0, fb, REG_16b1)
|
||||
|
||||
static void
|
||||
HYPER_ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
|
||||
{
|
||||
@ -1004,6 +1010,36 @@ stifb_blank(int blank_mode, struct fb_info *info)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
stifb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
|
||||
{
|
||||
struct stifb_info *fb = container_of(info, struct stifb_info, info);
|
||||
|
||||
SETUP_COPYAREA(fb);
|
||||
|
||||
SETUP_HW(fb);
|
||||
if (fb->info.var.bits_per_pixel == 32) {
|
||||
WRITE_WORD(0xBBA0A000, fb, REG_10);
|
||||
|
||||
NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xffffffff);
|
||||
} else {
|
||||
WRITE_WORD(fb->id == S9000_ID_HCRX ? 0x13a02000 : 0x13a01000, fb, REG_10);
|
||||
|
||||
NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xff);
|
||||
}
|
||||
|
||||
NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb,
|
||||
IBOvals(RopSrc, MaskAddrOffset(0),
|
||||
BitmapExtent08, StaticReg(1),
|
||||
DataDynamic, MaskOtc, BGx(0), FGx(0)));
|
||||
|
||||
WRITE_WORD(((area->sx << 16) | area->sy), fb, REG_24);
|
||||
WRITE_WORD(((area->width << 16) | area->height), fb, REG_7);
|
||||
WRITE_WORD(((area->dx << 16) | area->dy), fb, REG_25);
|
||||
|
||||
SETUP_FB(fb);
|
||||
}
|
||||
|
||||
static void __init
|
||||
stifb_init_display(struct stifb_info *fb)
|
||||
{
|
||||
@ -1069,7 +1105,7 @@ static struct fb_ops stifb_ops = {
|
||||
.fb_setcolreg = stifb_setcolreg,
|
||||
.fb_blank = stifb_blank,
|
||||
.fb_fillrect = cfb_fillrect,
|
||||
.fb_copyarea = cfb_copyarea,
|
||||
.fb_copyarea = stifb_copyarea,
|
||||
.fb_imageblit = cfb_imageblit,
|
||||
};
|
||||
|
||||
@ -1258,7 +1294,7 @@ static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref)
|
||||
info->fbops = &stifb_ops;
|
||||
info->screen_base = ioremap_nocache(REGION_BASE(fb,1), fix->smem_len);
|
||||
info->screen_size = fix->smem_len;
|
||||
info->flags = FBINFO_DEFAULT;
|
||||
info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA;
|
||||
info->pseudo_palette = &fb->pseudo_palette;
|
||||
|
||||
/* This has to be done !!! */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user