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ath9k: Add power save wrappers and modularize hw_pll handler
We should protect hw_pll handler with power save wrappers and also modularize hw_pll handler properly for better readability. Also add a debug message to track chip resets on pll hang condition. Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -673,7 +673,7 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
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REGWRITE_BUFFER_FLUSH(ah);
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}
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unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
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u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
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{
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REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
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udelay(100);
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@ -932,7 +932,7 @@ void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
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void ath9k_hw_reset_tsf(struct ath_hw *ah);
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void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
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void ath9k_hw_init_global_settings(struct ath_hw *ah);
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unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
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u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
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void ath9k_hw_set11nmac2040(struct ath_hw *ah);
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void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
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void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
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@ -624,23 +624,37 @@ out:
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ath9k_ps_restore(sc);
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}
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static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
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{
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static int count;
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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if (pll_sqsum >= 0x40000) {
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count++;
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if (count == 3) {
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/* Rx is hung for more than 500ms. Reset it */
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ath_dbg(common, ATH_DBG_RESET,
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"Possible RX hang, resetting");
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ath_reset(sc, true);
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count = 0;
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}
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} else
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count = 0;
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}
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void ath_hw_pll_work(struct work_struct *work)
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{
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struct ath_softc *sc = container_of(work, struct ath_softc,
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hw_pll_work.work);
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static int count;
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u32 pll_sqsum;
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if (AR_SREV_9485(sc->sc_ah)) {
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if (ar9003_get_pll_sqsum_dvc(sc->sc_ah) >= 0x40000) {
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count++;
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if (count == 3) {
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/* Rx is hung for more than 500ms. Reset it */
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ath_reset(sc, true);
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count = 0;
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}
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} else
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count = 0;
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ath9k_ps_wakeup(sc);
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pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
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ath9k_ps_restore(sc);
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ath_hw_pll_rx_hang_check(sc, pll_sqsum);
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ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
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}
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