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Disintegrate asm/system.h for MIPS

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Disintegrate asm/system.h for MIPS.

Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
cc: linux-mips@linux-mips.org
This commit is contained in:
David Howells 2012-03-28 18:30:02 +01:00
parent c40d04df15
commit b81947c646
90 changed files with 262 additions and 309 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/mips/cavium-octeon/setup.c
View File

@ -24,7 +24,6 @@
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/smp-ops.h>
#include <asm/system.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/bootinfo.h>

2
arch/mips/cavium-octeon/smp.c
View File

@ -15,8 +15,8 @@
#include <linux/module.h>
#include <asm/mmu_context.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/setup.h>
#include <asm/octeon/octeon.h>

1
arch/mips/dec/ecc-berr.c
View File

@ -24,7 +24,6 @@
#include <asm/irq_regs.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/dec/ecc.h>

1
arch/mips/dec/kn01-berr.c
View File

@ -22,7 +22,6 @@
#include <asm/mipsregs.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/uaccess.h>

1
arch/mips/dec/kn02xa-berr.c
View File

@ -21,7 +21,6 @@
#include <asm/addrspace.h>
#include <asm/irq_regs.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/dec/kn02ca.h>

2
arch/mips/dec/wbflush.c
View File

@ -17,8 +17,8 @@
#include <linux/init.h>
#include <asm/bootinfo.h>
#include <asm/system.h>
#include <asm/wbflush.h>
#include <asm/barrier.h>
static void wbflush_kn01(void);
static void wbflush_kn210(void);

1
arch/mips/emma/markeins/irq.c
View File

@ -27,7 +27,6 @@
#include <linux/delay.h>
#include <asm/irq_cpu.h>
#include <asm/system.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>

1
arch/mips/fw/arc/misc.c
View File

@ -17,7 +17,6 @@
#include <asm/fw/arc/types.h>
#include <asm/sgialib.h>
#include <asm/bootinfo.h>
#include <asm/system.h>
VOID
ArcHalt(VOID)

2
arch/mips/include/asm/atomic.h
View File

@ -18,8 +18,8 @@
#include <linux/types.h>
#include <asm/barrier.h>
#include <asm/cpu-features.h>
#include <asm/cmpxchg.h>
#include <asm/war.h>
#include <asm/system.h>
#define ATOMIC_INIT(i) { (i) }

2
arch/mips/include/asm/barrier.h
View File

@ -8,6 +8,8 @@
#ifndef __ASM_BARRIER_H
#define __ASM_BARRIER_H
#include <asm/addrspace.h>
/*
* read_barrier_depends - Flush all pending reads that subsequents reads
* depend on.

124
arch/mips/include/asm/cmpxchg.h
View File

@ -9,6 +9,130 @@
#define __ASM_CMPXCHG_H
#include <linux/irqflags.h>
#include <asm/war.h>
static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
{
__u32 retval;
smp_mb__before_llsc();
if (kernel_uses_llsc && R10000_LLSC_WAR) {
unsigned long dummy;
__asm__ __volatile__(
" .set mips3 \n"
"1: ll %0, %3 # xchg_u32 \n"
" .set mips0 \n"
" move %2, %z4 \n"
" .set mips3 \n"
" sc %2, %1 \n"
" beqzl %2, 1b \n"
" .set mips0 \n"
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
: "R" (*m), "Jr" (val)
: "memory");
} else if (kernel_uses_llsc) {
unsigned long dummy;
do {
__asm__ __volatile__(
" .set mips3 \n"
" ll %0, %3 # xchg_u32 \n"
" .set mips0 \n"
" move %2, %z4 \n"
" .set mips3 \n"
" sc %2, %1 \n"
" .set mips0 \n"
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
: "R" (*m), "Jr" (val)
: "memory");
} while (unlikely(!dummy));
} else {
unsigned long flags;
raw_local_irq_save(flags);
retval = *m;
*m = val;
raw_local_irq_restore(flags); /* implies memory barrier */
}
smp_llsc_mb();
return retval;
}
#ifdef CONFIG_64BIT
static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
{
__u64 retval;
smp_mb__before_llsc();
if (kernel_uses_llsc && R10000_LLSC_WAR) {
unsigned long dummy;
__asm__ __volatile__(
" .set mips3 \n"
"1: lld %0, %3 # xchg_u64 \n"
" move %2, %z4 \n"
" scd %2, %1 \n"
" beqzl %2, 1b \n"
" .set mips0 \n"
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
: "R" (*m), "Jr" (val)
: "memory");
} else if (kernel_uses_llsc) {
unsigned long dummy;
do {
__asm__ __volatile__(
" .set mips3 \n"
" lld %0, %3 # xchg_u64 \n"
" move %2, %z4 \n"
" scd %2, %1 \n"
" .set mips0 \n"
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
: "R" (*m), "Jr" (val)
: "memory");
} while (unlikely(!dummy));
} else {
unsigned long flags;
raw_local_irq_save(flags);
retval = *m;
*m = val;
raw_local_irq_restore(flags); /* implies memory barrier */
}
smp_llsc_mb();
return retval;
}
#else
extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
#endif
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
switch (size) {
case 4:
return __xchg_u32(ptr, x);
case 8:
return __xchg_u64(ptr, x);
}
return x;
}
#define xchg(ptr, x) \
({ \
BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
\
((__typeof__(*(ptr))) \
__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
})
#define __HAVE_ARCH_CMPXCHG 1

1
arch/mips/include/asm/dma.h
View File

@ -15,7 +15,6 @@
#include <asm/io.h> /* need byte IO */
#include <linux/spinlock.h> /* And spinlocks */
#include <linux/delay.h>
#include <asm/system.h>
#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER

17
arch/mips/include/asm/exec.h Normal file
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@ -0,0 +1,17 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
* Copyright (C) 1996 by Paul M. Antoine
* Copyright (C) 1999 Silicon Graphics
* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc.
*/
#ifndef _ASM_EXEC_H
#define _ASM_EXEC_H
extern unsigned long arch_align_stack(unsigned long sp);
#endif /* _ASM_EXEC_H */

1
arch/mips/include/asm/mach-au1x00/au1000_dma.h
View File

@ -33,7 +33,6 @@
#include <linux/io.h> /* need byte IO */
#include <linux/spinlock.h> /* And spinlocks */
#include <linux/delay.h>
#include <asm/system.h>
#define NUM_AU1000_DMA_CHANNELS 8

7
arch/mips/include/asm/processor.h
View File

@ -19,7 +19,6 @@
#include <asm/cpu-info.h>
#include <asm/mipsregs.h>
#include <asm/prefetch.h>
#include <asm/system.h>
/*
* Return current * instruction pointer ("program counter").
@ -356,6 +355,12 @@ unsigned long get_wchan(struct task_struct *p);
#define ARCH_HAS_PREFETCHW
#define prefetchw(x) __builtin_prefetch((x), 1, 1)
/*
* See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
* systems.
*/
#define __ARCH_WANT_UNLOCKED_CTXSW
#endif
#endif /* _ASM_PROCESSOR_H */

11
arch/mips/include/asm/setup.h
View File

@ -5,6 +5,17 @@
#ifdef __KERNEL__
extern void setup_early_printk(void);
extern void set_handler(unsigned long offset, void *addr, unsigned long len);
extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
typedef void (*vi_handler_t)(void);
extern void *set_vi_handler(int n, vi_handler_t addr);
extern void *set_except_vector(int n, void *addr);
extern unsigned long ebase;
extern void per_cpu_trap_init(void);
#endif /* __KERNEL__ */
#endif /* __SETUP_H */

85
arch/mips/include/asm/switch_to.h Normal file
View File

@ -0,0 +1,85 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
* Copyright (C) 1996 by Paul M. Antoine
* Copyright (C) 1999 Silicon Graphics
* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc.
*/
#ifndef _ASM_SWITCH_TO_H
#define _ASM_SWITCH_TO_H
#include <asm/cpu-features.h>
#include <asm/watch.h>
#include <asm/dsp.h>
struct task_struct;
/*
* switch_to(n) should switch tasks to task nr n, first
* checking that n isn't the current task, in which case it does nothing.
*/
extern asmlinkage void *resume(void *last, void *next, void *next_ti);
extern unsigned int ll_bit;
extern struct task_struct *ll_task;
#ifdef CONFIG_MIPS_MT_FPAFF
/*
* Handle the scheduler resume end of FPU affinity management. We do this
* inline to try to keep the overhead down. If we have been forced to run on
* a "CPU" with an FPU because of a previous high level of FP computation,
* but did not actually use the FPU during the most recent time-slice (CU1
* isn't set), we undo the restriction on cpus_allowed.
*
* We're not calling set_cpus_allowed() here, because we have no need to
* force prompt migration - we're already switching the current CPU to a
* different thread.
*/
#define __mips_mt_fpaff_switch_to(prev) \
do { \
struct thread_info *__prev_ti = task_thread_info(prev); \
\
if (cpu_has_fpu && \
test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
(!(KSTK_STATUS(prev) & ST0_CU1))) { \
clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
prev->cpus_allowed = prev->thread.user_cpus_allowed; \
} \
next->thread.emulated_fp = 0; \
} while(0)
#else
#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
#endif
#define __clear_software_ll_bit() \
do { \
if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \
ll_bit = 0; \
} while (0)
#define switch_to(prev, next, last) \
do { \
__mips_mt_fpaff_switch_to(prev); \
if (cpu_has_dsp) \
__save_dsp(prev); \
__clear_software_ll_bit(); \
(last) = resume(prev, next, task_thread_info(next)); \
} while (0)
#define finish_arch_switch(prev) \
do { \
if (cpu_has_dsp) \
__restore_dsp(current); \
if (cpu_has_userlocal) \
write_c0_userlocal(current_thread_info()->tp_value); \
__restore_watch(); \
} while (0)
#endif /* _ASM_SWITCH_TO_H */

236
arch/mips/include/asm/system.h
View File

@ -1,235 +1,5 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
* Copyright (C) 1996 by Paul M. Antoine
* Copyright (C) 1999 Silicon Graphics
* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc.
*/
#ifndef _ASM_SYSTEM_H
#define _ASM_SYSTEM_H
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/irqflags.h>
#include <asm/addrspace.h>
/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
#include <asm/barrier.h>
#include <asm/cmpxchg.h>
#include <asm/cpu-features.h>
#include <asm/dsp.h>
#include <asm/watch.h>
#include <asm/war.h>
/*
* switch_to(n) should switch tasks to task nr n, first
* checking that n isn't the current task, in which case it does nothing.
*/
extern asmlinkage void *resume(void *last, void *next, void *next_ti);
struct task_struct;
extern unsigned int ll_bit;
extern struct task_struct *ll_task;
#ifdef CONFIG_MIPS_MT_FPAFF
/*
* Handle the scheduler resume end of FPU affinity management. We do this
* inline to try to keep the overhead down. If we have been forced to run on
* a "CPU" with an FPU because of a previous high level of FP computation,
* but did not actually use the FPU during the most recent time-slice (CU1
* isn't set), we undo the restriction on cpus_allowed.
*
* We're not calling set_cpus_allowed() here, because we have no need to
* force prompt migration - we're already switching the current CPU to a
* different thread.
*/
#define __mips_mt_fpaff_switch_to(prev) \
do { \
struct thread_info *__prev_ti = task_thread_info(prev); \
\
if (cpu_has_fpu && \
test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
(!(KSTK_STATUS(prev) & ST0_CU1))) { \
clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
prev->cpus_allowed = prev->thread.user_cpus_allowed; \
} \
next->thread.emulated_fp = 0; \
} while(0)
#else
#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
#endif
#define __clear_software_ll_bit() \
do { \
if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \
ll_bit = 0; \
} while (0)
#define switch_to(prev, next, last) \
do { \
__mips_mt_fpaff_switch_to(prev); \
if (cpu_has_dsp) \
__save_dsp(prev); \
__clear_software_ll_bit(); \
(last) = resume(prev, next, task_thread_info(next)); \
} while (0)
#define finish_arch_switch(prev) \
do { \
if (cpu_has_dsp) \
__restore_dsp(current); \
if (cpu_has_userlocal) \
write_c0_userlocal(current_thread_info()->tp_value); \
__restore_watch(); \
} while (0)
static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
{
__u32 retval;
smp_mb__before_llsc();
if (kernel_uses_llsc && R10000_LLSC_WAR) {
unsigned long dummy;
__asm__ __volatile__(
" .set mips3 \n"
"1: ll %0, %3 # xchg_u32 \n"
" .set mips0 \n"
" move %2, %z4 \n"
" .set mips3 \n"
" sc %2, %1 \n"
" beqzl %2, 1b \n"
" .set mips0 \n"
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
: "R" (*m), "Jr" (val)
: "memory");
} else if (kernel_uses_llsc) {
unsigned long dummy;
do {
__asm__ __volatile__(
" .set mips3 \n"
" ll %0, %3 # xchg_u32 \n"
" .set mips0 \n"
" move %2, %z4 \n"
" .set mips3 \n"
" sc %2, %1 \n"
" .set mips0 \n"
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
: "R" (*m), "Jr" (val)
: "memory");
} while (unlikely(!dummy));
} else {
unsigned long flags;
raw_local_irq_save(flags);
retval = *m;
*m = val;
raw_local_irq_restore(flags); /* implies memory barrier */
}
smp_llsc_mb();
return retval;
}
#ifdef CONFIG_64BIT
static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
{
__u64 retval;
smp_mb__before_llsc();
if (kernel_uses_llsc && R10000_LLSC_WAR) {
unsigned long dummy;
__asm__ __volatile__(
" .set mips3 \n"
"1: lld %0, %3 # xchg_u64 \n"
" move %2, %z4 \n"
" scd %2, %1 \n"
" beqzl %2, 1b \n"
" .set mips0 \n"
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
: "R" (*m), "Jr" (val)
: "memory");
} else if (kernel_uses_llsc) {
unsigned long dummy;
do {
__asm__ __volatile__(
" .set mips3 \n"
" lld %0, %3 # xchg_u64 \n"
" move %2, %z4 \n"
" scd %2, %1 \n"
" .set mips0 \n"
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
: "R" (*m), "Jr" (val)
: "memory");
} while (unlikely(!dummy));
} else {
unsigned long flags;
raw_local_irq_save(flags);
retval = *m;
*m = val;
raw_local_irq_restore(flags); /* implies memory barrier */
}
smp_llsc_mb();
return retval;
}
#else
extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
#endif
static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
{
switch (size) {
case 4:
return __xchg_u32(ptr, x);
case 8:
return __xchg_u64(ptr, x);
}
return x;
}
#define xchg(ptr, x) \
({ \
BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
\
((__typeof__(*(ptr))) \
__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
})
extern void set_handler(unsigned long offset, void *addr, unsigned long len);
extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
typedef void (*vi_handler_t)(void);
extern void *set_vi_handler(int n, vi_handler_t addr);
extern void *set_except_vector(int n, void *addr);
extern unsigned long ebase;
extern void per_cpu_trap_init(void);
/*
* See include/asm-ia64/system.h; prevents deadlock on SMP
* systems.
*/
#define __ARCH_WANT_UNLOCKED_CTXSW
extern unsigned long arch_align_stack(unsigned long sp);
#endif /* _ASM_SYSTEM_H */
#include <asm/exec.h>
#include <asm/switch_to.h>

1
arch/mips/include/asm/txx9/jmr3927.h
View File

@ -12,7 +12,6 @@
#include <asm/txx9/tx3927.h>
#include <asm/addrspace.h>
#include <asm/system.h>
#include <asm/txx9irq.h>
/* CS */

2
arch/mips/kernel/cpu-bugs64.c
View File

@ -16,7 +16,7 @@
#include <asm/cpu.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/setup.h>
static char bug64hit[] __initdata =
"reliable operation impossible!\n%s";

1
arch/mips/kernel/cpu-probe.c
View File

@ -22,7 +22,6 @@
#include <asm/cpu.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/watch.h>
#include <asm/elf.h>
#include <asm/spram.h>

1
arch/mips/kernel/irq-rm7000.c
View File

@ -16,7 +16,6 @@
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
static inline void unmask_rm7k_irq(struct irq_data *d)
{

1
arch/mips/kernel/irq-rm9000.c
View File

@ -17,7 +17,6 @@
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
static inline void unmask_rm9k_irq(struct irq_data *d)
{

1
arch/mips/kernel/irq.c
View File

@ -23,7 +23,6 @@
#include <linux/ftrace.h>
#include <linux/atomic.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#ifdef CONFIG_KGDB

1
arch/mips/kernel/irq_cpu.c
View File

@ -35,7 +35,6 @@
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/system.h>
static inline void unmask_mips_irq(struct irq_data *d)
{

1
arch/mips/kernel/mips-mt.c
View File

@ -13,7 +13,6 @@
#include <asm/cpu.h>
#include <asm/processor.h>
#include <linux/atomic.h>
#include <asm/system.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/mipsmtregs.h>

1
arch/mips/kernel/process.c
View File

@ -32,7 +32,6 @@
#include <asm/dsp.h>
#include <asm/fpu.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/mipsregs.h>
#include <asm/processor.h>
#include <asm/uaccess.h>

1
arch/mips/kernel/ptrace.c
View File

@ -34,7 +34,6 @@
#include <asm/mipsmtregs.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/bootinfo.h>
#include <asm/reg.h>

1
arch/mips/kernel/ptrace32.c
View File

@ -32,7 +32,6 @@
#include <asm/mipsmtregs.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/bootinfo.h>

1
arch/mips/kernel/rtlx.c
View File

@ -38,7 +38,6 @@
#include <linux/atomic.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/vpe.h>
#include <asm/rtlx.h>

1
arch/mips/kernel/setup.c
View File

@ -31,7 +31,6 @@
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/smp-ops.h>
#include <asm/system.h>
#include <asm/prom.h>
struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly;

1
arch/mips/kernel/signal.c
View File

@ -34,6 +34,7 @@
#include <asm/cpu-features.h>
#include <asm/war.h>
#include <asm/vdso.h>
#include <asm/dsp.h>
#include "signal-common.h"

2
arch/mips/kernel/signal32.c
View File

@ -29,10 +29,10 @@
#include <asm/cacheflush.h>
#include <asm/sim.h>
#include <asm/ucontext.h>
#include <asm/system.h>
#include <asm/fpu.h>
#include <asm/war.h>
#include <asm/vdso.h>
#include <asm/dsp.h>
#include "signal-common.h"

1
arch/mips/kernel/signal_n32.c
View File

@ -35,7 +35,6 @@
#include <asm/sim.h>
#include <asm/uaccess.h>
#include <asm/ucontext.h>
#include <asm/system.h>
#include <asm/fpu.h>
#include <asm/cpu-features.h>
#include <asm/war.h>

1
arch/mips/kernel/smp-bmips.c
View File

@ -28,7 +28,6 @@
#include <asm/time.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/bootinfo.h>
#include <asm/pmon.h>
#include <asm/cacheflush.h>

1
arch/mips/kernel/smp-cmp.c
View File

@ -29,7 +29,6 @@
#include <asm/cacheflush.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>

1
arch/mips/kernel/smp-mt.c
View File

@ -28,7 +28,6 @@
#include <asm/cacheflush.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/time.h>

2
arch/mips/kernel/smp.c
View File

@ -38,9 +38,9 @@
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/r4k-timer.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
#include <asm/time.h>
#include <asm/setup.h>
#ifdef CONFIG_MIPS_MT_SMTC
#include <asm/mipsmtregs.h>

1
arch/mips/kernel/smtc-proc.c
View File

@ -11,7 +11,6 @@
#include <asm/cpu.h>
#include <asm/processor.h>
#include <linux/atomic.h>
#include <asm/system.h>
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/mipsregs.h>

1
arch/mips/kernel/smtc.c
View File

@ -31,7 +31,6 @@
#include <asm/cpu.h>
#include <asm/processor.h>
#include <linux/atomic.h>
#include <asm/system.h>
#include <asm/hardirq.h>
#include <asm/hazards.h>
#include <asm/irq.h>

1
arch/mips/kernel/spram.c
View File

@ -15,7 +15,6 @@
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/r4kcache.h>
#include <asm/hazards.h>

1
arch/mips/kernel/syscall.c
View File

@ -37,6 +37,7 @@
#include <asm/shmparam.h>
#include <asm/sysmips.h>
#include <asm/uaccess.h>
#include <asm/switch_to.h>
/*
* For historic reasons the pipe(2) syscall on MIPS has an unusual calling

1
arch/mips/kernel/traps.c
View File

@ -45,7 +45,6 @@
#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include <asm/sections.h>
#include <asm/system.h>
#include <asm/tlbdebug.h>
#include <asm/traps.h>
#include <asm/uaccess.h>

1
arch/mips/kernel/unaligned.c
View File

@ -85,7 +85,6 @@
#include <asm/cop2.h>
#include <asm/inst.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#define STR(x) __STR(x)
#define __STR(x) #x

1
arch/mips/kernel/vpe.c
View File

@ -49,7 +49,6 @@
#include <asm/cpu.h>
#include <asm/mips_mt.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/vpe.h>
#include <asm/kspd.h>

1
arch/mips/lasat/reset.c
View File

@ -21,7 +21,6 @@
#include <linux/pm.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <asm/lasat/lasat.h>
#include "picvue.h"

1
arch/mips/math-emu/dsemul.c
View File

@ -12,7 +12,6 @@
#include <asm/uaccess.h>
#include <asm/branch.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/cacheflush.h>
#include <asm/fpu_emulator.h>

1
arch/mips/mipssim/sim_smtc.c
View File

@ -28,7 +28,6 @@
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/smtc.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
#include <asm/smtc_ipi.h>

1
arch/mips/mipssim/sim_time.c
View File

@ -11,6 +11,7 @@
#include <asm/hardirq.h>
#include <asm/div64.h>
#include <asm/cpu.h>
#include <asm/setup.h>
#include <asm/time.h>
#include <asm/irq.h>
#include <asm/mc146818-time.h>

1
arch/mips/mm/c-octeon.c
View File

@ -21,7 +21,6 @@
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/r4kcache.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
#include <asm/war.h>

1
arch/mips/mm/c-r3k.c
View File

@ -18,7 +18,6 @@
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mmu_context.h>
#include <asm/system.h>
#include <asm/isadep.h>
#include <asm/io.h>
#include <asm/bootinfo.h>

1
arch/mips/mm/c-r4k.c
View File

@ -29,7 +29,6 @@
#include <asm/pgtable.h>
#include <asm/r4kcache.h>
#include <asm/sections.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
#include <asm/war.h>
#include <asm/cacheflush.h> /* for run_uncached() */

1
arch/mips/mm/c-tx39.c
View File

@ -18,7 +18,6 @@
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mmu_context.h>
#include <asm/system.h>
#include <asm/isadep.h>
#include <asm/io.h>
#include <asm/bootinfo.h>

1
arch/mips/mm/fault.c
View File

@ -22,7 +22,6 @@
#include <asm/branch.h>
#include <asm/mmu_context.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/ptrace.h>
#include <asm/highmem.h> /* For VMALLOC_END */

1
arch/mips/mm/page.c
View File

@ -22,7 +22,6 @@
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/prefetch.h>
#include <asm/system.h>
#include <asm/bootinfo.h>
#include <asm/mipsregs.h>
#include <asm/mmu_context.h>

1
arch/mips/mm/sc-ip22.c
View File

@ -12,7 +12,6 @@
#include <asm/bcache.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/bootinfo.h>
#include <asm/sgi/ip22.h>
#include <asm/sgi/mc.h>

1
arch/mips/mm/sc-mips.c
View File

@ -11,7 +11,6 @@
#include <asm/cacheops.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
#include <asm/r4kcache.h>

1
arch/mips/mm/sc-r5k.c
View File

@ -12,7 +12,6 @@
#include <asm/cacheops.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
#include <asm/r4kcache.h>

1
arch/mips/mm/tlb-r3k.c
View File

@ -19,7 +19,6 @@
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mmu_context.h>
#include <asm/system.h>
#include <asm/tlbmisc.h>
#include <asm/isadep.h>
#include <asm/io.h>

1
arch/mips/mm/tlb-r4k.c
View File

@ -18,7 +18,6 @@
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/tlbmisc.h>
extern void build_tlb_refill_handler(void);

1
arch/mips/mm/tlb-r8k.c
View File

@ -17,7 +17,6 @@
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/system.h>
extern void build_tlb_refill_handler(void);

1
arch/mips/mm/tlbex.c
View File

@ -32,6 +32,7 @@
#include <asm/pgtable.h>
#include <asm/war.h>
#include <asm/uasm.h>
#include <asm/setup.h>
/*
* TLB load/store/modify handlers.

1
arch/mips/mti-malta/malta-init.c
View File

@ -26,7 +26,6 @@
#include <asm/bootinfo.h>
#include <asm/gt64120.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/cacheflush.h>
#include <asm/smp-ops.h>
#include <asm/traps.h>

1
arch/mips/mti-malta/malta-int.c
View File

@ -44,6 +44,7 @@
#include <asm/msc01_ic.h>
#include <asm/gic.h>
#include <asm/gcmpregs.h>
#include <asm/setup.h>
int gcmp_present = -1;
int gic_present;

1
arch/mips/mti-malta/malta-time.c
View File

@ -35,6 +35,7 @@
#include <asm/irq.h>
#include <asm/div64.h>
#include <asm/cpu.h>
#include <asm/setup.h>
#include <asm/time.h>
#include <asm/mc146818-time.h>
#include <asm/msc01_ic.h>

1
arch/mips/netlogic/common/irq.c
View File

@ -43,7 +43,6 @@
#include <asm/errno.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/ptrace.h>
#include <asm/mipsregs.h>
#include <asm/thread_info.h>

1
arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
View File

@ -16,7 +16,6 @@
#include <linux/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <msp_cic_int.h>
#include <msp_regs.h>

1
arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
View File

@ -16,7 +16,6 @@
#include <linux/bitops.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <msp_cic_int.h>
#include <msp_regs.h>

1
arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
View File

@ -16,7 +16,6 @@
#include <linux/bitops.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <msp_slp_int.h>
#include <msp_regs.h>

1
arch/mips/pmc-sierra/yosemite/irq.c
View File

@ -44,7 +44,6 @@
#include <asm/irq.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/titan_dep.h>
/* Hypertransport specific */

1
arch/mips/pmc-sierra/yosemite/prom.c
View File

@ -20,7 +20,6 @@
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/smp-ops.h>
#include <asm/system.h>
#include <asm/bootinfo.h>
#include <asm/pmon.h>

1
arch/mips/pnx833x/common/interrupts.c
View File

@ -25,6 +25,7 @@
#include <linux/interrupt.h>
#include <asm/mipsregs.h>
#include <asm/irq_cpu.h>
#include <asm/setup.h>
#include <irq.h>
#include <irq-mapping.h>
#include <gpio.h>

1
arch/mips/powertv/asic/asic_int.c
View File

@ -34,6 +34,7 @@
#include <asm/irq_cpu.h>
#include <linux/io.h>
#include <asm/irq_regs.h>
#include <asm/setup.h>
#include <asm/mips-boards/generic.h>
#include <asm/mach-powertv/asic_regs.h>

1
arch/mips/powertv/asic/irq_asic.c
View File

@ -17,7 +17,6 @@
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/mach-powertv/asic_regs.h>

1
arch/mips/powertv/init.c
View File

@ -26,7 +26,6 @@
#include <asm/bootinfo.h>
#include <linux/io.h>
#include <asm/system.h>
#include <asm/cacheflush.h>
#include <asm/traps.h>

1
arch/mips/rb532/irq.c
View File

@ -42,7 +42,6 @@
#include <asm/bootinfo.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/mach-rc32434/irq.h>
#include <asm/mach-rc32434/gpio.h>

1
arch/mips/sgi-ip22/ip22-berr.c
View File

@ -9,7 +9,6 @@
#include <linux/sched.h>
#include <asm/addrspace.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/branch.h>
#include <asm/irq_regs.h>

1
arch/mips/sgi-ip22/ip22-reset.c
View File

@ -18,7 +18,6 @@
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/reboot.h>
#include <asm/sgialib.h>
#include <asm/sgi/ioc.h>

1
arch/mips/sgi-ip22/ip28-berr.c
View File

@ -11,7 +11,6 @@
#include <linux/seq_file.h>
#include <asm/addrspace.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/branch.h>
#include <asm/irq_regs.h>

1
arch/mips/sgi-ip27/ip27-irq.c
View File

@ -27,7 +27,6 @@
#include <asm/bootinfo.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/processor.h>
#include <asm/pci/bridge.h>

1
arch/mips/sgi-ip27/ip27-reset.c
View File

@ -19,7 +19,6 @@
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <asm/sgialib.h>
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>

1
arch/mips/sgi-ip32/ip32-irq.c
View File

@ -22,7 +22,6 @@
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/ip32/crime.h>
#include <asm/ip32/mace.h>

1
arch/mips/sgi-ip32/ip32-reset.c
View File

@ -20,7 +20,6 @@
#include <asm/addrspace.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <asm/wbflush.h>
#include <asm/ip32/mace.h>
#include <asm/ip32/crime.h>

1
arch/mips/sibyte/bcm1480/irq.c
View File

@ -27,7 +27,6 @@
#include <asm/errno.h>
#include <asm/irq_regs.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/sibyte/bcm1480_regs.h>

1
arch/mips/sibyte/common/sb_tbprof.c
View File

@ -53,7 +53,6 @@
#define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT
#endif
#include <asm/system.h>
#include <asm/uaccess.h>
#define SBPROF_TB_MAJOR 240

1
arch/mips/sibyte/sb1250/bus_watcher.c
View File

@ -30,7 +30,6 @@
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/sibyte/sb1250.h>

1
arch/mips/sibyte/sb1250/irq.c
View File

@ -26,7 +26,6 @@
#include <asm/errno.h>
#include <asm/signal.h>
#include <asm/system.h>
#include <asm/time.h>
#include <asm/io.h>

1
arch/mips/sni/reset.c
View File

@ -5,7 +5,6 @@
*/
#include <asm/io.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <asm/sni.h>
/*

1
arch/mips/vr41xx/common/irq.c
View File

@ -22,7 +22,6 @@
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <asm/system.h>
#include <asm/vr41xx/irq.h>
typedef struct irq_cascade {

1
arch/mips/vr41xx/common/pmu.c
View File

@ -30,7 +30,6 @@
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
#define PMU_TYPE1_BASE 0x0b0000a0UL
#define PMU_TYPE1_SIZE 0x0eUL